2024-05-23 12:22:04

by Seongsu Park

Subject: [PATCH] arm64: Cleanup __cpu_set_tcr_t0sz()

The T0SZ field of TCR_EL1 occupies bits 0-5 of the register and encode
the virtual address space translated by TTBR0_EL1. When updating the
field, for example because we are switching to/from the idmap page-table,
__cpu_set_tcr_t0sz() erroneously treats its 't0sz' argument as unshifted,
resulting in harmless but confusing double shifts by 0 in the code.

Co-developed-by: Leem ChaeHoon <[email protected]>
Signed-off-by: Leem ChaeHoon <[email protected]>
Signed-off-by: Seongsu Park <[email protected]>
---
arch/arm64/include/asm/mmu_context.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/include/asm/mmu_context.h b/arch/arm64/include/asm/mmu_context.h
index c768d16b81a4..bd19f4c758b7 100644
--- a/arch/arm64/include/asm/mmu_context.h
+++ b/arch/arm64/include/asm/mmu_context.h
@@ -72,11 +72,11 @@ static inline void __cpu_set_tcr_t0sz(unsigned long t0sz)
{
unsigned long tcr = read_sysreg(tcr_el1);

- if ((tcr & TCR_T0SZ_MASK) >> TCR_T0SZ_OFFSET == t0sz)
+ if ((tcr & TCR_T0SZ_MASK) == t0sz)
return;

tcr &= ~TCR_T0SZ_MASK;
- tcr |= t0sz << TCR_T0SZ_OFFSET;
+ tcr |= t0sz;
write_sysreg(tcr, tcr_el1);
isb();
}
--
2.34.1

2024-06-03 11:12:18

by Seongsu Park

Subject: RE: [PATCH] arm64: Cleanup __cpu_set_tcr_t0sz()

Dear All,

Please check this patch.
I think this patch is appropriate.

Thanks.
Seongsu Park.

> -----Original Message-----
> From: Seongsu Park <[email protected]>
> Sent: Thursday, May 23, 2024 9:22 PM
> To: [email protected]; [email protected]; [email protected];
> [email protected]
> Cc: [email protected]; [email protected];
> [email protected]; [email protected]
> Subject: [PATCH] arm64: Cleanup __cpu_set_tcr_t0sz()
>
> The T0SZ field of TCR_EL1 occupies bits 0-5 of the register and encode the
> virtual address space translated by TTBR0_EL1. When updating the field,
> for example because we are switching to/from the idmap page-table,
> __cpu_set_tcr_t0sz() erroneously treats its 't0sz' argument as unshifted,
> resulting in harmless but confusing double shifts by 0 in the code.
>
> Co-developed-by: Leem ChaeHoon <[email protected]>
> Signed-off-by: Leem ChaeHoon <[email protected]>
> Signed-off-by: Seongsu Park <[email protected]>
> ---
> arch/arm64/include/asm/mmu_context.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/include/asm/mmu_context.h
> b/arch/arm64/include/asm/mmu_context.h
> index c768d16b81a4..bd19f4c758b7 100644
> --- a/arch/arm64/include/asm/mmu_context.h
> +++ b/arch/arm64/include/asm/mmu_context.h
> @@ -72,11 +72,11 @@ static inline void __cpu_set_tcr_t0sz(unsigned long
> t0sz) {
> unsigned long tcr = read_sysreg(tcr_el1);
>
> - if ((tcr & TCR_T0SZ_MASK) >> TCR_T0SZ_OFFSET == t0sz)
> + if ((tcr & TCR_T0SZ_MASK) == t0sz)
> return;
>
> tcr &= ~TCR_T0SZ_MASK;
> - tcr |= t0sz << TCR_T0SZ_OFFSET;
> + tcr |= t0sz;
> write_sysreg(tcr, tcr_el1);
> isb();
> }
> --
> 2.34.1