Add support for PIL loading of WPSS co-processor for SC7280 SOCs.
Changes from v2:
- Add support to vote for multiple power domain
- Fix dt-bindings error
- Vote for load_state
Rakesh Pillai (3):
dt-bindings: remoteproc: qcom: adsp: Convert binding to YAML
dt-bindings: remoteproc: qcom: Add SC7280 WPSS support
remoteproc: qcom: q6v5_wpss: Add support for sc7280 WPSS
.../bindings/remoteproc/qcom,hexagon-v56.txt | 140 --------
.../bindings/remoteproc/qcom,hexagon-v56.yaml | 351 +++++++++++++++++++++
drivers/remoteproc/qcom_q6v5_adsp.c | 141 ++++++++-
3 files changed, 489 insertions(+), 143 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/remoteproc/qcom,hexagon-v56.txt
create mode 100644 Documentation/devicetree/bindings/remoteproc/qcom,hexagon-v56.yaml
--
2.7.4
Convert Qualcomm ADSP/CDSP Remoteproc devicetree
binding to YAML.
Signed-off-by: Rakesh Pillai <[email protected]>
---
.../bindings/remoteproc/qcom,hexagon-v56.txt | 140 -----------
.../bindings/remoteproc/qcom,hexagon-v56.yaml | 267 +++++++++++++++++++++
2 files changed, 267 insertions(+), 140 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/remoteproc/qcom,hexagon-v56.txt
create mode 100644 Documentation/devicetree/bindings/remoteproc/qcom,hexagon-v56.yaml
diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,hexagon-v56.txt b/Documentation/devicetree/bindings/remoteproc/qcom,hexagon-v56.txt
deleted file mode 100644
index 1337a3d..0000000
--- a/Documentation/devicetree/bindings/remoteproc/qcom,hexagon-v56.txt
+++ /dev/null
@@ -1,140 +0,0 @@
-Qualcomm Technology Inc. Hexagon v56 Peripheral Image Loader
-
-This document defines the binding for a component that loads and boots firmware
-on the Qualcomm Technology Inc. Hexagon v56 core.
-
-- compatible:
- Usage: required
- Value type: <string>
- Definition: must be one of:
- "qcom,qcs404-cdsp-pil",
- "qcom,sdm845-adsp-pil"
-
-- reg:
- Usage: required
- Value type: <prop-encoded-array>
- Definition: must specify the base address and size of the qdsp6ss register
-
-- interrupts-extended:
- Usage: required
- Value type: <prop-encoded-array>
- Definition: must list the watchdog, fatal IRQs ready, handover and
- stop-ack IRQs
-
-- interrupt-names:
- Usage: required
- Value type: <stringlist>
- Definition: must be "wdog", "fatal", "ready", "handover", "stop-ack"
-
-- clocks:
- Usage: required
- Value type: <prop-encoded-array>
- Definition: List of phandles and clock specifier pairs for the Hexagon,
- per clock-names below.
-
-- clock-names:
- Usage: required for SDM845 ADSP
- Value type: <stringlist>
- Definition: List of clock input name strings sorted in the same
- order as the clocks property. Definition must have
- "xo", "sway_cbcr", "lpass_ahbs_aon_cbcr",
- "lpass_ahbm_aon_cbcr", "qdsp6ss_xo", "qdsp6ss_sleep"
- and "qdsp6ss_core".
-
-- clock-names:
- Usage: required for QCS404 CDSP
- Value type: <stringlist>
- Definition: List of clock input name strings sorted in the same
- order as the clocks property. Definition must have
- "xo", "sway", "tbu", "bimc", "ahb_aon", "q6ss_slave",
- "q6ss_master", "q6_axim".
-
-- power-domains:
- Usage: required
- Value type: <phandle>
- Definition: reference to cx power domain node.
-
-- resets:
- Usage: required
- Value type: <phandle>
- Definition: reference to the list of resets for the Hexagon.
-
-- reset-names:
- Usage: required for SDM845 ADSP
- Value type: <stringlist>
- Definition: must be "pdc_sync" and "cc_lpass"
-
-- reset-names:
- Usage: required for QCS404 CDSP
- Value type: <stringlist>
- Definition: must be "restart"
-
-- qcom,halt-regs:
- Usage: required
- Value type: <prop-encoded-array>
- Definition: a phandle reference to a syscon representing TCSR followed
- by the offset within syscon for Hexagon halt register.
-
-- memory-region:
- Usage: required
- Value type: <phandle>
- Definition: reference to the reserved-memory for the firmware
-
-- qcom,smem-states:
- Usage: required
- Value type: <phandle>
- Definition: reference to the smem state for requesting the Hexagon to
- shut down
-
-- qcom,smem-state-names:
- Usage: required
- Value type: <stringlist>
- Definition: must be "stop"
-
-
-= SUBNODES
-The adsp node may have an subnode named "glink-edge" that describes the
-communication edge, channels and devices related to the Hexagon.
-See ../soc/qcom/qcom,glink.txt for details on how to describe these.
-
-= EXAMPLE
-The following example describes the resources needed to boot control the
-ADSP, as it is found on SDM845 boards.
-
- remoteproc@17300000 {
- compatible = "qcom,sdm845-adsp-pil";
- reg = <0x17300000 0x40c>;
-
- interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
- <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
- <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
- <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
- <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "wdog", "fatal", "ready",
- "handover", "stop-ack";
-
- clocks = <&rpmhcc RPMH_CXO_CLK>,
- <&gcc GCC_LPASS_SWAY_CLK>,
- <&lpasscc LPASS_Q6SS_AHBS_AON_CLK>,
- <&lpasscc LPASS_Q6SS_AHBM_AON_CLK>,
- <&lpasscc LPASS_QDSP6SS_XO_CLK>,
- <&lpasscc LPASS_QDSP6SS_SLEEP_CLK>,
- <&lpasscc LPASS_QDSP6SS_CORE_CLK>;
- clock-names = "xo", "sway_cbcr",
- "lpass_ahbs_aon_cbcr",
- "lpass_ahbm_aon_cbcr", "qdsp6ss_xo",
- "qdsp6ss_sleep", "qdsp6ss_core";
-
- power-domains = <&rpmhpd SDM845_CX>;
-
- resets = <&pdc_reset PDC_AUDIO_SYNC_RESET>,
- <&aoss_reset AOSS_CC_LPASS_RESTART>;
- reset-names = "pdc_sync", "cc_lpass";
-
- qcom,halt-regs = <&tcsr_mutex_regs 0x22000>;
-
- memory-region = <&pil_adsp_mem>;
-
- qcom,smem-states = <&adsp_smp2p_out 0>;
- qcom,smem-state-names = "stop";
- };
diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,hexagon-v56.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,hexagon-v56.yaml
new file mode 100644
index 0000000..051da43
--- /dev/null
+++ b/Documentation/devicetree/bindings/remoteproc/qcom,hexagon-v56.yaml
@@ -0,0 +1,267 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/remoteproc/qcom,hexagon-v56.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Hexagon v56 Peripheral Image Loader
+
+maintainers:
+ - Bjorn Andersson <[email protected]>
+
+description:
+ This document defines the binding for a component that loads and boots firmware
+ on the Qualcomm Technology Inc. Hexagon v56 core.
+
+properties:
+ compatible:
+ enum:
+ - qcom,qcs404-cdsp-pil
+ - qcom,sdm845-adsp-pil
+
+ reg:
+ maxItems: 1
+ description:
+ The base address and size of the qdsp6ss register
+
+ interrupts-extended:
+ minItems: 5
+ items:
+ - description: Watchdog interrupt
+ - description: Fatal interrupt
+ - description: Ready interrupt
+ - description: Handover interrupt
+ - description: Stop acknowledge interrupt
+
+ interrupt-names:
+ minItems: 5
+ items:
+ - const: wdog
+ - const: fatal
+ - const: ready
+ - const: handover
+ - const: stop-ack
+
+ clocks:
+ minItems: 7
+ maxItems: 8
+ description:
+ List of phandles and clock specifier pairs for the Hexagon,
+ per clock-names below.
+
+ clock-names:
+ minItems: 7
+ maxItems: 8
+
+ power-domains:
+ minItems: 1
+ items:
+ - description: CX power domain
+
+ resets:
+ minItems: 1
+ maxItems: 2
+ description:
+ reference to the list of resets for the Hexagon.
+
+ reset-names:
+ minItems: 1
+ maxItems: 2
+
+ memory-region:
+ maxItems: 1
+ description: Reference to the reserved-memory for the Hexagon core
+
+ qcom,halt-regs:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description:
+ Phandle reference to a syscon representing TCSR followed by the
+ three offsets within syscon for q6, modem and nc halt registers.
+
+ qcom,smem-states:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: States used by the AP to signal the Hexagon core
+ items:
+ - description: Stop the modem
+
+ qcom,smem-state-names:
+ $ref: /schemas/types.yaml#/definitions/string-array
+ description: The names of the state bits used for SMP2P output
+ items:
+ - const: stop
+
+ glink-edge:
+ type: object
+ description:
+ Qualcomm G-Link subnode which represents communication edge, channels
+ and devices related to the ADSP.
+
+required:
+ - compatible
+ - reg
+ - interrupts-extended
+ - interrupt-names
+ - clocks
+ - clock-names
+ - power-domains
+ - qcom,halt-regs
+ - memory-region
+ - qcom,smem-states
+ - qcom,smem-state-names
+
+additionalProperties: false
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sdm845-adsp-pil
+ then:
+ properties:
+ clocks:
+ items:
+ - description: XO clock
+ - description: SWAY clock
+ - description: LPASS AHBS AON clock
+ - description: LPASS AHBM AON clock
+ - description: QDSP6SS XO clock
+ - description: QDSP6SS SLEEP clock
+ - description: QDSP6SS CORE clock
+ clock-names:
+ items:
+ - const: xo
+ - const: sway_cbcr
+ - const: lpass_ahbs_aon_cbcr
+ - const: lpass_ahbm_aon_cbcr
+ - const: qdsp6ss_xo
+ - const: qdsp6ss_sleep
+ - const: qdsp6ss_core
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,qcs404-cdsp-pil
+ then:
+ properties:
+ clocks:
+ items:
+ - description: XO clock
+ - description: SWAY clock
+ - description: TBU clock
+ - description: BIMC clock
+ - description: AHB AON clock
+ - description: Q6SS SLAVE clock
+ - description: Q6SS MASTER clock
+ - description: Q6 AXIM clock
+ clock-names:
+ items:
+ - const: xo
+ - const: sway
+ - const: tbu
+ - const: bimc
+ - const: ahb_aon
+ - const: q6ss_slave
+ - const: q6ss_master
+ - const: q6_axim
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sc7280-wpss-pil
+ then:
+ properties:
+ clocks:
+ items:
+ - description: GCC WPSS AHB BDG Master clock
+ - description: GCC WPSS AHB clock
+ - description: GCC WPSS RSCP clock
+ clock-names:
+ items:
+ - const: gcc_wpss_ahb_bdg_mst_clk
+ - const: gcc_wpss_ahb_clk
+ - const: gcc_wpss_rscp_clk
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sdm845-adsp-pil
+ then:
+ properties:
+ resets:
+ items:
+ - description: PDC SYNC
+ - description: CC LPASS
+ reset-names:
+ items:
+ - const: pdc_sync
+ - const: cc_lpass
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,qcs404-cdsp-pil
+ then:
+ properties:
+ resets:
+ items:
+ - description: CDSP restart
+ reset-names:
+ items:
+ - const: restart
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/clock/qcom,gcc-sdm845.h>
+ #include <dt-bindings/clock/qcom,lpass-sdm845.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+ #include <dt-bindings/reset/qcom,sdm845-pdc.h>
+ #include <dt-bindings/reset/qcom,sdm845-aoss.h>
+ remoteproc@17300000 {
+ compatible = "qcom,sdm845-adsp-pil";
+ reg = <0x17300000 0x40c>;
+
+ interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
+ <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog", "fatal", "ready",
+ "handover", "stop-ack";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_LPASS_SWAY_CLK>,
+ <&lpasscc LPASS_Q6SS_AHBS_AON_CLK>,
+ <&lpasscc LPASS_Q6SS_AHBM_AON_CLK>,
+ <&lpasscc LPASS_QDSP6SS_XO_CLK>,
+ <&lpasscc LPASS_QDSP6SS_SLEEP_CLK>,
+ <&lpasscc LPASS_QDSP6SS_CORE_CLK>;
+ clock-names = "xo", "sway_cbcr",
+ "lpass_ahbs_aon_cbcr",
+ "lpass_ahbm_aon_cbcr", "qdsp6ss_xo",
+ "qdsp6ss_sleep", "qdsp6ss_core";
+
+ power-domains = <&rpmhpd SDM845_CX>;
+
+ resets = <&pdc_reset PDC_AUDIO_SYNC_RESET>,
+ <&aoss_reset AOSS_CC_LPASS_RESTART>;
+ reset-names = "pdc_sync", "cc_lpass";
+
+ qcom,halt-regs = <&tcsr_mutex_regs 0x22000>;
+
+ memory-region = <&pil_adsp_mem>;
+
+ qcom,smem-states = <&adsp_smp2p_out 0>;
+ qcom,smem-state-names = "stop";
+ };
--
2.7.4
Add support for PIL loading of WPSS processor for SC7280
- WPSS boot will be requested by the wifi driver and hence
disable auto-boot for WPSS.
- Add a separate shutdown sequence handler for WPSS.
- Add multiple power-domain voting support
Signed-off-by: Rakesh Pillai <[email protected]>
---
drivers/remoteproc/qcom_q6v5_adsp.c | 141 +++++++++++++++++++++++++++++++++++-
1 file changed, 138 insertions(+), 3 deletions(-)
diff --git a/drivers/remoteproc/qcom_q6v5_adsp.c b/drivers/remoteproc/qcom_q6v5_adsp.c
index 098362e6..f05e749 100644
--- a/drivers/remoteproc/qcom_q6v5_adsp.c
+++ b/drivers/remoteproc/qcom_q6v5_adsp.c
@@ -32,6 +32,7 @@
/* time out value */
#define ACK_TIMEOUT 1000
+#define ACK_TIMEOUT_US 1000000
#define BOOT_FSM_TIMEOUT 10000
/* mask values */
#define EVB_MASK GENMASK(27, 4)
@@ -51,6 +52,8 @@
#define QDSP6SS_CORE_CBCR 0x20
#define QDSP6SS_SLEEP_CBCR 0x3c
+#define QCOM_Q6V5_RPROC_PROXY_PD_MAX 3
+
struct adsp_pil_data {
int crash_reason_smem;
const char *firmware_name;
@@ -58,9 +61,13 @@ struct adsp_pil_data {
const char *ssr_name;
const char *sysmon_name;
int ssctl_id;
+ bool is_wpss;
+ bool auto_boot;
const char **clk_ids;
int num_clks;
+ const char **proxy_pd_names;
+ const char *load_state;
};
struct qcom_adsp {
@@ -93,11 +100,91 @@ struct qcom_adsp {
void *mem_region;
size_t mem_size;
+ struct device *proxy_pds[QCOM_Q6V5_RPROC_PROXY_PD_MAX];
+ int proxy_pd_count;
+
struct qcom_rproc_glink glink_subdev;
struct qcom_rproc_ssr ssr_subdev;
struct qcom_sysmon *sysmon;
+
+ int (*shutdown)(struct qcom_adsp *adsp);
};
+static int qcom_rproc_pds_attach(struct device *dev, struct device **devs,
+ const char **pd_names)
+{
+ size_t num_pds = 0;
+ int ret;
+ int i;
+
+ if (!pd_names)
+ return 0;
+
+ while (pd_names[num_pds])
+ num_pds++;
+
+ for (i = 0; i < num_pds; i++) {
+ devs[i] = dev_pm_domain_attach_by_name(dev, pd_names[i]);
+ if (IS_ERR_OR_NULL(devs[i])) {
+ ret = PTR_ERR(devs[i]) ? : -ENODATA;
+ goto unroll_attach;
+ }
+ }
+
+ return num_pds;
+
+unroll_attach:
+ for (i--; i >= 0; i--)
+ dev_pm_domain_detach(devs[i], false);
+
+ return ret;
+}
+
+static void qcom_rproc_pds_detach(struct qcom_adsp *adsp, struct device **pds,
+ size_t pd_count)
+{
+ int i;
+
+ for (i = 0; i < pd_count; i++)
+ dev_pm_domain_detach(pds[i], false);
+}
+
+static int qcom_wpss_shutdown(struct qcom_adsp *adsp)
+{
+ unsigned int val;
+
+ regmap_write(adsp->halt_map, adsp->halt_lpass + LPASS_HALTREQ_REG, 1);
+
+ /* Wait for halt ACK from QDSP6 */
+ regmap_read_poll_timeout(adsp->halt_map,
+ adsp->halt_lpass + LPASS_HALTACK_REG, val,
+ val, 1000, ACK_TIMEOUT_US);
+
+ /* Assert the WPSS PDC Reset */
+ reset_control_assert(adsp->pdc_sync_reset);
+ /* Place the WPSS processor into reset */
+ reset_control_assert(adsp->restart);
+ /* wait after asserting subsystem restart from AOSS */
+ usleep_range(200, 205);
+ /* Remove the WPSS reset */
+ reset_control_deassert(adsp->restart);
+ /* De-assert the WPSS PDC Reset */
+ reset_control_deassert(adsp->pdc_sync_reset);
+
+ usleep_range(100, 105);
+
+ clk_bulk_disable_unprepare(adsp->num_clks, adsp->clks);
+
+ regmap_write(adsp->halt_map, adsp->halt_lpass + LPASS_HALTREQ_REG, 0);
+
+ /* Wait for halt ACK from QDSP6 */
+ regmap_read_poll_timeout(adsp->halt_map,
+ adsp->halt_lpass + LPASS_HALTACK_REG, val,
+ !val, 1000, ACK_TIMEOUT_US);
+
+ return 0;
+}
+
static int qcom_adsp_shutdown(struct qcom_adsp *adsp)
{
unsigned long timeout;
@@ -272,7 +359,7 @@ static int adsp_stop(struct rproc *rproc)
if (ret == -ETIMEDOUT)
dev_err(adsp->dev, "timed out on wait\n");
- ret = qcom_adsp_shutdown(adsp);
+ ret = adsp->shutdown(adsp);
if (ret)
dev_err(adsp->dev, "failed to shutdown: %d\n", ret);
@@ -441,6 +528,8 @@ static int adsp_probe(struct platform_device *pdev)
dev_err(&pdev->dev, "unable to allocate remoteproc\n");
return -ENOMEM;
}
+
+ rproc->auto_boot = desc->auto_boot;
rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE);
adsp = (struct qcom_adsp *)rproc->priv;
@@ -449,6 +538,11 @@ static int adsp_probe(struct platform_device *pdev)
adsp->info_name = desc->sysmon_name;
platform_set_drvdata(pdev, adsp);
+ if (desc->is_wpss)
+ adsp->shutdown = qcom_wpss_shutdown;
+ else
+ adsp->shutdown = qcom_adsp_shutdown;
+
ret = adsp_alloc_memory_region(adsp);
if (ret)
goto free_rproc;
@@ -457,6 +551,14 @@ static int adsp_probe(struct platform_device *pdev)
if (ret)
goto free_rproc;
+ ret = qcom_rproc_pds_attach(adsp->dev, adsp->proxy_pds,
+ desc->proxy_pd_names);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "Failed to attach proxy power domains\n");
+ goto free_rproc;
+ }
+ adsp->proxy_pd_count = ret;
+
pm_runtime_enable(adsp->dev);
ret = adsp_init_reset(adsp);
@@ -467,8 +569,8 @@ static int adsp_probe(struct platform_device *pdev)
if (ret)
goto disable_pm;
- ret = qcom_q6v5_init(&adsp->q6v5, pdev, rproc, desc->crash_reason_smem, NULL,
- qcom_adsp_pil_handover);
+ ret = qcom_q6v5_init(&adsp->q6v5, pdev, rproc, desc->crash_reason_smem,
+ desc->load_state, qcom_adsp_pil_handover);
if (ret)
goto disable_pm;
@@ -490,6 +592,8 @@ static int adsp_probe(struct platform_device *pdev)
disable_pm:
pm_runtime_disable(adsp->dev);
+ qcom_rproc_pds_detach(adsp, adsp->proxy_pds, adsp->proxy_pd_count);
+
free_rproc:
rproc_free(rproc);
@@ -507,6 +611,7 @@ static int adsp_remove(struct platform_device *pdev)
qcom_remove_sysmon_subdev(adsp->sysmon);
qcom_remove_ssr_subdev(adsp->rproc, &adsp->ssr_subdev);
pm_runtime_disable(adsp->dev);
+ qcom_rproc_pds_detach(adsp, adsp->proxy_pds, adsp->proxy_pd_count);
rproc_free(adsp->rproc);
return 0;
@@ -518,11 +623,16 @@ static const struct adsp_pil_data adsp_resource_init = {
.ssr_name = "lpass",
.sysmon_name = "adsp",
.ssctl_id = 0x14,
+ .is_wpss = false,
+ .auto_boot = true,
.clk_ids = (const char*[]) {
"sway_cbcr", "lpass_ahbs_aon_cbcr", "lpass_ahbm_aon_cbcr",
"qdsp6ss_xo", "qdsp6ss_sleep", "qdsp6ss_core", NULL
},
.num_clks = 7,
+ .proxy_pd_names = (const char*[]) {
+ "cx", NULL
+ },
};
static const struct adsp_pil_data cdsp_resource_init = {
@@ -531,15 +641,40 @@ static const struct adsp_pil_data cdsp_resource_init = {
.ssr_name = "cdsp",
.sysmon_name = "cdsp",
.ssctl_id = 0x17,
+ .is_wpss = false,
+ .auto_boot = true,
.clk_ids = (const char*[]) {
"sway", "tbu", "bimc", "ahb_aon", "q6ss_slave", "q6ss_master",
"q6_axim", NULL
},
.num_clks = 7,
+ .proxy_pd_names = (const char*[]) {
+ "cx", NULL
+ },
+};
+
+static const struct adsp_pil_data wpss_resource_init = {
+ .crash_reason_smem = 626,
+ .firmware_name = "wpss.mdt",
+ .ssr_name = "wpss",
+ .sysmon_name = "wpss",
+ .ssctl_id = 0x19,
+ .is_wpss = true,
+ .auto_boot = false,
+ .load_state = "wpss",
+ .clk_ids = (const char*[]) {
+ "gcc_wpss_ahb_bdg_mst_clk", "gcc_wpss_ahb_clk",
+ "gcc_wpss_rscp_clk", NULL
+ },
+ .num_clks = 3,
+ .proxy_pd_names = (const char*[]) {
+ "cx", "mx", NULL
+ },
};
static const struct of_device_id adsp_of_match[] = {
{ .compatible = "qcom,qcs404-cdsp-pil", .data = &cdsp_resource_init },
+ { .compatible = "qcom,sc7280-wpss-pil", .data = &wpss_resource_init },
{ .compatible = "qcom,sdm845-adsp-pil", .data = &adsp_resource_init },
{ },
};
--
2.7.4
Add WPSS PIL loading support for SC7280 SoCs.
Signed-off-by: Rakesh Pillai <[email protected]>
---
.../bindings/remoteproc/qcom,hexagon-v56.yaml | 88 +++++++++++++++++++++-
1 file changed, 86 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,hexagon-v56.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,hexagon-v56.yaml
index 051da43..5674602 100644
--- a/Documentation/devicetree/bindings/remoteproc/qcom,hexagon-v56.yaml
+++ b/Documentation/devicetree/bindings/remoteproc/qcom,hexagon-v56.yaml
@@ -17,6 +17,7 @@ properties:
compatible:
enum:
- qcom,qcs404-cdsp-pil
+ - qcom,sc7280-wpss-pil
- qcom,sdm845-adsp-pil
reg:
@@ -43,14 +44,14 @@ properties:
- const: stop-ack
clocks:
- minItems: 7
+ minItems: 3
maxItems: 8
description:
List of phandles and clock specifier pairs for the Hexagon,
per clock-names below.
clock-names:
- minItems: 7
+ minItems: 3
maxItems: 8
power-domains:
@@ -58,6 +59,11 @@ properties:
items:
- description: CX power domain
+ power-domain-names:
+ minItems: 1
+ items:
+ - const: cx
+
resets:
minItems: 1
maxItems: 2
@@ -78,6 +84,10 @@ properties:
Phandle reference to a syscon representing TCSR followed by the
three offsets within syscon for q6, modem and nc halt registers.
+ qcom,qmp:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: Reference to the AOSS side-channel message RAM.
+
qcom,smem-states:
$ref: /schemas/types.yaml#/definitions/phandle-array
description: States used by the AP to signal the Hexagon core
@@ -117,6 +127,33 @@ allOf:
compatible:
contains:
enum:
+ - qcom,sc7280-wpss-pil
+ then:
+ properties:
+ interrupts-extended:
+ maxItems: 6
+ items:
+ - description: Watchdog interrupt
+ - description: Fatal interrupt
+ - description: Ready interrupt
+ - description: Handover interrupt
+ - description: Stop acknowledge interrupt
+ - description: Shutdown acknowledge interrupt
+ interrupt-names:
+ maxItems: 6
+ items:
+ - const: wdog
+ - const: fatal
+ - const: ready
+ - const: handover
+ - const: stop-ack
+ - const: shutdown-ack
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
- qcom,sdm845-adsp-pil
then:
properties:
@@ -192,6 +229,25 @@ allOf:
compatible:
contains:
enum:
+ - qcom,sc7280-wpss-pil
+ then:
+ properties:
+ power-domains:
+ maxItems: 2
+ items:
+ - description: CX power domain
+ - description: MX power domain
+ power-domain-names:
+ maxItems: 2
+ items:
+ - const: cx
+ - const: mx
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
- qcom,sdm845-adsp-pil
then:
properties:
@@ -219,6 +275,34 @@ allOf:
items:
- const: restart
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sc7280-wpss-pil
+ then:
+ properties:
+ resets:
+ items:
+ - description: AOSS restart
+ - description: PDC SYNC
+ reset-names:
+ items:
+ - const: restart
+ - const: pdc_sync
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sdm845-adsp-pil
+ - qcom,qcs404-cdsp-pil
+ then:
+ properties:
+ qcom,qmp: false
+
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
--
2.7.4
Quoting Rakesh Pillai (2021-09-16 09:55:53)
> Add support for PIL loading of WPSS processor for SC7280
> - WPSS boot will be requested by the wifi driver and hence
> disable auto-boot for WPSS.
> - Add a separate shutdown sequence handler for WPSS.
> - Add multiple power-domain voting support
>
> Signed-off-by: Rakesh Pillai <[email protected]>
> ---
Reviewed-by: Stephen Boyd <[email protected]>
Quoting Rakesh Pillai (2021-09-16 09:55:51)
> diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,hexagon-v56.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,hexagon-v56.yaml
> new file mode 100644
> index 0000000..051da43
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/remoteproc/qcom,hexagon-v56.yaml
> @@ -0,0 +1,267 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/remoteproc/qcom,hexagon-v56.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Hexagon v56 Peripheral Image Loader
> +
> +maintainers:
> + - Bjorn Andersson <[email protected]>
> +
> +description:
> + This document defines the binding for a component that loads and boots firmware
> + on the Qualcomm Technology Inc. Hexagon v56 core.
> +
> +properties:
> + compatible:
> + enum:
> + - qcom,qcs404-cdsp-pil
> + - qcom,sdm845-adsp-pil
> +
> + reg:
> + maxItems: 1
> + description:
> + The base address and size of the qdsp6ss register
> +
> + interrupts-extended:
> + minItems: 5
> + items:
> + - description: Watchdog interrupt
> + - description: Fatal interrupt
> + - description: Ready interrupt
> + - description: Handover interrupt
> + - description: Stop acknowledge interrupt
> +
> + interrupt-names:
> + minItems: 5
> + items:
> + - const: wdog
> + - const: fatal
> + - const: ready
> + - const: handover
> + - const: stop-ack
> +
> + clocks:
> + minItems: 7
> + maxItems: 8
> + description:
> + List of phandles and clock specifier pairs for the Hexagon,
> + per clock-names below.
> +
> + clock-names:
> + minItems: 7
> + maxItems: 8
> +
> + power-domains:
> + minItems: 1
> + items:
> + - description: CX power domain
> +
> + resets:
> + minItems: 1
> + maxItems: 2
> + description:
> + reference to the list of resets for the Hexagon.
> +
> + reset-names:
> + minItems: 1
> + maxItems: 2
> +
> + memory-region:
> + maxItems: 1
> + description: Reference to the reserved-memory for the Hexagon core
> +
> + qcom,halt-regs:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + description:
> + Phandle reference to a syscon representing TCSR followed by the
> + three offsets within syscon for q6, modem and nc halt registers.
> +
> + qcom,smem-states:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + description: States used by the AP to signal the Hexagon core
> + items:
> + - description: Stop the modem
> +
> + qcom,smem-state-names:
> + $ref: /schemas/types.yaml#/definitions/string-array
> + description: The names of the state bits used for SMP2P output
> + items:
> + - const: stop
> +
> + glink-edge:
> + type: object
> + description:
> + Qualcomm G-Link subnode which represents communication edge, channels
> + and devices related to the ADSP.
> +
> +required:
> + - compatible
> + - reg
> + - interrupts-extended
> + - interrupt-names
> + - clocks
> + - clock-names
> + - power-domains
> + - qcom,halt-regs
> + - memory-region
> + - qcom,smem-states
> + - qcom,smem-state-names
Is there some way to make sure that 'resets' and 'reset-names' is
present when the compatible that defines them is used and not required
otherwise?
> +
> +additionalProperties: false
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,sdm845-adsp-pil
> + then:
> + properties:
> + clocks:
> + items:
> + - description: XO clock
> + - description: SWAY clock
> + - description: LPASS AHBS AON clock
> + - description: LPASS AHBM AON clock
> + - description: QDSP6SS XO clock
> + - description: QDSP6SS SLEEP clock
> + - description: QDSP6SS CORE clock
> + clock-names:
> + items:
> + - const: xo
> + - const: sway_cbcr
> + - const: lpass_ahbs_aon_cbcr
> + - const: lpass_ahbm_aon_cbcr
> + - const: qdsp6ss_xo
> + - const: qdsp6ss_sleep
> + - const: qdsp6ss_core
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,qcs404-cdsp-pil
> + then:
> + properties:
> + clocks:
> + items:
> + - description: XO clock
> + - description: SWAY clock
> + - description: TBU clock
> + - description: BIMC clock
> + - description: AHB AON clock
> + - description: Q6SS SLAVE clock
> + - description: Q6SS MASTER clock
> + - description: Q6 AXIM clock
> + clock-names:
> + items:
> + - const: xo
> + - const: sway
> + - const: tbu
> + - const: bimc
> + - const: ahb_aon
> + - const: q6ss_slave
> + - const: q6ss_master
> + - const: q6_axim
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,sc7280-wpss-pil
This should be documented above in the compatible list?
> + then:
> + properties:
> + clocks:
> + items:
> + - description: GCC WPSS AHB BDG Master clock
> + - description: GCC WPSS AHB clock
> + - description: GCC WPSS RSCP clock
> + clock-names:
> + items:
> + - const: gcc_wpss_ahb_bdg_mst_clk
> + - const: gcc_wpss_ahb_clk
> + - const: gcc_wpss_rscp_clk
Is the 'gcc_wpss' prefix important? It would be shorter if it wasn't
there.
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,sdm845-adsp-pil
> + then:
> + properties:
> + resets:
> + items:
> + - description: PDC SYNC
> + - description: CC LPASS
> + reset-names:
> + items:
> + - const: pdc_sync
> + - const: cc_lpass
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,qcs404-cdsp-pil
> + then:
> + properties:
> + resets:
> + items:
> + - description: CDSP restart
> + reset-names:
> + items:
> + - const: restart
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/clock/qcom,rpmh.h>
> + #include <dt-bindings/clock/qcom,gcc-sdm845.h>
> + #include <dt-bindings/clock/qcom,lpass-sdm845.h>
> + #include <dt-bindings/power/qcom-rpmpd.h>
> + #include <dt-bindings/reset/qcom,sdm845-pdc.h>
> + #include <dt-bindings/reset/qcom,sdm845-aoss.h>
> + remoteproc@17300000 {
> + compatible = "qcom,sdm845-adsp-pil";
> + reg = <0x17300000 0x40c>;
> +
> + interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
> + <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
> + <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
> + <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
> + <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "wdog", "fatal", "ready",
> + "handover", "stop-ack";
> +
> + clocks = <&rpmhcc RPMH_CXO_CLK>,
> + <&gcc GCC_LPASS_SWAY_CLK>,
> + <&lpasscc LPASS_Q6SS_AHBS_AON_CLK>,
> + <&lpasscc LPASS_Q6SS_AHBM_AON_CLK>,
> + <&lpasscc LPASS_QDSP6SS_XO_CLK>,
> + <&lpasscc LPASS_QDSP6SS_SLEEP_CLK>,
> + <&lpasscc LPASS_QDSP6SS_CORE_CLK>;
> + clock-names = "xo", "sway_cbcr",
> + "lpass_ahbs_aon_cbcr",
> + "lpass_ahbm_aon_cbcr", "qdsp6ss_xo",
> + "qdsp6ss_sleep", "qdsp6ss_core";
> +
> + power-domains = <&rpmhpd SDM845_CX>;
> +
> + resets = <&pdc_reset PDC_AUDIO_SYNC_RESET>,
> + <&aoss_reset AOSS_CC_LPASS_RESTART>;
> + reset-names = "pdc_sync", "cc_lpass";
> +
> + qcom,halt-regs = <&tcsr_mutex_regs 0x22000>;
> +
> + memory-region = <&pil_adsp_mem>;
> +
> + qcom,smem-states = <&adsp_smp2p_out 0>;
> + qcom,smem-state-names = "stop";
> + };
Should there be two more examples for the other compatible strings here?
Quoting Rakesh Pillai (2021-09-16 09:55:52)
> @@ -78,6 +84,10 @@ properties:
> Phandle reference to a syscon representing TCSR followed by the
> three offsets within syscon for q6, modem and nc halt registers.
>
> + qcom,qmp:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description: Reference to the AOSS side-channel message RAM.
> +
> qcom,smem-states:
> $ref: /schemas/types.yaml#/definitions/phandle-array
> description: States used by the AP to signal the Hexagon core
> @@ -117,6 +127,33 @@ allOf:
> compatible:
> contains:
> enum:
> + - qcom,sc7280-wpss-pil
> + then:
Honestly I find this if/else to be a huge tangle. Why not split the
binding so that each compatible is a different file? Then it is easier
to read and see what properties to set.
> + properties:
> + interrupts-extended:
> + maxItems: 6
> + items:
> + - description: Watchdog interrupt
> + - description: Fatal interrupt
> + - description: Ready interrupt
> -----Original Message-----
> From: Stephen Boyd <[email protected]>
> Sent: Friday, September 17, 2021 11:56 AM
> To: Rakesh Pillai <[email protected]>; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]
> Cc: [email protected]; [email protected]; linux-
> [email protected]; [email protected]; [email protected];
> [email protected]
> Subject: Re: [PATCH v3 2/3] dt-bindings: remoteproc: qcom: Add SC7280
> WPSS support
>
> Quoting Rakesh Pillai (2021-09-16 09:55:52)
> > @@ -78,6 +84,10 @@ properties:
> > Phandle reference to a syscon representing TCSR followed by the
> > three offsets within syscon for q6, modem and nc halt registers.
> >
> > + qcom,qmp:
> > + $ref: /schemas/types.yaml#/definitions/phandle
> > + description: Reference to the AOSS side-channel message RAM.
> > +
> > qcom,smem-states:
> > $ref: /schemas/types.yaml#/definitions/phandle-array
> > description: States used by the AP to signal the Hexagon core @@
> > -117,6 +127,33 @@ allOf:
> > compatible:
> > contains:
> > enum:
> > + - qcom,sc7280-wpss-pil
> > + then:
>
> Honestly I find this if/else to be a huge tangle. Why not split the binding so
> that each compatible is a different file? Then it is easier to read and see what
> properties to set.
Hi Stephen,
I will create a separate dt-bindings yaml file for sc7280-wpss-pil, which will avoid all such if-else conditions.
>
> > + properties:
> > + interrupts-extended:
> > + maxItems: 6
> > + items:
> > + - description: Watchdog interrupt
> > + - description: Fatal interrupt
> > + - description: Ready interrupt
On Thu, Sep 16, 2021 at 11:24:10PM -0700, Stephen Boyd wrote:
> Quoting Rakesh Pillai (2021-09-16 09:55:51)
> > diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,hexagon-v56.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,hexagon-v56.yaml
> > new file mode 100644
> > index 0000000..051da43
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/remoteproc/qcom,hexagon-v56.yaml
> > @@ -0,0 +1,267 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/remoteproc/qcom,hexagon-v56.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Qualcomm Hexagon v56 Peripheral Image Loader
> > +
> > +maintainers:
> > + - Bjorn Andersson <[email protected]>
> > +
> > +description:
> > + This document defines the binding for a component that loads and boots firmware
> > + on the Qualcomm Technology Inc. Hexagon v56 core.
> > +
> > +properties:
> > + compatible:
> > + enum:
> > + - qcom,qcs404-cdsp-pil
> > + - qcom,sdm845-adsp-pil
> > +
> > + reg:
> > + maxItems: 1
> > + description:
> > + The base address and size of the qdsp6ss register
> > +
> > + interrupts-extended:
> > + minItems: 5
> > + items:
> > + - description: Watchdog interrupt
> > + - description: Fatal interrupt
> > + - description: Ready interrupt
> > + - description: Handover interrupt
> > + - description: Stop acknowledge interrupt
> > +
> > + interrupt-names:
> > + minItems: 5
> > + items:
> > + - const: wdog
> > + - const: fatal
> > + - const: ready
> > + - const: handover
> > + - const: stop-ack
> > +
> > + clocks:
> > + minItems: 7
> > + maxItems: 8
> > + description:
> > + List of phandles and clock specifier pairs for the Hexagon,
> > + per clock-names below.
> > +
> > + clock-names:
> > + minItems: 7
> > + maxItems: 8
> > +
> > + power-domains:
> > + minItems: 1
> > + items:
> > + - description: CX power domain
> > +
> > + resets:
> > + minItems: 1
> > + maxItems: 2
> > + description:
> > + reference to the list of resets for the Hexagon.
> > +
> > + reset-names:
> > + minItems: 1
> > + maxItems: 2
> > +
> > + memory-region:
> > + maxItems: 1
> > + description: Reference to the reserved-memory for the Hexagon core
> > +
> > + qcom,halt-regs:
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + description:
> > + Phandle reference to a syscon representing TCSR followed by the
> > + three offsets within syscon for q6, modem and nc halt registers.
> > +
> > + qcom,smem-states:
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + description: States used by the AP to signal the Hexagon core
> > + items:
> > + - description: Stop the modem
> > +
> > + qcom,smem-state-names:
> > + $ref: /schemas/types.yaml#/definitions/string-array
> > + description: The names of the state bits used for SMP2P output
> > + items:
> > + - const: stop
> > +
> > + glink-edge:
> > + type: object
> > + description:
> > + Qualcomm G-Link subnode which represents communication edge, channels
> > + and devices related to the ADSP.
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - interrupts-extended
> > + - interrupt-names
> > + - clocks
> > + - clock-names
> > + - power-domains
> > + - qcom,halt-regs
> > + - memory-region
> > + - qcom,smem-states
> > + - qcom,smem-state-names
>
> Is there some way to make sure that 'resets' and 'reset-names' is
> present when the compatible that defines them is used and not required
> otherwise?
Yes, plenty of examples of that.
>
> > +
> > +additionalProperties: false
> > +
> > +allOf:
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + enum:
> > + - qcom,sdm845-adsp-pil
> > + then:
> > + properties:
> > + clocks:
> > + items:
> > + - description: XO clock
> > + - description: SWAY clock
> > + - description: LPASS AHBS AON clock
> > + - description: LPASS AHBM AON clock
> > + - description: QDSP6SS XO clock
> > + - description: QDSP6SS SLEEP clock
> > + - description: QDSP6SS CORE clock
> > + clock-names:
> > + items:
> > + - const: xo
> > + - const: sway_cbcr
> > + - const: lpass_ahbs_aon_cbcr
> > + - const: lpass_ahbm_aon_cbcr
> > + - const: qdsp6ss_xo
> > + - const: qdsp6ss_sleep
> > + - const: qdsp6ss_core
> > +
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + enum:
> > + - qcom,qcs404-cdsp-pil
> > + then:
> > + properties:
> > + clocks:
> > + items:
> > + - description: XO clock
> > + - description: SWAY clock
> > + - description: TBU clock
> > + - description: BIMC clock
> > + - description: AHB AON clock
> > + - description: Q6SS SLAVE clock
> > + - description: Q6SS MASTER clock
> > + - description: Q6 AXIM clock
> > + clock-names:
> > + items:
> > + - const: xo
> > + - const: sway
> > + - const: tbu
> > + - const: bimc
> > + - const: ahb_aon
> > + - const: q6ss_slave
> > + - const: q6ss_master
> > + - const: q6_axim
> > +
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + enum:
> > + - qcom,sc7280-wpss-pil
>
> This should be documented above in the compatible list?
>
> > + then:
> > + properties:
> > + clocks:
> > + items:
> > + - description: GCC WPSS AHB BDG Master clock
> > + - description: GCC WPSS AHB clock
> > + - description: GCC WPSS RSCP clock
> > + clock-names:
> > + items:
> > + - const: gcc_wpss_ahb_bdg_mst_clk
> > + - const: gcc_wpss_ahb_clk
> > + - const: gcc_wpss_rscp_clk
>
> Is the 'gcc_wpss' prefix important? It would be shorter if it wasn't
> there.
Yes, and adding this new platform should be a separate patch.
Rob
On Thu 16 Sep 23:25 PDT 2021, Stephen Boyd wrote:
> Quoting Rakesh Pillai (2021-09-16 09:55:52)
> > @@ -78,6 +84,10 @@ properties:
> > Phandle reference to a syscon representing TCSR followed by the
> > three offsets within syscon for q6, modem and nc halt registers.
> >
> > + qcom,qmp:
> > + $ref: /schemas/types.yaml#/definitions/phandle
> > + description: Reference to the AOSS side-channel message RAM.
> > +
> > qcom,smem-states:
> > $ref: /schemas/types.yaml#/definitions/phandle-array
> > description: States used by the AP to signal the Hexagon core
> > @@ -117,6 +127,33 @@ allOf:
> > compatible:
> > contains:
> > enum:
> > + - qcom,sc7280-wpss-pil
> > + then:
>
> Honestly I find this if/else to be a huge tangle. Why not split the
> binding so that each compatible is a different file? Then it is easier
> to read and see what properties to set.
>
Further more, the way we express the non-PAS properties in the PAS node
in the dtsi and then switch the compatible in the non-PAS devices means
that we're causing validation errors.
So we should explode this binding to get rid of the conditionals and to
describe the "superset" of the PAS and non-PAS compatibles, for
platforms where this is applicable.
Regards,
Bjorn
> > + properties:
> > + interrupts-extended:
> > + maxItems: 6
> > + items:
> > + - description: Watchdog interrupt
> > + - description: Fatal interrupt
> > + - description: Ready interrupt
> -----Original Message-----
> From: Rob Herring <[email protected]>
> Sent: Wednesday, September 22, 2021 4:59 AM
> To: Stephen Boyd <[email protected]>
> Cc: Rakesh Pillai <[email protected]>; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> Rakesh Pillai <[email protected]>
> Subject: Re: [PATCH v3 1/3] dt-bindings: remoteproc: qcom: adsp: Convert
> binding to YAML
>
> On Thu, Sep 16, 2021 at 11:24:10PM -0700, Stephen Boyd wrote:
> > Quoting Rakesh Pillai (2021-09-16 09:55:51)
> > > diff --git
> > > a/Documentation/devicetree/bindings/remoteproc/qcom,hexagon-
> v56.yaml
> > > b/Documentation/devicetree/bindings/remoteproc/qcom,hexagon-
> v56.yaml
> > > new file mode 100644
> > > index 0000000..051da43
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/remoteproc/qcom,hexagon-
> v56.
> > > +++ yaml
> > > @@ -0,0 +1,267 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > > +---
> > > +$id:
> > > +http://devicetree.org/schemas/remoteproc/qcom,hexagon-v56.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: Qualcomm Hexagon v56 Peripheral Image Loader
> > > +
> > > +maintainers:
> > > + - Bjorn Andersson <[email protected]>
> > > +
> > > +description:
> > > + This document defines the binding for a component that loads and
> > > +boots firmware
> > > + on the Qualcomm Technology Inc. Hexagon v56 core.
> > > +
> > > +properties:
> > > + compatible:
> > > + enum:
> > > + - qcom,qcs404-cdsp-pil
> > > + - qcom,sdm845-adsp-pil
> > > +
> > > + reg:
> > > + maxItems: 1
> > > + description:
> > > + The base address and size of the qdsp6ss register
> > > +
> > > + interrupts-extended:
> > > + minItems: 5
> > > + items:
> > > + - description: Watchdog interrupt
> > > + - description: Fatal interrupt
> > > + - description: Ready interrupt
> > > + - description: Handover interrupt
> > > + - description: Stop acknowledge interrupt
> > > +
> > > + interrupt-names:
> > > + minItems: 5
> > > + items:
> > > + - const: wdog
> > > + - const: fatal
> > > + - const: ready
> > > + - const: handover
> > > + - const: stop-ack
> > > +
> > > + clocks:
> > > + minItems: 7
> > > + maxItems: 8
> > > + description:
> > > + List of phandles and clock specifier pairs for the Hexagon,
> > > + per clock-names below.
> > > +
> > > + clock-names:
> > > + minItems: 7
> > > + maxItems: 8
> > > +
> > > + power-domains:
> > > + minItems: 1
> > > + items:
> > > + - description: CX power domain
> > > +
> > > + resets:
> > > + minItems: 1
> > > + maxItems: 2
> > > + description:
> > > + reference to the list of resets for the Hexagon.
> > > +
> > > + reset-names:
> > > + minItems: 1
> > > + maxItems: 2
> > > +
> > > + memory-region:
> > > + maxItems: 1
> > > + description: Reference to the reserved-memory for the Hexagon
> > > + core
> > > +
> > > + qcom,halt-regs:
> > > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > > + description:
> > > + Phandle reference to a syscon representing TCSR followed by the
> > > + three offsets within syscon for q6, modem and nc halt
registers.
> > > +
> > > + qcom,smem-states:
> > > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > > + description: States used by the AP to signal the Hexagon core
> > > + items:
> > > + - description: Stop the modem
> > > +
> > > + qcom,smem-state-names:
> > > + $ref: /schemas/types.yaml#/definitions/string-array
> > > + description: The names of the state bits used for SMP2P output
> > > + items:
> > > + - const: stop
> > > +
> > > + glink-edge:
> > > + type: object
> > > + description:
> > > + Qualcomm G-Link subnode which represents communication edge,
> channels
> > > + and devices related to the ADSP.
> > > +
> > > +required:
> > > + - compatible
> > > + - reg
> > > + - interrupts-extended
> > > + - interrupt-names
> > > + - clocks
> > > + - clock-names
> > > + - power-domains
> > > + - qcom,halt-regs
> > > + - memory-region
> > > + - qcom,smem-states
> > > + - qcom,smem-state-names
> >
> > Is there some way to make sure that 'resets' and 'reset-names' is
> > present when the compatible that defines them is used and not required
> > otherwise?
>
> Yes, plenty of examples of that.
>
> >
> > > +
> > > +additionalProperties: false
> > > +
> > > +allOf:
> > > + - if:
> > > + properties:
> > > + compatible:
> > > + contains:
> > > + enum:
> > > + - qcom,sdm845-adsp-pil
> > > + then:
> > > + properties:
> > > + clocks:
> > > + items:
> > > + - description: XO clock
> > > + - description: SWAY clock
> > > + - description: LPASS AHBS AON clock
> > > + - description: LPASS AHBM AON clock
> > > + - description: QDSP6SS XO clock
> > > + - description: QDSP6SS SLEEP clock
> > > + - description: QDSP6SS CORE clock
> > > + clock-names:
> > > + items:
> > > + - const: xo
> > > + - const: sway_cbcr
> > > + - const: lpass_ahbs_aon_cbcr
> > > + - const: lpass_ahbm_aon_cbcr
> > > + - const: qdsp6ss_xo
> > > + - const: qdsp6ss_sleep
> > > + - const: qdsp6ss_core
> > > +
> > > + - if:
> > > + properties:
> > > + compatible:
> > > + contains:
> > > + enum:
> > > + - qcom,qcs404-cdsp-pil
> > > + then:
> > > + properties:
> > > + clocks:
> > > + items:
> > > + - description: XO clock
> > > + - description: SWAY clock
> > > + - description: TBU clock
> > > + - description: BIMC clock
> > > + - description: AHB AON clock
> > > + - description: Q6SS SLAVE clock
> > > + - description: Q6SS MASTER clock
> > > + - description: Q6 AXIM clock
> > > + clock-names:
> > > + items:
> > > + - const: xo
> > > + - const: sway
> > > + - const: tbu
> > > + - const: bimc
> > > + - const: ahb_aon
> > > + - const: q6ss_slave
> > > + - const: q6ss_master
> > > + - const: q6_axim
> > > +
> > > + - if:
> > > + properties:
> > > + compatible:
> > > + contains:
> > > + enum:
> > > + - qcom,sc7280-wpss-pil
> >
> > This should be documented above in the compatible list?
> >
> > > + then:
> > > + properties:
> > > + clocks:
> > > + items:
> > > + - description: GCC WPSS AHB BDG Master clock
> > > + - description: GCC WPSS AHB clock
> > > + - description: GCC WPSS RSCP clock
> > > + clock-names:
> > > + items:
> > > + - const: gcc_wpss_ahb_bdg_mst_clk
> > > + - const: gcc_wpss_ahb_clk
> > > + - const: gcc_wpss_rscp_clk
> >
> > Is the 'gcc_wpss' prefix important? It would be shorter if it wasn't
> > there.
>
> Yes, and adding this new platform should be a separate patch.
>
> Rob
Hi Rob,
I have posted v4 for this patch series, where the dt-bindings for wpss has
been moved to a separate file.
Can you please review v4 ?
Thanks,
Rakesh Pillai
> -----Original Message-----
> From: Bjorn Andersson <[email protected]>
> Sent: Wednesday, September 22, 2021 5:08 AM
> To: Stephen Boyd <[email protected]>
> Cc: Rakesh Pillai <[email protected]>; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected]; [email protected]
> Subject: Re: [PATCH v3 2/3] dt-bindings: remoteproc: qcom: Add SC7280
> WPSS support
>
> On Thu 16 Sep 23:25 PDT 2021, Stephen Boyd wrote:
>
> > Quoting Rakesh Pillai (2021-09-16 09:55:52)
> > > @@ -78,6 +84,10 @@ properties:
> > > Phandle reference to a syscon representing TCSR followed by the
> > > three offsets within syscon for q6, modem and nc halt
registers.
> > >
> > > + qcom,qmp:
> > > + $ref: /schemas/types.yaml#/definitions/phandle
> > > + description: Reference to the AOSS side-channel message RAM.
> > > +
> > > qcom,smem-states:
> > > $ref: /schemas/types.yaml#/definitions/phandle-array
> > > description: States used by the AP to signal the Hexagon core
> > > @@ -117,6 +127,33 @@ allOf:
> > > compatible:
> > > contains:
> > > enum:
> > > + - qcom,sc7280-wpss-pil
> > > + then:
> >
> > Honestly I find this if/else to be a huge tangle. Why not split the
> > binding so that each compatible is a different file? Then it is easier
> > to read and see what properties to set.
> >
>
> Further more, the way we express the non-PAS properties in the PAS node
> in the dtsi and then switch the compatible in the non-PAS devices means
that
> we're causing validation errors.
>
> So we should explode this binding to get rid of the conditionals and to
> describe the "superset" of the PAS and non-PAS compatibles, for platforms
> where this is applicable.
>
> Regards,
> Bjorn
Hi Bjorn,
I have posted v4 for this patchseries with wpss dt-bindings added as a
separate file.
Can you please check v4 ?
Thanks,
Rakesh Pillai.
>
> > > + properties:
> > > + interrupts-extended:
> > > + maxItems: 6
> > > + items:
> > > + - description: Watchdog interrupt
> > > + - description: Fatal interrupt
> > > + - description: Ready interrupt