2023-10-18 06:18:29

by Sascha Hauer

Subject: [PATCH v8 17/26] PM / devfreq: rockchip-dfi: make register stride SoC specific

The currently supported RK3399 has a stride of 20 between the channel
specific registers. Upcoming RK3588 has a different stride, so put
the stride into driver data to make it configurable.
While at it convert decimal 20 to hex 0x14 for consistency with RK3588
which has a register stride 0x4000 and we want to write that in hex
as well.

Reviewed-by: Jonathan Cameron <[email protected]>
Reviewed-by: Sebastian Reichel <[email protected]>
Signed-off-by: Sascha Hauer <[email protected]>
---

Notes:
Changes since v7:
- Initialize ddrmon_stride for RK3568 and explain why it's not needed

drivers/devfreq/event/rockchip-dfi.c | 13 +++++++++----
1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c
index 63977f9fc2693..a3d823ac68ace 100644
--- a/drivers/devfreq/event/rockchip-dfi.c
+++ b/drivers/devfreq/event/rockchip-dfi.c
@@ -113,6 +113,7 @@ struct rockchip_dfi {
int active_events;
int burst_len;
int buswidth[DMC_MAX_CHANNELS];
+ int ddrmon_stride;
};

static int rockchip_dfi_enable(struct rockchip_dfi *dfi)
@@ -190,13 +191,13 @@ static void rockchip_dfi_read_counters(struct rockchip_dfi *dfi, struct dmc_coun
if (!(dfi->channel_mask & BIT(i)))
continue;
res->c[i].read_access = readl_relaxed(dfi_regs +
- DDRMON_CH0_RD_NUM + i * 20);
+ DDRMON_CH0_RD_NUM + i * dfi->ddrmon_stride);
res->c[i].write_access = readl_relaxed(dfi_regs +
- DDRMON_CH0_WR_NUM + i * 20);
+ DDRMON_CH0_WR_NUM + i * dfi->ddrmon_stride);
res->c[i].access = readl_relaxed(dfi_regs +
- DDRMON_CH0_DFI_ACCESS_NUM + i * 20);
+ DDRMON_CH0_DFI_ACCESS_NUM + i * dfi->ddrmon_stride);
res->c[i].clock_cycles = readl_relaxed(dfi_regs +
- DDRMON_CH0_COUNT_NUM + i * 20);
+ DDRMON_CH0_COUNT_NUM + i * dfi->ddrmon_stride);
}
}

@@ -664,6 +665,8 @@ static int rk3399_dfi_init(struct rockchip_dfi *dfi)
dfi->buswidth[0] = FIELD_GET(RK3399_PMUGRF_OS_REG2_BW_CH0, val) == 0 ? 4 : 2;
dfi->buswidth[1] = FIELD_GET(RK3399_PMUGRF_OS_REG2_BW_CH1, val) == 0 ? 4 : 2;

+ dfi->ddrmon_stride = 0x14;
+
return 0;
};

@@ -690,6 +693,8 @@ static int rk3568_dfi_init(struct rockchip_dfi *dfi)

dfi->buswidth[0] = FIELD_GET(RK3568_PMUGRF_OS_REG2_BW_CH0, reg2) == 0 ? 4 : 2;

+ dfi->ddrmon_stride = 0x0; /* not relevant, we only have a single channel on this SoC */
+
return 0;
};

--
2.39.2

2023-10-18 15:11:53

by Chanwoo Choi

Subject: Re: [PATCH v8 17/26] PM / devfreq: rockchip-dfi: make register stride SoC specific

On 23. 10. 18. 15:17, Sascha Hauer wrote:
> The currently supported RK3399 has a stride of 20 between the channel
> specific registers. Upcoming RK3588 has a different stride, so put
> the stride into driver data to make it configurable.
> While at it convert decimal 20 to hex 0x14 for consistency with RK3588
> which has a register stride 0x4000 and we want to write that in hex
> as well.
>
> Reviewed-by: Jonathan Cameron <[email protected]>
> Reviewed-by: Sebastian Reichel <[email protected]>
> Signed-off-by: Sascha Hauer <[email protected]>
> ---
>
> Notes:
> Changes since v7:
> - Initialize ddrmon_stride for RK3568 and explain why it's not needed
>
> drivers/devfreq/event/rockchip-dfi.c | 13 +++++++++----
> 1 file changed, 9 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c
> index 63977f9fc2693..a3d823ac68ace 100644
> --- a/drivers/devfreq/event/rockchip-dfi.c
> +++ b/drivers/devfreq/event/rockchip-dfi.c
> @@ -113,6 +113,7 @@ struct rockchip_dfi {
> int active_events;
> int burst_len;
> int buswidth[DMC_MAX_CHANNELS];
> + int ddrmon_stride;
> };
>
> static int rockchip_dfi_enable(struct rockchip_dfi *dfi)
> @@ -190,13 +191,13 @@ static void rockchip_dfi_read_counters(struct rockchip_dfi *dfi, struct dmc_coun
> if (!(dfi->channel_mask & BIT(i)))
> continue;
> res->c[i].read_access = readl_relaxed(dfi_regs +
> - DDRMON_CH0_RD_NUM + i * 20);
> + DDRMON_CH0_RD_NUM + i * dfi->ddrmon_stride);
> res->c[i].write_access = readl_relaxed(dfi_regs +
> - DDRMON_CH0_WR_NUM + i * 20);
> + DDRMON_CH0_WR_NUM + i * dfi->ddrmon_stride);
> res->c[i].access = readl_relaxed(dfi_regs +
> - DDRMON_CH0_DFI_ACCESS_NUM + i * 20);
> + DDRMON_CH0_DFI_ACCESS_NUM + i * dfi->ddrmon_stride);
> res->c[i].clock_cycles = readl_relaxed(dfi_regs +
> - DDRMON_CH0_COUNT_NUM + i * 20);
> + DDRMON_CH0_COUNT_NUM + i * dfi->ddrmon_stride);
> }
> }
>
> @@ -664,6 +665,8 @@ static int rk3399_dfi_init(struct rockchip_dfi *dfi)
> dfi->buswidth[0] = FIELD_GET(RK3399_PMUGRF_OS_REG2_BW_CH0, val) == 0 ? 4 : 2;
> dfi->buswidth[1] = FIELD_GET(RK3399_PMUGRF_OS_REG2_BW_CH1, val) == 0 ? 4 : 2;
>
> + dfi->ddrmon_stride = 0x14;
> +
> return 0;
> };
>
> @@ -690,6 +693,8 @@ static int rk3568_dfi_init(struct rockchip_dfi *dfi)
>
> dfi->buswidth[0] = FIELD_GET(RK3568_PMUGRF_OS_REG2_BW_CH0, reg2) == 0 ? 4 : 2;
>
> + dfi->ddrmon_stride = 0x0; /* not relevant, we only have a single channel on this SoC */
> +
> return 0;
> };
>

Acked-by: Chanwoo Choi <[email protected]>

--
Best Regards,
Samsung Electronics
Chanwoo Choi

2023-10-19 12:18:01

by Chanwoo Choi

Subject: RE: [PATCH v8 17/26] PM / devfreq: rockchip-dfi: make register stride SoC specific

> -----Original Message-----
> From: Chanwoo Choi <[email protected]>
> Sent: Thursday, October 19, 2023 12:11 AM
> To: Sascha Hauer <[email protected]>; linux-
> [email protected]
> Cc: [email protected]; [email protected];
> [email protected]; Heiko Stuebner <[email protected]>; Kyungmin Park
> <[email protected]>; MyungJoo Ham <[email protected]>; Will
> Deacon <[email protected]>; Mark Rutland <[email protected]>;
> [email protected]; Michael Riesch <[email protected]>;
> Robin Murphy <[email protected]>; Vincent Legoll
> <[email protected]>; Rob Herring <[email protected]>; Krzysztof
> Kozlowski <[email protected]>; Conor Dooley
> <[email protected]>; [email protected]; Sebastian Reichel
> <[email protected]>; Jonathan Cameron
> <[email protected]>
> Subject: Re: [PATCH v8 17/26] PM / devfreq: rockchip-dfi: make register
> stride SoC specific
>
> On 23. 10. 18. 15:17, Sascha Hauer wrote:
> > The currently supported RK3399 has a stride of 20 between the channel
> > specific registers. Upcoming RK3588 has a different stride, so put the
> > stride into driver data to make it configurable.
> > While at it convert decimal 20 to hex 0x14 for consistency with RK3588
> > which has a register stride 0x4000 and we want to write that in hex as
> > well.
> >
> > Reviewed-by: Jonathan Cameron <[email protected]>
> > Reviewed-by: Sebastian Reichel <[email protected]>
> > Signed-off-by: Sascha Hauer <[email protected]>
> > ---
> >
> > Notes:
> > Changes since v7:
> > - Initialize ddrmon_stride for RK3568 and explain why it's not
> > needed
> >
> > drivers/devfreq/event/rockchip-dfi.c | 13 +++++++++----
> > 1 file changed, 9 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/devfreq/event/rockchip-dfi.c
> > b/drivers/devfreq/event/rockchip-dfi.c
> > index 63977f9fc2693..a3d823ac68ace 100644
> > --- a/drivers/devfreq/event/rockchip-dfi.c
> > +++ b/drivers/devfreq/event/rockchip-dfi.c
> > @@ -113,6 +113,7 @@ struct rockchip_dfi {
> > int active_events;
> > int burst_len;
> > int buswidth[DMC_MAX_CHANNELS];
> > + int ddrmon_stride;
> > };
> >
> > static int rockchip_dfi_enable(struct rockchip_dfi *dfi) @@ -190,13
> > +191,13 @@ static void rockchip_dfi_read_counters(struct rockchip_dfi
> *dfi, struct dmc_coun
> > if (!(dfi->channel_mask & BIT(i)))
> > continue;
> > res->c[i].read_access = readl_relaxed(dfi_regs +
> > - DDRMON_CH0_RD_NUM + i * 20);
> > + DDRMON_CH0_RD_NUM + i * dfi->ddrmon_stride);
> > res->c[i].write_access = readl_relaxed(dfi_regs +
> > - DDRMON_CH0_WR_NUM + i * 20);
> > + DDRMON_CH0_WR_NUM + i * dfi->ddrmon_stride);
> > res->c[i].access = readl_relaxed(dfi_regs +
> > - DDRMON_CH0_DFI_ACCESS_NUM + i * 20);
> > + DDRMON_CH0_DFI_ACCESS_NUM + i * dfi-
> >ddrmon_stride);
> > res->c[i].clock_cycles = readl_relaxed(dfi_regs +
> > - DDRMON_CH0_COUNT_NUM + i * 20);
> > + DDRMON_CH0_COUNT_NUM + i * dfi->ddrmon_stride);
> > }
> > }
> >
> > @@ -664,6 +665,8 @@ static int rk3399_dfi_init(struct rockchip_dfi *dfi)
> > dfi->buswidth[0] = FIELD_GET(RK3399_PMUGRF_OS_REG2_BW_CH0, val) ==
> 0 ? 4 : 2;
> > dfi->buswidth[1] = FIELD_GET(RK3399_PMUGRF_OS_REG2_BW_CH1, val) ==
> 0
> > ? 4 : 2;
> >
> > + dfi->ddrmon_stride = 0x14;
> > +
> > return 0;
> > };
> >
> > @@ -690,6 +693,8 @@ static int rk3568_dfi_init(struct rockchip_dfi
> > *dfi)
> >
> > dfi->buswidth[0] = FIELD_GET(RK3568_PMUGRF_OS_REG2_BW_CH0, reg2) ==
> > 0 ? 4 : 2;
> >
> > + dfi->ddrmon_stride = 0x0; /* not relevant, we only have a single
> > +channel on this SoC */
> > +
> > return 0;
> > };
> >
>
> Acked-by: Chanwoo Choi <[email protected]>
>
> --
> Best Regards,
> Samsung Electronics
> Chanwoo Choi


Applied it. Thanks

Best Regards,
Chanwoo Choi