2022-06-03 16:00:03

by Alim Akhtar

Subject: [PATCH v2 5/7] ufs: ufs-exynos: add mphy apb clock mask

Bit[3] of HCI_CLKSTOP_CTRL register is for enabling/disabling MPHY APB
clock. Lets add it to CLK_STOP_MASK, so that the same can be controlled
during clock masking/unmasking.

Signed-off-by: Alim Akhtar <[email protected]>
---
drivers/ufs/host/ufs-exynos.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c
index a81d8cbd542f..cc128aff8871 100644
--- a/drivers/ufs/host/ufs-exynos.c
+++ b/drivers/ufs/host/ufs-exynos.c
@@ -52,11 +52,12 @@
#define HCI_ERR_EN_DME_LAYER 0x88
#define HCI_CLKSTOP_CTRL 0xB0
#define REFCLKOUT_STOP BIT(4)
+#define MPHY_APBCLK_STOP BIT(3)
#define REFCLK_STOP BIT(2)
#define UNIPRO_MCLK_STOP BIT(1)
#define UNIPRO_PCLK_STOP BIT(0)
#define CLK_STOP_MASK (REFCLKOUT_STOP | REFCLK_STOP |\
- UNIPRO_MCLK_STOP |\
+ UNIPRO_MCLK_STOP | MPHY_APBCLK_STOP|\
UNIPRO_PCLK_STOP)
#define HCI_MISC 0xB4
#define REFCLK_CTRL_EN BIT(7)
--
2.25.1

2022-06-08 06:44:49

by Chanho Park

Subject: RE: [PATCH v2 5/7] ufs: ufs-exynos: add mphy apb clock mask

> Subject: [PATCH v2 5/7] ufs: ufs-exynos: add mphy apb clock mask
>
> Bit[3] of HCI_CLKSTOP_CTRL register is for enabling/disabling MPHY APB
> clock. Lets add it to CLK_STOP_MASK, so that the same can be controlled
> during clock masking/unmasking.
>
> Signed-off-by: Alim Akhtar <[email protected]>

Reviewed-by: Chanho Park <[email protected]>

And tested on my ExynosAutov9 SADK board.

Tested-by: Chanho Park <[email protected]>

Best Regards,
Chanho Park