This patch looks like it should be in the 3.9-stable tree, should we apply
it?
------------------
From: "Jay Agarwal <[email protected]>"
commit ff49fad1d9bf2c49f52817b04cde8e4412434637 upstream
Registering pciex as peripheral clock instead of fixed clock
as tegra_perih_reset_assert(deassert) api of this clock api
gives warning and ultimately does not succeed to assert(deassert)
Signed-off-by: Jay Agarwal <[email protected]>
Acked-by: Stephen Warren <[email protected]>
Signed-off-by: Mike Turquette <[email protected]>
Signed-off-by: Jonghwan Choi <[email protected]>
---
drivers/clk/tegra/clk-tegra30.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/tegra/clk-tegra30.c
b/drivers/clk/tegra/clk-tegra30.c
index ba6f51b..1f8595b 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -1592,6 +1592,12 @@ static void __init tegra30_periph_clk_init(void)
clk_register_clkdev(clk, "afi", "tegra-pcie");
clks[afi] = clk;
+ /* pciex */
+ clk = tegra_clk_register_periph_gate("pciex", "pll_e", 0, clk_base,
0,
+ 74, &periph_u_regs,
periph_clk_enb_refcnt);
+ clk_register_clkdev(clk, "pciex", "tegra-pcie");
+ clks[pciex] = clk;
+
/* kfuse */
clk = tegra_clk_register_periph_gate("kfuse", "clk_m",
TEGRA_PERIPH_ON_APB,
@@ -1710,11 +1716,6 @@ static void __init tegra30_fixed_clk_init(void)
1, 0, &cml_lock);
clk_register_clkdev(clk, "cml1", NULL);
clks[cml1] = clk;
-
- /* pciex */
- clk = clk_register_fixed_rate(NULL, "pciex", "pll_e", 0, 100000000);
- clk_register_clkdev(clk, "pciex", NULL);
- clks[pciex] = clk;
}
static void __init tegra30_osc_clk_init(void)
--
1.7.9.5
+Stephen to suggest
> -----Original Message-----
> From: Jonghwan Choi [mailto:[email protected]]
> Sent: Wednesday, June 19, 2013 5:49 AM
> To: 'Jonghwan Choi'; [email protected]
> Cc: [email protected]; Jay Agarwal
> Subject: [PATCH 3.9-stable] ARM: tegra30: clocks: Fix pciex clock registration
>
> This patch looks like it should be in the 3.9-stable tree, should we apply it?
>
> ------------------
>
> From: "Jay Agarwal <[email protected]>"
>
> commit ff49fad1d9bf2c49f52817b04cde8e4412434637 upstream
>
> Registering pciex as peripheral clock instead of fixed clock as
> tegra_perih_reset_assert(deassert) api of this clock api gives warning and
> ultimately does not succeed to assert(deassert)
>
> Signed-off-by: Jay Agarwal <[email protected]>
> Acked-by: Stephen Warren <[email protected]>
> Signed-off-by: Mike Turquette <[email protected]>
> Signed-off-by: Jonghwan Choi <[email protected]>
> ---
> drivers/clk/tegra/clk-tegra30.c | 11 ++++++-----
> 1 file changed, 6 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
> index ba6f51b..1f8595b 100644
> --- a/drivers/clk/tegra/clk-tegra30.c
> +++ b/drivers/clk/tegra/clk-tegra30.c
> @@ -1592,6 +1592,12 @@ static void __init tegra30_periph_clk_init(void)
> clk_register_clkdev(clk, "afi", "tegra-pcie");
> clks[afi] = clk;
>
> + /* pciex */
> + clk = tegra_clk_register_periph_gate("pciex", "pll_e", 0, clk_base,
> 0,
> + 74, &periph_u_regs,
> periph_clk_enb_refcnt);
> + clk_register_clkdev(clk, "pciex", "tegra-pcie");
> + clks[pciex] = clk;
> +
> /* kfuse */
> clk = tegra_clk_register_periph_gate("kfuse", "clk_m",
> TEGRA_PERIPH_ON_APB,
> @@ -1710,11 +1716,6 @@ static void __init tegra30_fixed_clk_init(void)
> 1, 0, &cml_lock);
> clk_register_clkdev(clk, "cml1", NULL);
> clks[cml1] = clk;
> -
> - /* pciex */
> - clk = clk_register_fixed_rate(NULL, "pciex", "pll_e", 0, 100000000);
> - clk_register_clkdev(clk, "pciex", NULL);
> - clks[pciex] = clk;
> }
>
> static void __init tegra30_osc_clk_init(void)
> --
> 1.7.9.5
On 06/18/2013 06:19 PM, Jonghwan Choi wrote:
> This patch looks like it should be in the 3.9-stable tree, should we apply
> it?
The PCIe driver doesn't work usefully in that release, so there's not
much point back-porting this fix; alone, it won't make PCIe work there.