This series adds support for UFS controller found in FSD SoC.
The HCI is almost same as found on other Exynos SoCs with minor
differences. This also adds the required UFS-PHY driver changes.
Patch 2/7: common change to handle different CDR offsets
*Changes since v1:
- Addressed review comments from Bart, Krzysztof, Chanho
- collected Ack-by tags
- rebased on next-20220602
Alim Akhtar (7):
dt-bindings: phy: Add FSD UFS PHY bindings
phy: samsung-ufs: move cdr offset to drvdata
phy: samsung-ufs: add support for FSD ufs phy driver
dt-bindings: ufs: exynos-ufs: add fsd compatible
ufs: ufs-exynos: add mphy apb clock mask
ufs: host: ufs-exynos: add support for fsd ufs hci
arm64: dts: fsd: add ufs device node
.../bindings/phy/samsung,ufs-phy.yaml | 1 +
.../bindings/ufs/samsung,exynos-ufs.yaml | 1 +
arch/arm64/boot/dts/tesla/fsd-evb.dts | 4 +
arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi | 14 ++
arch/arm64/boot/dts/tesla/fsd.dtsi | 29 ++++
drivers/phy/samsung/Makefile | 1 +
drivers/phy/samsung/phy-exynos7-ufs.c | 3 +
drivers/phy/samsung/phy-exynosautov9-ufs.c | 2 +
drivers/phy/samsung/phy-fsd-ufs.c | 58 +++++++
drivers/phy/samsung/phy-samsung-ufs.c | 6 +-
drivers/phy/samsung/phy-samsung-ufs.h | 3 +-
drivers/ufs/host/ufs-exynos.c | 141 +++++++++++++++++-
12 files changed, 260 insertions(+), 3 deletions(-)
create mode 100644 drivers/phy/samsung/phy-fsd-ufs.c
base-commit: 2e776ccffa840ce53ee1c21bde54cbe4bc102c3b
--
2.25.1
Adds support for Tesla Full Self-Driving (FSD) ufs phy driver.
This SoC has different cdr lock status offset.
Signed-off-by: Bharat Uppal <[email protected]>
Signed-off-by: Alim Akhtar <[email protected]>
---
drivers/phy/samsung/Makefile | 1 +
drivers/phy/samsung/phy-fsd-ufs.c | 58 +++++++++++++++++++++++++++
drivers/phy/samsung/phy-samsung-ufs.c | 3 ++
drivers/phy/samsung/phy-samsung-ufs.h | 1 +
4 files changed, 63 insertions(+)
create mode 100644 drivers/phy/samsung/phy-fsd-ufs.c
diff --git a/drivers/phy/samsung/Makefile b/drivers/phy/samsung/Makefile
index 65e4cc59403f..afb34a153e34 100644
--- a/drivers/phy/samsung/Makefile
+++ b/drivers/phy/samsung/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_PHY_SAMSUNG_UFS) += phy-exynos-ufs.o
phy-exynos-ufs-y += phy-samsung-ufs.o
phy-exynos-ufs-y += phy-exynos7-ufs.o
phy-exynos-ufs-y += phy-exynosautov9-ufs.o
+phy-exynos-ufs-y += phy-fsd-ufs.o
obj-$(CONFIG_PHY_SAMSUNG_USB2) += phy-exynos-usb2.o
phy-exynos-usb2-y += phy-samsung-usb2.o
phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4210_USB2) += phy-exynos4210-usb2.o
diff --git a/drivers/phy/samsung/phy-fsd-ufs.c b/drivers/phy/samsung/phy-fsd-ufs.c
new file mode 100644
index 000000000000..0503625bfcec
--- /dev/null
+++ b/drivers/phy/samsung/phy-fsd-ufs.c
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * UFS PHY driver data for FSD SoC
+ *
+ * Copyright (C) 2022 Samsung Electronics Co., Ltd.
+ *
+ */
+#include "phy-samsung-ufs.h"
+
+#define FSD_EMBEDDED_COMBO_PHY_CTRL 0x724
+#define FSD_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1
+#define FSD_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0)
+#define FSD_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS 0x6e
+
+static const struct samsung_ufs_phy_cfg fsd_pre_init_cfg[] = {
+ PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_ANY),
+ PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_ANY),
+ PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_ANY),
+ PHY_COMN_REG_CFG(0x017, 0x94, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x035, 0x58, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x037, 0x40, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x03b, 0x83, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x04c, 0x5b, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x04d, 0x83, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x05c, 0x14, PWR_MODE_ANY),
+ END_UFS_PHY_CFG
+};
+
+/* Calibration for HS mode series A/B */
+static const struct samsung_ufs_phy_cfg fsd_pre_pwr_hs_cfg[] = {
+ END_UFS_PHY_CFG
+};
+
+/* Calibration for HS mode series A/B atfer PMC */
+static const struct samsung_ufs_phy_cfg fsd_post_pwr_hs_cfg[] = {
+ END_UFS_PHY_CFG
+};
+
+static const struct samsung_ufs_phy_cfg *fsd_ufs_phy_cfgs[CFG_TAG_MAX] = {
+ [CFG_PRE_INIT] = fsd_pre_init_cfg,
+ [CFG_PRE_PWR_HS] = fsd_pre_pwr_hs_cfg,
+ [CFG_POST_PWR_HS] = fsd_post_pwr_hs_cfg,
+};
+
+const struct samsung_ufs_phy_drvdata fsd_ufs_phy = {
+ .cfg = fsd_ufs_phy_cfgs,
+ .isol = {
+ .offset = FSD_EMBEDDED_COMBO_PHY_CTRL,
+ .mask = FSD_EMBEDDED_COMBO_PHY_CTRL_MASK,
+ .en = FSD_EMBEDDED_COMBO_PHY_CTRL_EN,
+ },
+ .has_symbol_clk = 0,
+ .cdr_lock_status_offset = FSD_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS,
+};
diff --git a/drivers/phy/samsung/phy-samsung-ufs.c b/drivers/phy/samsung/phy-samsung-ufs.c
index 8e5ae228daa7..935c5c7a6d1e 100644
--- a/drivers/phy/samsung/phy-samsung-ufs.c
+++ b/drivers/phy/samsung/phy-samsung-ufs.c
@@ -351,6 +351,9 @@ static const struct of_device_id samsung_ufs_phy_match[] = {
}, {
.compatible = "samsung,exynosautov9-ufs-phy",
.data = &exynosautov9_ufs_phy,
+ }, {
+ .compatible = "tesla,fsd-ufs-phy",
+ .data = &fsd_ufs_phy,
},
{},
};
diff --git a/drivers/phy/samsung/phy-samsung-ufs.h b/drivers/phy/samsung/phy-samsung-ufs.h
index 965c79bbc278..74b40ef8e1d8 100644
--- a/drivers/phy/samsung/phy-samsung-ufs.h
+++ b/drivers/phy/samsung/phy-samsung-ufs.h
@@ -142,5 +142,6 @@ static inline void samsung_ufs_phy_ctrl_isol(
extern const struct samsung_ufs_phy_drvdata exynos7_ufs_phy;
extern const struct samsung_ufs_phy_drvdata exynosautov9_ufs_phy;
+extern const struct samsung_ufs_phy_drvdata fsd_ufs_phy;
#endif /* _PHY_SAMSUNG_UFS_ */
--
2.25.1
Move CDR lock offset to drv data so that it can be extended for other SoCs
which are having CDR lock at different register offset.
Signed-off-by: Bharat Uppal <[email protected]>
Signed-off-by: Alim Akhtar <[email protected]>
---
drivers/phy/samsung/phy-exynos7-ufs.c | 3 +++
drivers/phy/samsung/phy-exynosautov9-ufs.c | 2 ++
drivers/phy/samsung/phy-samsung-ufs.c | 3 ++-
drivers/phy/samsung/phy-samsung-ufs.h | 2 +-
4 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/phy/samsung/phy-exynos7-ufs.c b/drivers/phy/samsung/phy-exynos7-ufs.c
index 7c9008e163db..dca21fb6e2a6 100644
--- a/drivers/phy/samsung/phy-exynos7-ufs.c
+++ b/drivers/phy/samsung/phy-exynos7-ufs.c
@@ -11,6 +11,8 @@
#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1
#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0)
+#define EXYNOS7_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS 0x5e
+
/* Calibration for phy initialization */
static const struct samsung_ufs_phy_cfg exynos7_pre_init_cfg[] = {
PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_ANY),
@@ -74,4 +76,5 @@ const struct samsung_ufs_phy_drvdata exynos7_ufs_phy = {
.en = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN,
},
.has_symbol_clk = 1,
+ .cdr_lock_status_offset = EXYNOS7_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS,
};
diff --git a/drivers/phy/samsung/phy-exynosautov9-ufs.c b/drivers/phy/samsung/phy-exynosautov9-ufs.c
index 36398a15c2db..1572b985c70d 100644
--- a/drivers/phy/samsung/phy-exynosautov9-ufs.c
+++ b/drivers/phy/samsung/phy-exynosautov9-ufs.c
@@ -10,6 +10,7 @@
#define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL 0x728
#define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1
#define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0)
+#define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS 0x5e
#define PHY_TRSV_REG_CFG_AUTOV9(o, v, d) \
PHY_TRSV_REG_CFG_OFFSET(o, v, d, 0x50)
@@ -64,4 +65,5 @@ const struct samsung_ufs_phy_drvdata exynosautov9_ufs_phy = {
.en = EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_EN,
},
.has_symbol_clk = 0,
+ .cdr_lock_status_offset = EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS,
};
diff --git a/drivers/phy/samsung/phy-samsung-ufs.c b/drivers/phy/samsung/phy-samsung-ufs.c
index 602ddef259eb..8e5ae228daa7 100644
--- a/drivers/phy/samsung/phy-samsung-ufs.c
+++ b/drivers/phy/samsung/phy-samsung-ufs.c
@@ -63,7 +63,8 @@ static int samsung_ufs_phy_wait_for_lock_acq(struct phy *phy)
}
err = readl_poll_timeout(
- ufs_phy->reg_pma + PHY_APB_ADDR(PHY_CDR_LOCK_STATUS),
+ ufs_phy->reg_pma +
+ PHY_APB_ADDR(ufs_phy->drvdata->cdr_lock_status_offset),
val, (val & PHY_CDR_LOCK_BIT), sleep_us, timeout_us);
if (err)
dev_err(ufs_phy->dev,
diff --git a/drivers/phy/samsung/phy-samsung-ufs.h b/drivers/phy/samsung/phy-samsung-ufs.h
index 91a0e9f94f98..965c79bbc278 100644
--- a/drivers/phy/samsung/phy-samsung-ufs.h
+++ b/drivers/phy/samsung/phy-samsung-ufs.h
@@ -40,7 +40,6 @@
/* UFS PHY registers */
#define PHY_PLL_LOCK_STATUS 0x1e
-#define PHY_CDR_LOCK_STATUS 0x5e
#define PHY_PLL_LOCK_BIT BIT(5)
#define PHY_CDR_LOCK_BIT BIT(4)
@@ -109,6 +108,7 @@ struct samsung_ufs_phy_drvdata {
u32 en;
} isol;
bool has_symbol_clk;
+ u32 cdr_lock_status_offset;
};
struct samsung_ufs_phy {
--
2.25.1
Adds support of UFS HCI which is found in Tesla Full Self-Driving (FSD)
SoC.
Signed-off-by: Bharat Uppal <[email protected]>
Signed-off-by: Alim Akhtar <[email protected]>
---
drivers/ufs/host/ufs-exynos.c | 138 ++++++++++++++++++++++++++++++++++
1 file changed, 138 insertions(+)
diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c
index cc128aff8871..7e0ab8a8662e 100644
--- a/drivers/ufs/host/ufs-exynos.c
+++ b/drivers/ufs/host/ufs-exynos.c
@@ -1474,6 +1474,102 @@ static int exynosauto_ufs_vh_init(struct ufs_hba *hba)
return 0;
}
+static int fsd_ufs_pre_link(struct exynos_ufs *ufs)
+{
+ int i;
+ struct ufs_hba *hba = ufs->hba;
+
+ ufshcd_dme_set(hba, UIC_ARG_MIB(0x9514), 1000000000L / ufs->mclk_rate);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(0x201), 0x12);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40);
+
+ for_each_ufs_tx_lane(ufs, i) {
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xAA, i), 1000000000L / ufs->mclk_rate);
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8F, i), 0x3F);
+ }
+
+ for_each_ufs_rx_lane(ufs, i) {
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x12, i), 1000000000L / ufs->mclk_rate);
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x5C, i), 0x38);
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0F, i), 0x0);
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x65, i), 0x1);
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x69, i), 0x1);
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x21, i), 0x0);
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x22, i), 0x0);
+ }
+
+ ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(0x9536), 0x4E20);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(0x9564), 0x2e820183);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0x0);
+
+ exynos_ufs_establish_connt(ufs);
+
+ return 0;
+}
+
+static int fsd_ufs_post_link(struct exynos_ufs *ufs)
+{
+ int i;
+ struct ufs_hba *hba = ufs->hba;
+ u32 hw_cap_min_tactivate;
+ u32 peer_rx_min_actv_time_cap;
+ u32 max_rx_hibern8_time_cap;
+
+ ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(0x8F, 4),
+ &hw_cap_min_tactivate); /* HW Capability of MIN_TACTIVATE */
+ ufshcd_dme_get(hba, UIC_ARG_MIB(0x15A8),
+ &peer_rx_min_actv_time_cap); /* PA_TActivate */
+ ufshcd_dme_get(hba, UIC_ARG_MIB(0x15A7),
+ &max_rx_hibern8_time_cap); /* PA_Hibern8Time */
+
+ if (peer_rx_min_actv_time_cap >= hw_cap_min_tactivate)
+ ufshcd_dme_peer_set(hba, UIC_ARG_MIB(0x15A8),
+ peer_rx_min_actv_time_cap + 1);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(0x15A7), max_rx_hibern8_time_cap + 1);
+
+ ufshcd_dme_set(hba, UIC_ARG_MIB(0x9529), 0x01);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(0x15A4), 0xFA);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(0x9529), 0x00);
+
+ ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40);
+
+ for_each_ufs_rx_lane(ufs, i) {
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x35, i), 0x05);
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x73, i), 0x01);
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x41, i), 0x02);
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x42, i), 0xAC);
+ }
+
+ ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0);
+
+ return 0;
+}
+
+static int fsd_ufs_pre_pwr_change(struct exynos_ufs *ufs,
+ struct ufs_pa_layer_attr *pwr)
+{
+ struct ufs_hba *hba = ufs->hba;
+
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), 0x1);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), 0x1);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(DL_FC0PROTTIMEOUTVAL), 8064);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(DL_TC0REPLAYTIMEOUTVAL), 28224);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(DL_AFC0REQTIMEOUTVAL), 20160);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 12000);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), 32000);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), 16000);
+
+ unipro_writel(ufs, 8064, 0x7888);
+ unipro_writel(ufs, 28224, 0x788C);
+ unipro_writel(ufs, 20160, 0x7890);
+ unipro_writel(ufs, 12000, 0x78B8);
+ unipro_writel(ufs, 32000, 0x78BC);
+ unipro_writel(ufs, 16000, 0x78C0);
+
+ return 0;
+}
+
static struct ufs_hba_variant_ops ufs_hba_exynos_ops = {
.name = "exynos_ufs",
.init = exynos_ufs_init,
@@ -1596,6 +1692,46 @@ static struct exynos_ufs_drv_data exynos_ufs_drvs = {
.post_pwr_change = exynos7_ufs_post_pwr_change,
};
+static struct exynos_ufs_uic_attr fsd_uic_attr = {
+ .tx_trailingclks = 0x10,
+ .tx_dif_p_nsec = 3000000, /* unit: ns */
+ .tx_dif_n_nsec = 1000000, /* unit: ns */
+ .tx_high_z_cnt_nsec = 20000, /* unit: ns */
+ .tx_base_unit_nsec = 100000, /* unit: ns */
+ .tx_gran_unit_nsec = 4000, /* unit: ns */
+ .tx_sleep_cnt = 1000, /* unit: ns */
+ .tx_min_activatetime = 0xa,
+ .rx_filler_enable = 0x2,
+ .rx_dif_p_nsec = 1000000, /* unit: ns */
+ .rx_hibern8_wait_nsec = 4000000, /* unit: ns */
+ .rx_base_unit_nsec = 100000, /* unit: ns */
+ .rx_gran_unit_nsec = 4000, /* unit: ns */
+ .rx_sleep_cnt = 1280, /* unit: ns */
+ .rx_stall_cnt = 320, /* unit: ns */
+ .rx_hs_g1_sync_len_cap = SYNC_LEN_COARSE(0xf),
+ .rx_hs_g2_sync_len_cap = SYNC_LEN_COARSE(0xf),
+ .rx_hs_g3_sync_len_cap = SYNC_LEN_COARSE(0xf),
+ .rx_hs_g1_prep_sync_len_cap = PREP_LEN(0xf),
+ .rx_hs_g2_prep_sync_len_cap = PREP_LEN(0xf),
+ .rx_hs_g3_prep_sync_len_cap = PREP_LEN(0xf),
+ .pa_dbg_option_suite = 0x2E820183,
+};
+
+struct exynos_ufs_drv_data fsd_ufs_drvs = {
+ .uic_attr = &fsd_uic_attr,
+ .quirks = UFSHCD_QUIRK_PRDT_BYTE_GRAN |
+ UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR |
+ UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR |
+ UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR,
+ .opts = EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL |
+ EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL |
+ EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR |
+ EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX,
+ .pre_link = fsd_ufs_pre_link,
+ .post_link = fsd_ufs_post_link,
+ .pre_pwr_change = fsd_ufs_pre_pwr_change,
+};
+
static const struct of_device_id exynos_ufs_of_match[] = {
{ .compatible = "samsung,exynos7-ufs",
.data = &exynos_ufs_drvs },
@@ -1603,6 +1739,8 @@ static const struct of_device_id exynos_ufs_of_match[] = {
.data = &exynosauto_ufs_drvs },
{ .compatible = "samsung,exynosautov9-ufs-vh",
.data = &exynosauto_ufs_vh_drvs },
+ { .compatible = "tesla,fsd-ufs",
+ .data = &fsd_ufs_drvs },
{},
};
--
2.25.1
Adds tesla,fsd-ufs compatible for Tesla FSD SoC.
Signed-off-by: Bharat Uppal <[email protected]>
Signed-off-by: Alim Akhtar <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
---
Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
index c949eb617313..2c715eec48b8 100644
--- a/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
+++ b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
@@ -21,6 +21,7 @@ properties:
- samsung,exynos7-ufs
- samsung,exynosautov9-ufs
- samsung,exynosautov9-ufs-vh
+ - tesla,fsd-ufs
reg:
items:
--
2.25.1
Add tesla,fsd-ufs-phy compatible for Tesla Full Self-Driving (FSD) SoC.
Signed-off-by: Bharat Uppal <[email protected]>
Signed-off-by: Alim Akhtar <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
---
Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
index f6ed1a005e7a..ee354bf37c64 100644
--- a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
@@ -17,6 +17,7 @@ properties:
enum:
- samsung,exynos7-ufs-phy
- samsung,exynosautov9-ufs-phy
+ - tesla,fsd-ufs-phy
reg:
maxItems: 1
--
2.25.1
Adds FSD ufs device node and enable the same for fsd platform.
This also adds the required pin configuration for the same.
Signed-off-by: Bharat Uppal <[email protected]>
Signed-off-by: Alim Akhtar <[email protected]>
---
arch/arm64/boot/dts/tesla/fsd-evb.dts | 4 +++
arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi | 14 +++++++++++
arch/arm64/boot/dts/tesla/fsd.dtsi | 29 ++++++++++++++++++++++
3 files changed, 47 insertions(+)
diff --git a/arch/arm64/boot/dts/tesla/fsd-evb.dts b/arch/arm64/boot/dts/tesla/fsd-evb.dts
index 5af560c1b5e6..1db6ddf03f01 100644
--- a/arch/arm64/boot/dts/tesla/fsd-evb.dts
+++ b/arch/arm64/boot/dts/tesla/fsd-evb.dts
@@ -37,3 +37,7 @@ &fin_pll {
&serial_0 {
status = "okay";
};
+
+&ufs {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
index d4d0cb005712..387a41e251d5 100644
--- a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
@@ -50,6 +50,20 @@ gpf5: gpf5-gpio-bank {
interrupt-controller;
#interrupt-cells = <2>;
};
+
+ ufs_rst_n: ufs-rst-n-pins {
+ samsung,pins = "gpf5-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV2>;
+ };
+
+ ufs_refclk_out: ufs-refclk-out-pins {
+ samsung,pins = "gpf5-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV2>;
+ };
};
&pinctrl_peric {
diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi
index af39655331de..7d1acf8f6466 100644
--- a/arch/arm64/boot/dts/tesla/fsd.dtsi
+++ b/arch/arm64/boot/dts/tesla/fsd.dtsi
@@ -740,6 +740,35 @@ timer@10040000 {
clocks = <&fin_pll>, <&clock_imem IMEM_MCT_PCLK>;
clock-names = "fin_pll", "mct";
};
+
+ ufs: ufs@15120000 {
+ compatible = "tesla,fsd-ufs";
+ reg = <0x0 0x15120000 0x0 0x200>, /* 0: HCI standard */
+ <0x0 0x15121100 0x0 0x200>, /* 1: Vendor specified */
+ <0x0 0x15110000 0x0 0x8000>, /* 2: UNIPRO */
+ <0x0 0x15130000 0x0 0x100>; /* 3: UFS protector */
+ reg-names = "hci", "vs_hci", "unipro", "ufsp";
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock_fsys0 UFS0_TOP0_HCLK_BUS>,
+ <&clock_fsys0 UFS0_TOP0_CLK_UNIPRO>;
+ clock-names = "core_clk", "sclk_unipro_main";
+ freq-table-hz = <0 0>, <0 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
+ phys = <&ufs_phy>;
+ phy-names = "ufs-phy";
+ status = "disabled";
+ };
+
+ ufs_phy: ufs-phy@15124000 {
+ compatible = "tesla,fsd-ufs-phy";
+ reg = <0x0 0x15124000 0x0 0x800>;
+ reg-names = "phy-pma";
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ #phy-cells = <0>;
+ clocks = <&clock_fsys0 UFS0_MPHY_REFCLK_IXTAL26>;
+ clock-names = "ref_clk";
+ };
};
};
--
2.25.1
On Fri, 3 Jun 2022 21:17:14 +0530, Alim Akhtar wrote:
> Adds FSD ufs device node and enable the same for fsd platform.
> This also adds the required pin configuration for the same.
>
>
Applied, thanks!
[7/7] arm64: dts: fsd: add ufs device node
https://git.kernel.org/krzk/linux/c/c75f5c9e11cf71e77c5cb8f0e082e5ee1e71545a
Best regards,
--
Krzysztof Kozlowski <[email protected]>
> Subject: [PATCH v2 3/7] phy: samsung-ufs: add support for FSD ufs phy
> driver
>
> Adds support for Tesla Full Self-Driving (FSD) ufs phy driver.
> This SoC has different cdr lock status offset.
>
> Signed-off-by: Bharat Uppal <[email protected]>
> Signed-off-by: Alim Akhtar <[email protected]>
Reviewed-by: Chanho Park <[email protected]>
As you may know, it seems to be rebased if below patchset goes first.
https://lore.kernel.org/linux-phy/[email protected]/T/#t
Best Regards,
Chanho Park
> Subject: [PATCH v2 6/7] ufs: host: ufs-exynos: add support for fsd ufs hci
>
> Adds support of UFS HCI which is found in Tesla Full Self-Driving (FSD)
> SoC.
>
> Signed-off-by: Bharat Uppal <[email protected]>
> Signed-off-by: Alim Akhtar <[email protected]>
> ---
> drivers/ufs/host/ufs-exynos.c | 138 ++++++++++++++++++++++++++++++++++
> 1 file changed, 138 insertions(+)
>
> diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c
> index cc128aff8871..7e0ab8a8662e 100644
> --- a/drivers/ufs/host/ufs-exynos.c
> +++ b/drivers/ufs/host/ufs-exynos.c
> @@ -1474,6 +1474,102 @@ static int exynosauto_ufs_vh_init(struct ufs_hba
> *hba)
> return 0;
> }
>
> +static int fsd_ufs_pre_link(struct exynos_ufs *ufs) {
> + int i;
> + struct ufs_hba *hba = ufs->hba;
> +
> + ufshcd_dme_set(hba, UIC_ARG_MIB(0x9514), 1000000000L / ufs-
> >mclk_rate);
> + ufshcd_dme_set(hba, UIC_ARG_MIB(0x201), 0x12);
> + ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40);
> +
> + for_each_ufs_tx_lane(ufs, i) {
> + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xAA, i), 1000000000L /
> ufs->mclk_rate);
Use NSEC_PER_SEC and DIV_ROUND_UP as well.
> + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8F, i), 0x3F);
> + }
> +
> + for_each_ufs_rx_lane(ufs, i) {
> + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x12, i), 1000000000L /
> ufs->mclk_rate);
> + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x5C, i), 0x38);
> + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0F, i), 0x0);
> + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x65, i), 0x1);
> + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x69, i), 0x1);
> + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x21, i), 0x0);
> + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x22, i), 0x0);
> + }
> +
> + ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0);
> + ufshcd_dme_set(hba, UIC_ARG_MIB(0x9536), 0x4E20);
> + ufshcd_dme_set(hba, UIC_ARG_MIB(0x9564), 0x2e820183);
> + ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0x0);
> +
> + exynos_ufs_establish_connt(ufs);
> +
> + return 0;
> +}
> +
> +static int fsd_ufs_post_link(struct exynos_ufs *ufs) {
> + int i;
> + struct ufs_hba *hba = ufs->hba;
> + u32 hw_cap_min_tactivate;
> + u32 peer_rx_min_actv_time_cap;
> + u32 max_rx_hibern8_time_cap;
> +
> + ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(0x8F, 4),
> + &hw_cap_min_tactivate); /* HW Capability of
> MIN_TACTIVATE */
> + ufshcd_dme_get(hba, UIC_ARG_MIB(0x15A8),
> + &peer_rx_min_actv_time_cap); /* PA_TActivate */
> + ufshcd_dme_get(hba, UIC_ARG_MIB(0x15A7),
> + &max_rx_hibern8_time_cap); /* PA_Hibern8Time */
> +
> + if (peer_rx_min_actv_time_cap >= hw_cap_min_tactivate)
> + ufshcd_dme_peer_set(hba, UIC_ARG_MIB(0x15A8),
> + peer_rx_min_actv_time_cap + 1);
> + ufshcd_dme_set(hba, UIC_ARG_MIB(0x15A7), max_rx_hibern8_time_cap +
> 1);
> +
> + ufshcd_dme_set(hba, UIC_ARG_MIB(0x9529), 0x01);
> + ufshcd_dme_set(hba, UIC_ARG_MIB(0x15A4), 0xFA);
> + ufshcd_dme_set(hba, UIC_ARG_MIB(0x9529), 0x00);
> +
> + ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40);
> +
> + for_each_ufs_rx_lane(ufs, i) {
> + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x35, i), 0x05);
> + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x73, i), 0x01);
> + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x41, i), 0x02);
> + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x42, i), 0xAC);
> + }
> +
> + ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0);
> +
> + return 0;
> +}
> +
> +static int fsd_ufs_pre_pwr_change(struct exynos_ufs *ufs,
> + struct ufs_pa_layer_attr *pwr)
> +{
> + struct ufs_hba *hba = ufs->hba;
> +
> + ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), 0x1);
> + ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), 0x1);
> + ufshcd_dme_set(hba, UIC_ARG_MIB(DL_FC0PROTTIMEOUTVAL), 8064);
> + ufshcd_dme_set(hba, UIC_ARG_MIB(DL_TC0REPLAYTIMEOUTVAL), 28224);
> + ufshcd_dme_set(hba, UIC_ARG_MIB(DL_AFC0REQTIMEOUTVAL), 20160);
> + ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 12000);
> + ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), 32000);
> + ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), 16000);
If you set custom pwrmode setting, you'll need to set UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING.
> +
> + unipro_writel(ufs, 8064, 0x7888);
> + unipro_writel(ufs, 28224, 0x788C);
> + unipro_writel(ufs, 20160, 0x7890);
Duplicated setting with above dme_set calls. (DL_FC0PROTTIMEOUTVAL / DL_TC0REPLAYTIMEOUTVAL / DL_AFC0REQTIMEOUTVAL)
Unipro registers are mirrored and you can use unipro_* APIs but need to choose one of them.
> + unipro_writel(ufs, 12000, 0x78B8);
> + unipro_writel(ufs, 32000, 0x78BC);
> + unipro_writel(ufs, 16000, 0x78C0);
Put some documents the register as DME_POWERMODE_REQ_REMOTEL2TIMER0/1/2 or use macro for them.
Best Regards,
Chanho Park
> Subject: [PATCH v2 2/7] phy: samsung-ufs: move cdr offset to drvdata
>
> Move CDR lock offset to drv data so that it can be extended for other SoCs
> which are having CDR lock at different register offset.
>
> Signed-off-by: Bharat Uppal <[email protected]>
> Signed-off-by: Alim Akhtar <[email protected]>
Reviewed-by: Chanho Park <[email protected]>
Best Regards,
Chanho Park