The current arasan sdhci PHY configuration isn't compatible
with the PHY on Intel's LGM(Lightning Mountain) SoC devices.
Therefore, add a new compatible, to adapt the Intel's LGM
SDXC PHY with arasan-sdhc controller to configure the PHY.
Linux code base : V5.4-rc1
Ramuthevar Vadivel Murugan (2):
dt-bindings: mmc: sdhci-of-arasan: Add new compatible for Intel LGM
SDXC
mmc: sdhci-of-arasan: Add Support for Intel LGM SDXC
Documentation/devicetree/bindings/mmc/arasan,sdhci.txt | 17 +++++++++++++++++
drivers/mmc/host/sdhci-of-arasan.c | 15 +++++++++++++++
2 files changed, 32 insertions(+)
--
2.11.0
From: Ramuthevar Vadivel Murugan <[email protected]>
Add a new compatible to use the sdhc-arasan host controller driver
with the eMMC PHY on Intel's Lightning Mountain(LGM) SoC.
Signed-off-by: Ramuthevar Vadivel Murugan <[email protected]>
---
Documentation/devicetree/bindings/mmc/arasan,sdhci.txt | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
index 7ca0aa7ccc0b..eb78d9a28c8b 100644
--- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
+++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
@@ -19,6 +19,8 @@ Required Properties:
Note: This binding has been deprecated and moved to [5].
- "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1": Intel LGM eMMC PHY
For this device it is strongly suggested to include arasan,soc-ctl-syscon.
+ - "intel,lgm-sdhci-5.1-sdxc", "arasan,sdhci-5.1": Intel LGM SDXC PHY
+ For this device it is strongly suggested to include arasan,soc-ctl-syscon.
[5] Documentation/devicetree/bindings/mmc/sdhci-am654.txt
@@ -97,3 +99,18 @@ Example:
phy-names = "phy_arasan";
arasan,soc-ctl-syscon = <&sysconf>;
};
+
+ sdxc: sdhci@ec600000 {
+ compatible = "arasan,sdhci-5.1", "intel,lgm-sdhci-5.1-sdxc";
+ reg = <0xec600000 0x300>;
+ interrupt-parent = <&ioapic1>;
+ interrupts = <43 1>;
+ clocks = <&cgu0 LGM_CLK_SDIO>, <&cgu0 LGM_CLK_NGI>,
+ <&cgu0 LGM_GCLK_SDXC>;
+ clock-names = "clk_xin", "clk_ahb", "gate";
+ clock-output-names = "sdxc_cardclock";
+ #clock-cells = <0>;
+ phys = <&sdxc_phy>;
+ phy-names = "phy_arasan";
+ arasan,soc-ctl-syscon = <&sysconf>;
+ };
--
2.11.0
From: Ramuthevar Vadivel Murugan <[email protected]>
The current arasan sdhci PHY configuration isn't compatible
with the PHY on Intel's LGM(Lightning Mountain) SoC devices.
Therefore, add a new compatible, to adapt the Intel's LGM
SDXC PHY with arasan-sdhc controller to configure the PHY.
Signed-off-by: Ramuthevar Vadivel Murugan <[email protected]>
---
drivers/mmc/host/sdhci-of-arasan.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c
index 7023cbec4017..55de839a8a5e 100644
--- a/drivers/mmc/host/sdhci-of-arasan.c
+++ b/drivers/mmc/host/sdhci-of-arasan.c
@@ -120,6 +120,12 @@ static const struct sdhci_arasan_soc_ctl_map intel_lgm_emmc_soc_ctl_map = {
.hiword_update = false,
};
+static const struct sdhci_arasan_soc_ctl_map intel_lgm_sdxc_soc_ctl_map = {
+ .baseclkfreq = { .reg = 0x80, .width = 8, .shift = 2 },
+ .clockmultiplier = { .reg = 0, .width = -1, .shift = -1 },
+ .hiword_update = false,
+};
+
/**
* sdhci_arasan_syscon_write - Write to a field in soc_ctl registers
*
@@ -384,6 +390,11 @@ static struct sdhci_arasan_of_data intel_lgm_emmc_data = {
.pdata = &sdhci_arasan_cqe_pdata,
};
+static struct sdhci_arasan_of_data intel_lgm_sdxc_data = {
+ .soc_ctl_map = &intel_lgm_sdxc_soc_ctl_map,
+ .pdata = &sdhci_arasan_cqe_pdata,
+};
+
#ifdef CONFIG_PM_SLEEP
/**
* sdhci_arasan_suspend - Suspend method for the driver
@@ -489,6 +500,10 @@ static const struct of_device_id sdhci_arasan_of_match[] = {
.compatible = "intel,lgm-sdhci-5.1-emmc",
.data = &intel_lgm_emmc_data,
},
+ {
+ .compatible = "intel,lgm-sdhci-5.1-sdxc",
+ .data = &intel_lgm_sdxc_data,
+ },
/* Generic compatible below here */
{
.compatible = "arasan,sdhci-8.9a",
--
2.11.0
On 3/10/19 7:00 AM, Ramuthevar,Vadivel MuruganX wrote:
> From: Ramuthevar Vadivel Murugan <[email protected]>
>
> The current arasan sdhci PHY configuration isn't compatible
> with the PHY on Intel's LGM(Lightning Mountain) SoC devices.
>
> Therefore, add a new compatible, to adapt the Intel's LGM
> SDXC PHY with arasan-sdhc controller to configure the PHY.
>
> Signed-off-by: Ramuthevar Vadivel Murugan <[email protected]>
Aren't these patches already in v5.4-rc1
Hi Adrian,
Thank you for the comments.
On 3/10/2019 3:02 PM, Adrian Hunter wrote:
> On 3/10/19 7:00 AM, Ramuthevar,Vadivel MuruganX wrote:
>> From: Ramuthevar Vadivel Murugan <[email protected]>
>>
>> The current arasan sdhci PHY configuration isn't compatible
>> with the PHY on Intel's LGM(Lightning Mountain) SoC devices.
>>
>> Therefore, add a new compatible, to adapt the Intel's LGM
>> SDXC PHY with arasan-sdhc controller to configure the PHY.
>>
>> Signed-off-by: Ramuthevar Vadivel Murugan <[email protected]>
> Aren't these patches already in v5.4-rc1
No, these patches are not there in v5.4-rc1.
The one which is in v5.4-rc1 supports only eMMC, does not SD/SDIO, so
these patches are required.
---
With Best Regards
Vadivel Murugan
Hi Adrian,
On 3/10/2019 3:46 PM, Ramuthevar, Vadivel MuruganX wrote:
> Hi Adrian,
>
> Thank you for the comments.
>
> On 3/10/2019 3:02 PM, Adrian Hunter wrote:
>> On 3/10/19 7:00 AM, Ramuthevar,Vadivel MuruganX wrote:
>>> From: Ramuthevar Vadivel Murugan
>>> <[email protected]>
>>>
>>> The current arasan sdhci PHY configuration isn't compatible
>>> with the PHY on Intel's LGM(Lightning Mountain) SoC devices.
>>>
>>> Therefore, add a new compatible, to adapt the Intel's LGM
>>> SDXC PHY with arasan-sdhc controller to configure the PHY.
>>>
>>> Signed-off-by: Ramuthevar Vadivel Murugan
>>> <[email protected]>
>> Aren't these patches already in v5.4-rc1
>
> No, these patches are not there in v5.4-rc1.
>
> The one which is in v5.4-rc1 supports only eMMC, does not SD/SDIO, so
> these patches are required.
>
can you please provide your suggestions and opinions further on the
above reply, to proceed, Thanks!
> ---
> With Best Regards
> Vadivel Murugan
On 3/10/19 7:00 AM, Ramuthevar,Vadivel MuruganX wrote:
> From: Ramuthevar Vadivel Murugan <[email protected]>
>
> The current arasan sdhci PHY configuration isn't compatible
> with the PHY on Intel's LGM(Lightning Mountain) SoC devices.
>
> Therefore, add a new compatible, to adapt the Intel's LGM
> SDXC PHY with arasan-sdhc controller to configure the PHY.
>
> Signed-off-by: Ramuthevar Vadivel Murugan <[email protected]>
Acked-by: Adrian Hunter <[email protected]>
> ---
> drivers/mmc/host/sdhci-of-arasan.c | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c
> index 7023cbec4017..55de839a8a5e 100644
> --- a/drivers/mmc/host/sdhci-of-arasan.c
> +++ b/drivers/mmc/host/sdhci-of-arasan.c
> @@ -120,6 +120,12 @@ static const struct sdhci_arasan_soc_ctl_map intel_lgm_emmc_soc_ctl_map = {
> .hiword_update = false,
> };
>
> +static const struct sdhci_arasan_soc_ctl_map intel_lgm_sdxc_soc_ctl_map = {
> + .baseclkfreq = { .reg = 0x80, .width = 8, .shift = 2 },
> + .clockmultiplier = { .reg = 0, .width = -1, .shift = -1 },
> + .hiword_update = false,
> +};
> +
> /**
> * sdhci_arasan_syscon_write - Write to a field in soc_ctl registers
> *
> @@ -384,6 +390,11 @@ static struct sdhci_arasan_of_data intel_lgm_emmc_data = {
> .pdata = &sdhci_arasan_cqe_pdata,
> };
>
> +static struct sdhci_arasan_of_data intel_lgm_sdxc_data = {
> + .soc_ctl_map = &intel_lgm_sdxc_soc_ctl_map,
> + .pdata = &sdhci_arasan_cqe_pdata,
> +};
> +
> #ifdef CONFIG_PM_SLEEP
> /**
> * sdhci_arasan_suspend - Suspend method for the driver
> @@ -489,6 +500,10 @@ static const struct of_device_id sdhci_arasan_of_match[] = {
> .compatible = "intel,lgm-sdhci-5.1-emmc",
> .data = &intel_lgm_emmc_data,
> },
> + {
> + .compatible = "intel,lgm-sdhci-5.1-sdxc",
> + .data = &intel_lgm_sdxc_data,
> + },
> /* Generic compatible below here */
> {
> .compatible = "arasan,sdhci-8.9a",
>
On Wed, Oct 09, 2019 at 09:06:16AM +0800, Ramuthevar, Vadivel MuruganX wrote:
> Hi Adrian,
>
> ??? Thank you for the Acked-by, will add *Acked-by* in the next-patch.
Please, stop top-posting.
Besides that, there is no need for next version if the only comments you got
are ACKs. Rb:s, etc.
--
With Best Regards,
Andy Shevchenko
Hi Andy,
On 9/10/2019 5:40 PM, Andy Shevchenko wrote:
> On Wed, Oct 09, 2019 at 09:06:16AM +0800, Ramuthevar, Vadivel MuruganX wrote:
>> Hi Adrian,
>>
>> Thank you for the Acked-by, will add *Acked-by* in the next-patch.
> Please, stop top-posting.
>
> Besides that, there is no need for next version if the only comments you got
> are ACKs. Rb:s, etc.
Sure, Thanks!
---
Regards
Vadivel