This patchset final purpose is add PCIe driver for StarFive JH7110 SoC.
JH7110 using PLDA XpressRICH PCIe IP. Microchip PolarFire Using the
same IP and have commit their codes, which are mixed with PLDA
controller codes and Microchip platform codes.
For re-use the PLDA controller codes, I request refactoring microchip
codes, move PLDA common codes to PLDA files.
Desigware and Cadence is good example for refactoring codes.
So first step is extract the PLDA common codes from microchip, and
refactoring the microchip codes.(patch1 - 8)
Then, add Starfive codes. (patch9 - 11)
This patchset is base on v6.5
The patch is base on Daire microchip commit,(accepted, not merge in mainline now)
https://patchwork.kernel.org/project/linux-pci/cover/[email protected]/
patch11 dts patch base on stg clk patchset and syscon patch(these will be merged in 6.6-rcx).
https://patchwork.kernel.org/project/linux-riscv/cover/[email protected]/
https://patchwork.kernel.org/project/linux-riscv/patch/[email protected]/
patch1 is move PLDA XpressRICH PCIe host common properties dt-binding
docs from microchip,pcie-host.yaml
patch2 is move PolarFire codes to PLDA directory.
patch3 is move PLDA IP register macros to plda-pcie.h
patch4 is rename data structure setup and IRQ functions in microchip codes.
patch5 is move the patch4 functions to common file pcie-plda-host.c
patch6 is Add PLDA event interrupt codes and IRQ domain ops.
patch7 is rename IRQ init function in microchip codes, prepare to move
the common file pcie-plda-host.c,
patch8 is move IRQ init functions and other functions to pcie-plda-host.c
patch9 is add StarFive JH7110 PCIe dt-binding doc.
patch10 is add StarFive JH7110 Soc PCIe codes.
patch11 is Starfive dts config
previous version:
v1:https://patchwork.kernel.org/project/linux-pci/cover/[email protected]/
v2:https://patchwork.kernel.org/project/linux-pci/cover/[email protected]/
v3:https://patchwork.kernel.org/project/linux-pci/cover/[email protected]/
v4:https://patchwork.kernel.org/project/linux-pci/cover/[email protected]/
change:
v5:
patch 6 -8:
- Some variables names changed (evt->event).
- plda_handle_event() using a unify callback function to get events
num.
- Add plda_event_ops data structure.
patch 10:
plda_event_ops changed which is related to patch 6- 8 changed.
v4:
patch 3:
Copy the interrupt events macros to pcie-plda-host.c
patch 7 - 8:
get_events() change in patch 7. Patch 8 is just move the codes.
other change:
All the functions in commit message add ().
v3:
patch 2- 8:
- splite refactoring patches to multiple patch.
- rename plda_pcie to plda_pcie_rp. Maybe other vendor will
upstream PLDA ep codes.
patch 9:
- Remove the redundant reference.
- move the offset value to codes in starfive,stg-syscon
- change reset-gpio to prest-gpio.
patch10:
- Add 100ms delay after preset for PCIe 6.0 spec.
- stg-syscon related modification.
patch11:
- Add dts configure.
v2:
patch1:
- squash dt-bindings patches to patch1
- add 'required' list.
- plda doc rename to plda,xpressrich-axi-common.yaml
patch2 - 8:
- squash the microchip modification patch.
patch9:
- remove the plda common required property.
patch10:
- Sync the hide rc bar ops with config read function.
- Revert the T_PVPERL to 100ms and add comments for the source.
- Replace the link check function by the standard link ops.
- Convert to new pm ops marcos.
- Some formats modification.
- pcie-plda-host modification merge to patch4.
other:
- remove the pcie-plda-plat.c
- remove the starfive dts patch first. for it depends on
stg clock and syscon setting.
Minda Chen (11):
dt-bindings: PCI: Add PLDA XpressRICH PCIe host common properties
PCI: microchip: Move pcie-microchip-host.c to plda directory
PCI: microchip: Move PLDA IP register macros to pcie-plda.h
PCI: microchip: Rename data structure and functions
PCI: plda: Move the common functions to pcie-plda-host.c
PCI: plda: Add event interrupt codes and IRQ domain ops
PCI: microchip: Rename IRQ init function
PCI: microchip: Move IRQ init functions to pcie-plda-host.c
dt-bindings: PCI: Add StarFive JH7110 PCIe controller
PCI: starfive: Add JH7110 PCIe controller
riscv: dts: starfive: add PCIe dts configuration for JH7110
.../bindings/pci/microchip,pcie-host.yaml | 55 +-
.../pci/plda,xpressrich3-axi-common.yaml | 75 ++
.../bindings/pci/starfive,jh7110-pcie.yaml | 120 ++++
MAINTAINERS | 17 +-
.../jh7110-starfive-visionfive-2.dtsi | 64 ++
arch/riscv/boot/dts/starfive/jh7110.dtsi | 86 +++
drivers/pci/controller/Kconfig | 9 +-
drivers/pci/controller/Makefile | 2 +-
drivers/pci/controller/plda/Kconfig | 30 +
drivers/pci/controller/plda/Makefile | 4 +
.../{ => plda}/pcie-microchip-host.c | 605 ++--------------
drivers/pci/controller/plda/pcie-plda-host.c | 656 ++++++++++++++++++
drivers/pci/controller/plda/pcie-plda.h | 239 +++++++
drivers/pci/controller/plda/pcie-starfive.c | 460 ++++++++++++
14 files changed, 1817 insertions(+), 605 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pci/plda,xpressrich3-axi-common.yaml
create mode 100644 Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml
create mode 100644 drivers/pci/controller/plda/Kconfig
create mode 100644 drivers/pci/controller/plda/Makefile
rename drivers/pci/controller/{ => plda}/pcie-microchip-host.c (54%)
create mode 100644 drivers/pci/controller/plda/pcie-plda-host.c
create mode 100644 drivers/pci/controller/plda/pcie-plda.h
create mode 100644 drivers/pci/controller/plda/pcie-starfive.c
base-commit: 2dde18cd1d8fac735875f2e4987f11817cc0bc2c
--
2.17.1
Add PCIe dts configuraion for JH7110 SoC platform.
Signed-off-by: Minda Chen <[email protected]>
Reviewed-by: Hal Feng <[email protected]>
---
.../jh7110-starfive-visionfive-2.dtsi | 64 ++++++++++++++
arch/riscv/boot/dts/starfive/jh7110.dtsi | 86 +++++++++++++++++++
2 files changed, 150 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
index de0f40a8be93..4dd61e2fec7d 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -15,6 +15,8 @@
i2c2 = &i2c2;
i2c5 = &i2c5;
i2c6 = &i2c6;
+ pcie0 = &pcie0;
+ pcie1 = &pcie1;
serial0 = &uart0;
};
@@ -208,6 +210,54 @@
};
};
+ pcie0_pins: pcie0-0 {
+ wake-pins {
+ pinmux = <GPIOMUX(32, GPOUT_LOW,
+ GPOEN_DISABLE,
+ GPI_NONE)>;
+ bias-pull-up;
+ drive-strength = <2>;
+ input-enable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+
+ clkreq-pins {
+ pinmux = <GPIOMUX(27, GPOUT_LOW,
+ GPOEN_DISABLE,
+ GPI_NONE)>;
+ bias-pull-down;
+ drive-strength = <2>;
+ input-enable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+ };
+
+ pcie1_pins: pcie1-0 {
+ wake-pins {
+ pinmux = <GPIOMUX(21, GPOUT_LOW,
+ GPOEN_DISABLE,
+ GPI_NONE)>;
+ bias-pull-up;
+ drive-strength = <2>;
+ input-enable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+
+ clkreq-pins {
+ pinmux = <GPIOMUX(29, GPOUT_LOW,
+ GPOEN_DISABLE,
+ GPI_NONE)>;
+ bias-pull-down;
+ drive-strength = <2>;
+ input-enable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+ };
+
uart0_pins: uart0-0 {
tx-pins {
pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX,
@@ -233,6 +283,20 @@
};
};
+&pcie0 {
+ pinctrl-names = "default";
+ perst-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&pcie0_pins>;
+ status = "okay";
+};
+
+&pcie1 {
+ pinctrl-names = "default";
+ perst-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&pcie1_pins>;
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 02354e642c44..7a5dc43cf63c 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -629,5 +629,91 @@
#reset-cells = <1>;
power-domains = <&pwrc JH7110_PD_VOUT>;
};
+
+ pcie0: pcie@940000000 {
+ compatible = "starfive,jh7110-pcie";
+ reg = <0x9 0x40000000 0x0 0x1000000>,
+ <0x0 0x2b000000 0x0 0x100000>;
+ reg-names = "cfg", "apb";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>,
+ <0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>;
+ interrupts = <56>;
+ interrupt-parent = <&plic>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc0 0x1>,
+ <0x0 0x0 0x0 0x2 &pcie_intc0 0x2>,
+ <0x0 0x0 0x0 0x3 &pcie_intc0 0x3>,
+ <0x0 0x0 0x0 0x4 &pcie_intc0 0x4>;
+ msi-controller;
+ device_type = "pci";
+ starfive,stg-syscon = <&stg_syscon>;
+ bus-range = <0x0 0xff>;
+ clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
+ <&stgcrg JH7110_STGCLK_PCIE0_TL>,
+ <&stgcrg JH7110_STGCLK_PCIE0_AXI_MST0>,
+ <&stgcrg JH7110_STGCLK_PCIE0_APB>;
+ clock-names = "noc", "tl", "axi_mst0", "apb";
+ resets = <&stgcrg JH7110_STGRST_PCIE0_AXI_MST0>,
+ <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV0>,
+ <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV>,
+ <&stgcrg JH7110_STGRST_PCIE0_BRG>,
+ <&stgcrg JH7110_STGRST_PCIE0_CORE>,
+ <&stgcrg JH7110_STGRST_PCIE0_APB>;
+ reset-names = "mst0", "slv0", "slv", "brg",
+ "core", "apb";
+ status = "disabled";
+
+ pcie_intc0: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ pcie1: pcie@9c0000000 {
+ compatible = "starfive,jh7110-pcie";
+ reg = <0x9 0xc0000000 0x0 0x1000000>,
+ <0x0 0x2c000000 0x0 0x100000>;
+ reg-names = "cfg", "apb";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x82000000 0x0 0x38000000 0x0 0x38000000 0x0 0x08000000>,
+ <0xc3000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>;
+ interrupts = <57>;
+ interrupt-parent = <&plic>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc1 0x1>,
+ <0x0 0x0 0x0 0x2 &pcie_intc1 0x2>,
+ <0x0 0x0 0x0 0x3 &pcie_intc1 0x3>,
+ <0x0 0x0 0x0 0x4 &pcie_intc1 0x4>;
+ msi-controller;
+ device_type = "pci";
+ starfive,stg-syscon = <&stg_syscon>;
+ bus-range = <0x0 0xff>;
+ clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
+ <&stgcrg JH7110_STGCLK_PCIE1_TL>,
+ <&stgcrg JH7110_STGCLK_PCIE1_AXI_MST0>,
+ <&stgcrg JH7110_STGCLK_PCIE1_APB>;
+ clock-names = "noc", "tl", "axi_mst0", "apb";
+ resets = <&stgcrg JH7110_STGRST_PCIE1_AXI_MST0>,
+ <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV0>,
+ <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV>,
+ <&stgcrg JH7110_STGRST_PCIE1_BRG>,
+ <&stgcrg JH7110_STGRST_PCIE1_CORE>,
+ <&stgcrg JH7110_STGRST_PCIE1_APB>;
+ reset-names = "mst0", "slv0", "slv", "brg",
+ "core", "apb";
+ status = "disabled";
+
+ pcie_intc1: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
};
};
--
2.17.1
On 2023/9/8 1:19, Rob Herring wrote:
> On Thu, Sep 7, 2023 at 4:11 AM Minda Chen <[email protected]> wrote:
>>
>> Add PCIe dts configuraion for JH7110 SoC platform.
>>
>> Signed-off-by: Minda Chen <[email protected]>
>> Reviewed-by: Hal Feng <[email protected]>
>> ---
>> .../jh7110-starfive-visionfive-2.dtsi | 64 ++++++++++++++
>> arch/riscv/boot/dts/starfive/jh7110.dtsi | 86 +++++++++++++++++++
>> 2 files changed, 150 insertions(+)
>>
>> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> index de0f40a8be93..4dd61e2fec7d 100644
>> --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> @@ -15,6 +15,8 @@
>> i2c2 = &i2c2;
>> i2c5 = &i2c5;
>> i2c6 = &i2c6;
>> + pcie0 = &pcie0;
>> + pcie1 = &pcie1;
>
> That's not a defined alias. We already have "linux,pci-domain" if you
> need to number PCI host bridges.
>
Okay, we will number PCI host bridges by "linux,pci-domain".
>> serial0 = &uart0;
>> };
>>
>> @@ -208,6 +210,54 @@
>> };
>> };
>>
>> + pcie0_pins: pcie0-0 {
>> + wake-pins {
>> + pinmux = <GPIOMUX(32, GPOUT_LOW,
>> + GPOEN_DISABLE,
>> + GPI_NONE)>;
>> + bias-pull-up;
>> + drive-strength = <2>;
>> + input-enable;
>> + input-schmitt-disable;
>> + slew-rate = <0>;
>> + };
>> +
>> + clkreq-pins {
>> + pinmux = <GPIOMUX(27, GPOUT_LOW,
>> + GPOEN_DISABLE,
>> + GPI_NONE)>;
>> + bias-pull-down;
>> + drive-strength = <2>;
>> + input-enable;
>> + input-schmitt-disable;
>> + slew-rate = <0>;
>> + };
>> + };
>> +
>> + pcie1_pins: pcie1-0 {
>> + wake-pins {
>> + pinmux = <GPIOMUX(21, GPOUT_LOW,
>> + GPOEN_DISABLE,
>> + GPI_NONE)>;
>> + bias-pull-up;
>> + drive-strength = <2>;
>> + input-enable;
>> + input-schmitt-disable;
>> + slew-rate = <0>;
>> + };
>> +
>> + clkreq-pins {
>> + pinmux = <GPIOMUX(29, GPOUT_LOW,
>> + GPOEN_DISABLE,
>> + GPI_NONE)>;
>> + bias-pull-down;
>> + drive-strength = <2>;
>> + input-enable;
>> + input-schmitt-disable;
>> + slew-rate = <0>;
>> + };
>> + };
>> +
>> uart0_pins: uart0-0 {
>> tx-pins {
>> pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX,
>> @@ -233,6 +283,20 @@
>> };
>> };
>>
>> +&pcie0 {
>> + pinctrl-names = "default";
>> + perst-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>;
>> + pinctrl-0 = <&pcie0_pins>;
>> + status = "okay";
>> +};
>> +
>> +&pcie1 {
>> + pinctrl-names = "default";
>> + perst-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>;
>> + pinctrl-0 = <&pcie1_pins>;
>> + status = "okay";
>> +};
>> +
>> &uart0 {
>> pinctrl-names = "default";
>> pinctrl-0 = <&uart0_pins>;
>> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> index 02354e642c44..7a5dc43cf63c 100644
>> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> @@ -629,5 +629,91 @@
>> #reset-cells = <1>;
>> power-domains = <&pwrc JH7110_PD_VOUT>;
>> };
>> +
>> + pcie0: pcie@940000000 {
>> + compatible = "starfive,jh7110-pcie";
>> + reg = <0x9 0x40000000 0x0 0x1000000>,
>> + <0x0 0x2b000000 0x0 0x100000>;
>> + reg-names = "cfg", "apb";
>> + #address-cells = <3>;
>> + #size-cells = <2>;
>> + #interrupt-cells = <1>;
>> + ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>,
>> + <0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>;
>> + interrupts = <56>;
>> + interrupt-parent = <&plic>;
>> + interrupt-map-mask = <0x0 0x0 0x0 0x7>;
>> + interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc0 0x1>,
>> + <0x0 0x0 0x0 0x2 &pcie_intc0 0x2>,
>> + <0x0 0x0 0x0 0x3 &pcie_intc0 0x3>,
>> + <0x0 0x0 0x0 0x4 &pcie_intc0 0x4>;
>> + msi-controller;
>> + device_type = "pci";
>> + starfive,stg-syscon = <&stg_syscon>;
>> + bus-range = <0x0 0xff>;
>> + clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
>> + <&stgcrg JH7110_STGCLK_PCIE0_TL>,
>> + <&stgcrg JH7110_STGCLK_PCIE0_AXI_MST0>,
>> + <&stgcrg JH7110_STGCLK_PCIE0_APB>;
>> + clock-names = "noc", "tl", "axi_mst0", "apb";
>> + resets = <&stgcrg JH7110_STGRST_PCIE0_AXI_MST0>,
>> + <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV0>,
>> + <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV>,
>> + <&stgcrg JH7110_STGRST_PCIE0_BRG>,
>> + <&stgcrg JH7110_STGRST_PCIE0_CORE>,
>> + <&stgcrg JH7110_STGRST_PCIE0_APB>;
>> + reset-names = "mst0", "slv0", "slv", "brg",
>> + "core", "apb";
>> + status = "disabled";
>> +
>> + pcie_intc0: interrupt-controller {
>> + #address-cells = <0>;
>> + #interrupt-cells = <1>;
>> + interrupt-controller;
>> + };
>> + };
>> +
>> + pcie1: pcie@9c0000000 {
>> + compatible = "starfive,jh7110-pcie";
>> + reg = <0x9 0xc0000000 0x0 0x1000000>,
>> + <0x0 0x2c000000 0x0 0x100000>;
>> + reg-names = "cfg", "apb";
>> + #address-cells = <3>;
>> + #size-cells = <2>;
>> + #interrupt-cells = <1>;
>> + ranges = <0x82000000 0x0 0x38000000 0x0 0x38000000 0x0 0x08000000>,
>> + <0xc3000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>;
>> + interrupts = <57>;
>> + interrupt-parent = <&plic>;
>> + interrupt-map-mask = <0x0 0x0 0x0 0x7>;
>> + interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc1 0x1>,
>> + <0x0 0x0 0x0 0x2 &pcie_intc1 0x2>,
>> + <0x0 0x0 0x0 0x3 &pcie_intc1 0x3>,
>> + <0x0 0x0 0x0 0x4 &pcie_intc1 0x4>;
>> + msi-controller;
>> + device_type = "pci";
>> + starfive,stg-syscon = <&stg_syscon>;
>> + bus-range = <0x0 0xff>;
>> + clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
>> + <&stgcrg JH7110_STGCLK_PCIE1_TL>,
>> + <&stgcrg JH7110_STGCLK_PCIE1_AXI_MST0>,
>> + <&stgcrg JH7110_STGCLK_PCIE1_APB>;
>> + clock-names = "noc", "tl", "axi_mst0", "apb";
>> + resets = <&stgcrg JH7110_STGRST_PCIE1_AXI_MST0>,
>> + <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV0>,
>> + <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV>,
>> + <&stgcrg JH7110_STGRST_PCIE1_BRG>,
>> + <&stgcrg JH7110_STGRST_PCIE1_CORE>,
>> + <&stgcrg JH7110_STGRST_PCIE1_APB>;
>> + reset-names = "mst0", "slv0", "slv", "brg",
>> + "core", "apb";
>> + status = "disabled";
>> +
>> + pcie_intc1: interrupt-controller {
>> + #address-cells = <0>;
>> + #interrupt-cells = <1>;
>> + interrupt-controller;
>> + };
>> + };
>> };
>> };
>> --
>> 2.17.1
>>