Hi all,
This is v5 of the patch set which adds support of Dynamic Memory Controller
for Exynos5422 SoC.
The driver supports Dynamic Voltage and Frequency Scalling
for the DMC and DRAM. It also provides needed timings for different
speed operations of the DRAM memory.
changes:
v5:
- removed unneeded wrapper functions i.e. for regulator_set_voltage
- removed unused defines
- removed direct access to clock register base and used CCF for
pause and timing set usage
- switched to OPP coming from DT according to Chanowoo's comments
- switched to timings coming from DT, added parsing function
- extended dt-binding with description of OPPs and timings
- according to Rob Herring comment, moved dt-binding file before driver code
in the patch set.
- re-based on top of v5.0
v4:
- removed unneeded DPLL and G3D clocks IDs
- changed names of parent clocks for mout_mx_mspll_ccore_phy_p
and added one more parent: mout_sclk_epll
- removed 933Mhz and 138MHz from the BPLL ratio table
v3:
- in DTS align to proper indent the clocks and clock-names entries
v2:
- changed file name exynos5-dmc.c -> exynos5422-dmc.c
and related entries in other files
- changed dt-binding file name
- changed config entry to CONFIG_ARM_EXYNOS5422_DMC_DEVFREQ
- removed sysfs and print info messages (print only one line)
- removed function exynos5_read_chip_info and compact code
- changed dt-binding patch and move it up in the patch set
- new entries in MAINTAINERS are added with the driver c code
- clean-up in DTS file: renamed nodes to 'ppmu' and 'memory-controller',
entries moved to suggested location (before nocp nodes or after),
moved according to alfabetical order, compacted clocks names with right indent.
Regards,
Lukasz Luba
Lukasz Luba (8):
clk: samsung: add needed IDs for DMC clocks in Exynos5420
clk: samsung: add new clocks for DMC for Exynos5422 SoC
clk: samsung: add BPLL rate table for Exynos 5422 SoC
dt-bindings: devfreq: add Exynos5422 DMC device description
drivers: devfreq: add DMC driver for Exynos5422
DT: arm: exynos: add DMC device for exynos5422
drivers: devfreq: events: add Exynos PPMU new events
ARM: exynos_defconfig: enable DMC driver
.../devicetree/bindings/devfreq/exynos5422-dmc.txt | 177 +++
MAINTAINERS | 8 +
arch/arm/boot/dts/exynos5420.dtsi | 83 ++
arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 87 ++
arch/arm/configs/exynos_defconfig | 1 +
drivers/clk/samsung/clk-exynos5420.c | 67 +-
drivers/devfreq/Kconfig | 13 +
drivers/devfreq/Makefile | 1 +
drivers/devfreq/event/exynos-ppmu.c | 6 +
drivers/devfreq/exynos5422-dmc.c | 1154 ++++++++++++++++++++
include/dt-bindings/clock/exynos5420.h | 18 +-
11 files changed, 1609 insertions(+), 6 deletions(-)
create mode 100644 Documentation/devicetree/bindings/devfreq/exynos5422-dmc.txt
create mode 100644 drivers/devfreq/exynos5422-dmc.c
--
2.7.4
Enable driver for Dynamic Memory Controller dynamic frequency and
voltage scaling in Exynos5422 SoCs.
Signed-off-by: Lukasz Luba <[email protected]>
---
arch/arm/configs/exynos_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig
index d635edf..b5dddcc 100644
--- a/arch/arm/configs/exynos_defconfig
+++ b/arch/arm/configs/exynos_defconfig
@@ -291,6 +291,7 @@ CONFIG_DEVFREQ_GOV_PERFORMANCE=y
CONFIG_DEVFREQ_GOV_POWERSAVE=y
CONFIG_DEVFREQ_GOV_USERSPACE=y
CONFIG_ARM_EXYNOS_BUS_DEVFREQ=y
+CONFIG_ARM_EXYNOS5422_DMC_DEVFREQ=y
CONFIG_DEVFREQ_EVENT_EXYNOS_NOCP=y
CONFIG_EXYNOS_IOMMU=y
CONFIG_EXTCON=y
--
2.7.4
Define new IDs for clocks used by Dynamic Memory Controller in
Exynos5422 SoC.
Signed-off-by: Lukasz Luba <[email protected]>
---
include/dt-bindings/clock/exynos5420.h | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h
index 355f469..abb1842 100644
--- a/include/dt-bindings/clock/exynos5420.h
+++ b/include/dt-bindings/clock/exynos5420.h
@@ -60,6 +60,7 @@
#define CLK_MAU_EPLL 159
#define CLK_SCLK_HSIC_12M 160
#define CLK_SCLK_MPHY_IXTAL24 161
+#define CLK_SCLK_BPLL 162
/* gate clocks */
#define CLK_UART0 257
@@ -195,6 +196,18 @@
#define CLK_ACLK432_CAM 518
#define CLK_ACLK_FL1550_CAM 519
#define CLK_ACLK550_CAM 520
+#define CLK_CLKM_PHY0 521
+#define CLK_CLKM_PHY1 522
+#define CLK_ACLK_PPMU_DREX0_0 523
+#define CLK_ACLK_PPMU_DREX0_1 524
+#define CLK_ACLK_PPMU_DREX1_0 525
+#define CLK_ACLK_PPMU_DREX1_1 526
+#define CLK_PCLK_PPMU_DREX0_0 527
+#define CLK_PCLK_PPMU_DREX0_1 528
+#define CLK_PCLK_PPMU_DREX1_0 529
+#define CLK_PCLK_PPMU_DREX1_1 530
+#define CLK_CDREX_PAUSE 531
+#define CLK_CDREX_TIMING_SET 532
/* mux clocks */
#define CLK_MOUT_HDMI 640
@@ -217,6 +230,8 @@
#define CLK_MOUT_EPLL 657
#define CLK_MOUT_MAU_EPLL 658
#define CLK_MOUT_USER_MAU_EPLL 659
+#define CLK_MOUT_SCLK_SPLL 660
+#define CLK_MOUT_MX_MSPLL_CCORE_PHY 661
/* divider clocks */
#define CLK_DOUT_PIXEL 768
@@ -248,8 +263,9 @@
#define CLK_DOUT_CCLK_DREX0 794
#define CLK_DOUT_CLK2X_PHY0 795
#define CLK_DOUT_PCLK_CORE_MEM 796
+#define CLK_FF_DOUT_SPLL2 797
/* must be greater than maximal clock id */
-#define CLK_NR_CLKS 797
+#define CLK_NR_CLKS 798
#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */
--
2.7.4
Define new performance events supported by Exynos5422 SoC counters.
The counters are built-in in Dynamic Memory Controller and provide
information regarding memory utilization.
Signed-off-by: Lukasz Luba <[email protected]>
---
drivers/devfreq/event/exynos-ppmu.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/devfreq/event/exynos-ppmu.c b/drivers/devfreq/event/exynos-ppmu.c
index c61de0b..67d6674 100644
--- a/drivers/devfreq/event/exynos-ppmu.c
+++ b/drivers/devfreq/event/exynos-ppmu.c
@@ -89,6 +89,12 @@ static struct __exynos_ppmu_events {
PPMU_EVENT(d1-cpu),
PPMU_EVENT(d1-general),
PPMU_EVENT(d1-rt),
+
+ /* For Exynos5422 SoC */
+ PPMU_EVENT(dmc0_0),
+ PPMU_EVENT(dmc0_1),
+ PPMU_EVENT(dmc1_0),
+ PPMU_EVENT(dmc1_1),
};
static int exynos_ppmu_find_ppmu_id(struct devfreq_event_dev *edev)
--
2.7.4
Add new table rate for BPLL for Exynos5422 SoC supporting Dynamic Memory
Controller frequencies for driver's DRAM timings.
Signed-off-by: Lukasz Luba <[email protected]>
---
drivers/clk/samsung/clk-exynos5420.c | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 6da5875..6f5db70 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -1331,6 +1331,17 @@ static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __ini
PLL_35XX_RATE(24 * MHZ, 200000000, 200, 3, 3),
};
+static const struct samsung_pll_rate_table exynos5422_bpll_rate_table[] = {
+ PLL_35XX_RATE(24 * MHZ, 825000000, 275, 4, 1),
+ PLL_35XX_RATE(24 * MHZ, 728000000, 182, 3, 1),
+ PLL_35XX_RATE(24 * MHZ, 633000000, 211, 4, 1),
+ PLL_35XX_RATE(24 * MHZ, 543000000, 181, 2, 2),
+ PLL_35XX_RATE(24 * MHZ, 413000000, 413, 6, 2),
+ PLL_35XX_RATE(24 * MHZ, 275000000, 275, 3, 3),
+ PLL_35XX_RATE(24 * MHZ, 206000000, 206, 3, 3),
+ PLL_35XX_RATE(24 * MHZ, 165000000, 110, 2, 3),
+};
+
static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = {
PLL_36XX_RATE(24 * MHZ, 600000000U, 100, 2, 1, 0),
PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0),
@@ -1473,7 +1484,7 @@ static void __init exynos5x_clk_init(struct device_node *np,
exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl;
exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl;
exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
- exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
+ exynos5x_plls[bpll].rate_table = exynos5422_bpll_rate_table;
}
samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls),
--
2.7.4
The patch adds description for DT binding for a new Exynos5422 Dynamic
Memory Controller device.
Signed-off-by: Lukasz Luba <[email protected]>
---
.../devicetree/bindings/devfreq/exynos5422-dmc.txt | 177 +++++++++++++++++++++
1 file changed, 177 insertions(+)
create mode 100644 Documentation/devicetree/bindings/devfreq/exynos5422-dmc.txt
diff --git a/Documentation/devicetree/bindings/devfreq/exynos5422-dmc.txt b/Documentation/devicetree/bindings/devfreq/exynos5422-dmc.txt
new file mode 100644
index 0000000..0e73e98
--- /dev/null
+++ b/Documentation/devicetree/bindings/devfreq/exynos5422-dmc.txt
@@ -0,0 +1,177 @@
+* Exynos5422 frequency and voltage scaling for Dynamic Memory Controller device
+
+The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the DRAM
+memory chips are connected. The driver is to monitor the controller in runtime
+and switch frequency and voltage. To monitor the usage of the controller in
+runtime, the driver uses the PPMU (Platform Performance Monitoring Unit), which
+is able to measure the current load of the memory.
+When 'userspace' governor is used for the driver, an application is able to
+switch the DMC frequency.
+
+Required properties for DMC device for Exynos5422:
+- compatible: Should be "samsung,exynos5422-bus".
+- clock-names : the name of clock used by the bus, "bus".
+- clocks : phandles for clock specified in "clock-names" property.
+- devfreq-events : phandles for PPMU devices connected to this DMC.
+
+The example definition of a DMC and PPMU devices declared in DT is shown below:
+
+ ppmu_dmc0_0: ppmu@10d00000 {
+ compatible = "samsung,exynos-ppmu";
+ reg = <0x10d00000 0x2000>;
+ clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;
+ clock-names = "ppmu";
+ status = "okay";
+ events {
+ ppmu_event_dmc0_0: ppmu-event3-dmc0_0 {
+ event-name = "ppmu-event3-dmc0_0";
+ };
+ };
+ };
+
+
+ ppmu_dmc0_1: ppmu@10d10000 {
+ compatible = "samsung,exynos-ppmu";
+ reg = <0x10d10000 0x2000>;
+ clocks = <&clock CLK_PCLK_PPMU_DREX0_1>;
+ clock-names = "ppmu";
+ status = "okay";
+ events {
+ ppmu_event_dmc0_1: ppmu-event3-dmc0_1 {
+ event-name = "ppmu-event3-dmc0_1";
+ };
+ };
+ };
+
+ ppmu_dmc1_0: ppmu@10d10000 {
+ compatible = "samsung,exynos-ppmu";
+ reg = <0x10d60000 0x2000>;
+ clocks = <&clock CLK_PCLK_PPMU_DREX1_0>;
+ clock-names = "ppmu";
+ status = "okay";
+ events {
+ ppmu_event_dmc1_0: ppmu-event3-dmc1_0 {
+ event-name = "ppmu-event3-dmc1_0";
+ };
+ };
+ };
+
+ ppmu_dmc1_1: ppmu@10d70000 {
+ compatible = "samsung,exynos-ppmu";
+ reg = <0x10d70000 0x2000>;
+ clocks = <&clock CLK_PCLK_PPMU_DREX1_1>;
+ clock-names = "ppmu";
+ status = "okay";
+ events {
+ ppmu_event_dmc1_1: ppmu-event3-dmc1_1 {
+ event-name = "ppmu-event3-dmc1_1";
+ };
+ };
+ };
+
+ dmc: memory-controller@10c20000 {
+ compatible = "samsung,exynos5422-dmc";
+ reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>,
+ <0x10000000 0x1000>;
+ clocks = <&clock CLK_FOUT_SPLL>,
+ <&clock CLK_MOUT_SCLK_SPLL>,
+ <&clock CLK_FF_DOUT_SPLL2>,
+ <&clock CLK_FOUT_BPLL>,
+ <&clock CLK_MOUT_BPLL>,
+ <&clock CLK_SCLK_BPLL>,
+ <&clock CLK_MOUT_MX_MSPLL_CCORE>,
+ <&clock CLK_MOUT_MX_MSPLL_CCORE_PHY>,
+ <&clock CLK_MOUT_MCLK_CDREX>,
+ <&clock CLK_DOUT_CLK2X_PHY0>,
+ <&clock CLK_CLKM_PHY0>,
+ <&clock CLK_CLKM_PHY1>,
+ <&clock CLK_CDREX_PAUSE>,
+ <&clock CLK_CDREX_TIMING_SET>;
+ clock-names = "fout_spll",
+ "mout_sclk_spll",
+ "ff_dout_spll2",
+ "fout_bpll",
+ "mout_bpll",
+ "sclk_bpll",
+ "mout_mx_mspll_ccore",
+ "mout_mx_mspll_ccore_phy",
+ "mout_mclk_cdrex",
+ "dout_clk2x_phy0",
+ "clkm_phy0",
+ "clkm_phy1",
+ "clk_cdrex_pause",
+ "clk_cdrex_timing_set";
+ status = "okay";
+ operating-points-v2 = <&dmc_opp_table>;
+ devfreq-events = <&ppmu_dmc0_0>, <&ppmu_dmc0_1>,
+ <&ppmu_dmc1_0>, <&ppmu_dmc1_1>;
+ };
+
+The needed timings of DRAM memory are stored in dedicated nodes.
+There are two nodes with regular timings and for bypass mode.
+
+ dmc_bypass_mode: bypass_mode {
+ compatible = "samsung,dmc-bypass-mode";
+
+ freq-hz = <400000000>;
+ volt-uv = <887500>;
+ dram-timing-row = <0x365a9713>;
+ dram-timing-data = <0x4740085e>;
+ dram-timing-power = <0x543a0446>;
+ };
+
+ dram_timing: timing {
+ compatible = "samsung,dram-timing";
+
+ dram-timing-names = "165MHz", "206MHz", "275MHz", "413MHz",
+ "543MHz", "633MHz", "728MHz", "825MHz";
+ dram-timing-row = <0x11223185>, <0x112331C6>, <0x12244287>,
+ <0x1B35538A>, <0x244764CD>, <0x2A48758F>,
+ <0x30598651>, <0x365A9713>;
+ dram-timing-data = <0x2720085E>, <0x2720085E>, <0x2720085E>,
+ <0x2720085E>, <0x3730085E>, <0x3730085E>,
+ <0x3730085E>, <0x4740085E>;
+ dram-timing-power = <0x140C0225>, <0x180F0225>, <0x1C140225>,
+ <0x2C1D0225>, <0x38270335>, <0x402D0335>,
+ <0x4C330336>, <0x543A0446>;
+ };
+
+The frequencies supported by the DMC are stored in OPP table v2.
+
+ dmc_opp_table: opp_table2 {
+ compatible = "operating-points-v2";
+
+ opp00 {
+ opp-hz = /bits/ 64 <165000000>;
+ opp-microvolt = <875000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <206000000>;
+ opp-microvolt = <875000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <275000000>;
+ opp-microvolt = <875000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <413000000>;
+ opp-microvolt = <887500>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <543000000>;
+ opp-microvolt = <937500>;
+ };
+ opp05 {
+ opp-hz = /bits/ 64 <633000000>;
+ opp-microvolt = <1012500>;
+ };
+ opp06 {
+ opp-hz = /bits/ 64 <728000000>;
+ opp-microvolt = <1037500>;
+ };
+ opp07 {
+ opp-hz = /bits/ 64 <825000000>;
+ opp-microvolt = <1050000>;
+ };
+ };
+
--
2.7.4
Add description of Dynamic Memory Controller and PPMU counters.
They are used by exynos5422-dmc driver.
Signed-off-by: Lukasz Luba <[email protected]>
---
arch/arm/boot/dts/exynos5420.dtsi | 83 +++++++++++++++++++++++++
arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 87 +++++++++++++++++++++++++++
2 files changed, 170 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index aaff158..fc00fda 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -235,6 +235,41 @@
status = "disabled";
};
+ dmc: memory-controller@10c20000 {
+ compatible = "samsung,exynos5422-dmc";
+ reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>,
+ <0x10000000 0x1000>;
+ clocks = <&clock CLK_FOUT_SPLL>,
+ <&clock CLK_MOUT_SCLK_SPLL>,
+ <&clock CLK_FF_DOUT_SPLL2>,
+ <&clock CLK_FOUT_BPLL>,
+ <&clock CLK_MOUT_BPLL>,
+ <&clock CLK_SCLK_BPLL>,
+ <&clock CLK_MOUT_MX_MSPLL_CCORE>,
+ <&clock CLK_MOUT_MX_MSPLL_CCORE_PHY>,
+ <&clock CLK_MOUT_MCLK_CDREX>,
+ <&clock CLK_DOUT_CLK2X_PHY0>,
+ <&clock CLK_CLKM_PHY0>,
+ <&clock CLK_CLKM_PHY1>,
+ <&clock CLK_CDREX_PAUSE>,
+ <&clock CLK_CDREX_TIMING_SET>;
+ clock-names = "fout_spll",
+ "mout_sclk_spll",
+ "ff_dout_spll2",
+ "fout_bpll",
+ "mout_bpll",
+ "sclk_bpll",
+ "mout_mx_mspll_ccore",
+ "mout_mx_mspll_ccore_phy",
+ "mout_mclk_cdrex",
+ "dout_clk2x_phy0",
+ "clkm_phy0",
+ "clkm_phy1",
+ "clk_cdrex_pause",
+ "clk_cdrex_timing_set";
+ status = "disabled";
+ };
+
nocp_mem0_0: nocp@10ca1000 {
compatible = "samsung,exynos5420-nocp";
reg = <0x10CA1000 0x200>;
@@ -271,6 +306,54 @@
status = "disabled";
};
+ ppmu_dmc0_0: ppmu@10d00000 {
+ compatible = "samsung,exynos-ppmu";
+ reg = <0x10d00000 0x2000>;
+ clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;
+ clock-names = "ppmu";
+ events {
+ ppmu_event_dmc0_0: ppmu-event3-dmc0_0 {
+ event-name = "ppmu-event3-dmc0_0";
+ };
+ };
+ };
+
+ ppmu_dmc0_1: ppmu@10d10000 {
+ compatible = "samsung,exynos-ppmu";
+ reg = <0x10d10000 0x2000>;
+ clocks = <&clock CLK_PCLK_PPMU_DREX0_1>;
+ clock-names = "ppmu";
+ events {
+ ppmu_event_dmc0_1: ppmu-event3-dmc0_1 {
+ event-name = "ppmu-event3-dmc0_1";
+ };
+ };
+ };
+
+ ppmu_dmc1_0: ppmu@10d10000 {
+ compatible = "samsung,exynos-ppmu";
+ reg = <0x10d60000 0x2000>;
+ clocks = <&clock CLK_PCLK_PPMU_DREX1_0>;
+ clock-names = "ppmu";
+ events {
+ ppmu_event_dmc1_0: ppmu-event3-dmc1_0 {
+ event-name = "ppmu-event3-dmc1_0";
+ };
+ };
+ };
+
+ ppmu_dmc1_1: ppmu@10d70000 {
+ compatible = "samsung,exynos-ppmu";
+ reg = <0x10d70000 0x2000>;
+ clocks = <&clock CLK_PCLK_PPMU_DREX1_1>;
+ clock-names = "ppmu";
+ events {
+ ppmu_event_dmc1_1: ppmu-event3-dmc1_1 {
+ event-name = "ppmu-event3-dmc1_1";
+ };
+ };
+ };
+
gsc_pd: power-domain@10044000 {
compatible = "samsung,exynos4210-pd";
reg = <0x10044000 0x20>;
diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index bf09eab..6b28fb3 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -34,6 +34,69 @@
clock-frequency = <24000000>;
};
};
+
+ dmc_opp_table: opp_table2 {
+ compatible = "operating-points-v2";
+
+ opp00 {
+ opp-hz = /bits/ 64 <165000000>;
+ opp-microvolt = <875000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <206000000>;
+ opp-microvolt = <875000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <275000000>;
+ opp-microvolt = <875000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <413000000>;
+ opp-microvolt = <887500>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <543000000>;
+ opp-microvolt = <937500>;
+ };
+ opp05 {
+ opp-hz = /bits/ 64 <633000000>;
+ opp-microvolt = <1012500>;
+ };
+ opp06 {
+ opp-hz = /bits/ 64 <728000000>;
+ opp-microvolt = <1037500>;
+ };
+ opp07 {
+ opp-hz = /bits/ 64 <825000000>;
+ opp-microvolt = <1050000>;
+ };
+ };
+
+ dmc_bypass_mode: bypass_mode {
+ compatible = "samsung,dmc-bypass-mode";
+
+ freq-hz = <400000000>;
+ volt-uv = <887500>;
+ dram-timing-row = <0x365a9713>;
+ dram-timing-data = <0x4740085e>;
+ dram-timing-power = <0x543a0446>;
+ };
+
+ dram_timing: timing {
+ compatible = "samsung,dram-timing";
+
+ dram-timing-names = "165MHz", "206MHz", "275MHz", "413MHz",
+ "543MHz", "633MHz", "728MHz", "825MHz";
+ dram-timing-row = <0x11223185>, <0x112331C6>, <0x12244287>,
+ <0x1B35538A>, <0x244764CD>, <0x2A48758F>,
+ <0x30598651>, <0x365A9713>;
+ dram-timing-data = <0x2720085E>, <0x2720085E>, <0x2720085E>,
+ <0x2720085E>, <0x3730085E>, <0x3730085E>,
+ <0x3730085E>, <0x4740085E>;
+ dram-timing-power = <0x140C0225>, <0x180F0225>, <0x1C140225>,
+ <0x2C1D0225>, <0x38270335>, <0x402D0335>,
+ <0x4C330336>, <0x543A0446>;
+ };
};
&bus_wcore {
@@ -127,6 +190,14 @@
cpu-supply = <&buck2_reg>;
};
+&dmc {
+ devfreq-events = <&ppmu_dmc0_0>, <&ppmu_dmc0_1>,
+ <&ppmu_dmc1_0>, <&ppmu_dmc1_1>;
+
+ operating-points-v2 = <&dmc_opp_table>;
+ status = "okay";
+};
+
&hsi2c_4 {
status = "okay";
@@ -535,6 +606,22 @@
};
};
+&ppmu_dmc0_0 {
+ status = "okay";
+};
+
+&ppmu_dmc0_1 {
+ status = "okay";
+};
+
+&ppmu_dmc1_0 {
+ status = "okay";
+};
+
+&ppmu_dmc1_1 {
+ status = "okay";
+};
+
&tmu_cpu0 {
vtmu-supply = <&ldo7_reg>;
};
--
2.7.4
This patch adds driver for Exynos5422 Dynamic Memory Controller.
The driver provides support for dynamic frequency and voltage scaling for
DMC and DRAM. It supports changing timings of DRAM running with different
frequency.
The patch also contains needed MAINTAINERS file update.
Signed-off-by: Lukasz Luba <[email protected]>
---
MAINTAINERS | 8 +
drivers/devfreq/Kconfig | 13 +
drivers/devfreq/Makefile | 1 +
drivers/devfreq/exynos5422-dmc.c | 1154 ++++++++++++++++++++++++++++++++++++++
4 files changed, 1176 insertions(+)
create mode 100644 drivers/devfreq/exynos5422-dmc.c
diff --git a/MAINTAINERS b/MAINTAINERS
index dce5c09..e20172b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3323,6 +3323,14 @@ S: Maintained
F: drivers/devfreq/exynos-bus.c
F: Documentation/devicetree/bindings/devfreq/exynos-bus.txt
+DMC FREQUENCY DRIVER FOR SAMSUNG EXYNOS5422
+M: Lukasz Luba <[email protected]>
+L: [email protected]
+L: [email protected]
+S: Maintained
+F: drivers/devfreq/exynos5422-dmc.c
+F: Documentation/devicetree/bindings/devfreq/exynos5422-dmc.txt
+
BUSLOGIC SCSI DRIVER
M: Khalid Aziz <[email protected]>
L: [email protected]
diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
index 6a172d3..a476477 100644
--- a/drivers/devfreq/Kconfig
+++ b/drivers/devfreq/Kconfig
@@ -113,6 +113,19 @@ config ARM_RK3399_DMC_DEVFREQ
It sets the frequency for the memory controller and reads the usage counts
from hardware.
+config ARM_EXYNOS5422_DMC_DEVFREQ
+ tristate "ARM EXYNOS5422 DMC DEVFREQ Driver"
+ depends on ARCH_EXYNOS || COMPILE_TEST
+ select DEVFREQ_GOV_SIMPLE_ONDEMAND
+ select DEVFREQ_GOV_USERSPACE
+ select PM_DEVFREQ_EVENT
+ select PM_OPP
+ help
+ This adds DEVFREQ driver for Exynos5422 DMC (Dynamic Memory Controller).
+ The driver provides support for Dynamic Voltage and Frequency Scaling in
+ DMC and DRAM. It also supports changing timings of DRAM running with
+ different frequency.
+
source "drivers/devfreq/event/Kconfig"
endif # PM_DEVFREQ
diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile
index 32b8d4d..e3620ff 100644
--- a/drivers/devfreq/Makefile
+++ b/drivers/devfreq/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_DEVFREQ_GOV_PASSIVE) += governor_passive.o
# DEVFREQ Drivers
obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ) += exynos-bus.o
+obj-$(CONFIG_ARM_EXYNOS5422_DMC_DEVFREQ) += exynos5422-dmc.o
obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o
obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra-devfreq.o
diff --git a/drivers/devfreq/exynos5422-dmc.c b/drivers/devfreq/exynos5422-dmc.c
new file mode 100644
index 0000000..0505a99
--- /dev/null
+++ b/drivers/devfreq/exynos5422-dmc.c
@@ -0,0 +1,1154 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 Samsung Electronics Co., Ltd.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/devfreq.h>
+#include <linux/devfreq-event.h>
+#include <linux/device.h>
+#include <linux/export.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/pm_opp.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/slab.h>
+
+#define EXYNOS5_DREXI_TIMINGAREF (0x0030)
+#define EXYNOS5_DREXI_TIMINGROW0 (0x0034)
+#define EXYNOS5_DREXI_TIMINGDATA0 (0x0038)
+#define EXYNOS5_DREXI_TIMINGPOWER0 (0x003C)
+#define EXYNOS5_DREXI_TIMINGROW1 (0x00E4)
+#define EXYNOS5_DREXI_TIMINGDATA1 (0x00E8)
+#define EXYNOS5_DREXI_TIMINGPOWER1 (0x00EC)
+
+#define EXYNOS5_AREF_NORMAL (0x2e)
+
+#define IS_MEM_2GB(val) \
+ ( \
+ (((val) & 0xf0) & 0x20) ? 1 : \
+ (((val) & 0xf0) & 0x30) ? 1 : 0 \
+ )
+
+#define EXYNOS5_POP_OPTIONS(val) (((val >> 4) & 0x3UL) << 4)
+#define EXYNOS5_DDR_TYPE(val) (((val >> 14) & 0x1UL))
+
+#define EXYNOS5_CHIP_PROD_ID (0)
+#define EXYNOS5_CHIP_PKG_ID (4)
+
+#define PPMU_PMCNT_CONST_RATIO_MUL 15
+#define PPMU_PMCNT_CONST_RATIO_DIV 10
+
+/**
+ * enum dmc_slot_id - An enum with slots in DMC
+ */
+enum dmc_slot_id {
+ DMC0_0,
+ DMC0_1,
+ DMC1_0,
+ DMC1_1,
+ DMC_SLOTS_END
+};
+
+/**
+ * struct dmc_slot_info - Describes DMC's slot
+ *
+ * The structure holds DMC's slot name which is part of the device name
+ * provided in DT. Each slot has particular share of the DMC bandwidth.
+ * To abstract the model performance and values in performance counters,
+ * fields 'ratio_mul' and 'ratio_div' are used in calculation algorithm
+ * for each slot. Please check the corresponding function with the algorithm,
+ * to see how these variables are used.
+ */
+struct dmc_slot_info {
+ char *name;
+ int id;
+ int ratio_mul;
+ int ratio_div;
+};
+
+/**
+ * struct dmc_opp_table - Operating level desciption
+ *
+ * Covers frequency and voltage settings of the DMC operating mode.
+ */
+struct dmc_opp_table {
+ u32 freq_hz;
+ u32 volt_uv;
+};
+
+/**
+ * struct exynos5_dmc - main structure describing DMC device
+ *
+ * The main structure for the Dynamic Memory Controller which covers clocks,
+ * memory regions, HW information, parameters and current operating mode.
+ */
+struct exynos5_dmc {
+ struct device *dev;
+ struct devfreq *df;
+ struct devfreq_simple_ondemand_data gov_data;
+ void __iomem *base_drexi0;
+ void __iomem *base_drexi1;
+ void __iomem *chip_id;
+ struct mutex lock;
+ unsigned long curr_rate;
+ unsigned long curr_volt;
+ struct dmc_opp_table *opp;
+ struct dmc_opp_table opp_bypass;
+ int opp_count;
+ u32 *timing_row;
+ u32 *timing_data;
+ u32 *timing_power;
+ u32 bypass_timing_row;
+ u32 bypass_timing_data;
+ u32 bypass_timing_power;
+ unsigned int prod_rev;
+ unsigned int pkg_rev;
+ unsigned int mem_info;
+ struct regulator *vdd_mif;
+ struct clk *fout_spll;
+ struct clk *fout_bpll;
+ struct clk *mout_spll;
+ struct clk *mout_bpll;
+ struct clk *mout_mclk_cdrex;
+ struct clk *dout_clk2x_phy0;
+ struct clk *mout_mx_mspll_ccore;
+ struct clk *mx_mspll_ccore_phy;
+ struct clk *mout_mx_mspll_ccore_phy;
+ struct clk *cdrex_pause;
+ struct clk *timing_set;
+ struct devfreq_event_dev **counter;
+ int num_counters;
+ bool counters_enabled;
+};
+
+/**
+ * exynos5_counters_fname() - Macro generating function for event devices
+ * @f: function name suffix
+ *
+ * Macro which generates needed function for manipulation of event devices.
+ * It aims to avoid code duplication relaying on similar prefix and function
+ * parameters in the devfreq event device framework functions.
+ */
+#define exynos5_counters_fname(f) \
+static int exynos5_counters_##f(struct exynos5_dmc *dmc) \
+{ \
+ int i, ret; \
+ \
+ for (i = 0; i < dmc->num_counters; i++) { \
+ if (!dmc->counter[i]) \
+ continue; \
+ ret = devfreq_event_##f(dmc->counter[i]); \
+ if (ret < 0) \
+ return ret; \
+ } \
+ return 0; \
+}
+exynos5_counters_fname(set_event);
+exynos5_counters_fname(enable_edev);
+exynos5_counters_fname(disable_edev);
+
+/**
+ * dmc_slot - An array which holds DMC's slots information
+ *
+ * The array is used in algorithm calculating slots performance and usage
+ * based on performance counters' values. The values i.e. 15/10=1.5 correspond
+ * to slot share in the DMC channel, which has 2.0 abstract width.
+ */
+static const struct dmc_slot_info dmc_slot[] = {
+ {"dmc0_0", DMC0_0, 15, 10},
+ {"dmc0_1", DMC0_1, 5, 10},
+ {"dmc1_0", DMC1_0, 10, 10},
+ {"dmc1_1", DMC1_0, 10, 10},
+};
+
+/**
+ * find_target_freq_id() - Finds requested frequency in local DMC configuration
+ * @dmc: device for which the information is checked
+ * @target_rate: requested frequency in KHz
+ *
+ * Seeks in the local DMC driver structure for the requested frequency value
+ * and returns index or error value.
+ */
+static int find_target_freq_idx(struct exynos5_dmc *dmc,
+ unsigned long target_rate)
+{
+ int i;
+
+ for (i = dmc->opp_count - 1; i >= 0; i--)
+ if (dmc->opp[i].freq_hz <= target_rate)
+ return i;
+
+ return -EINVAL;
+}
+
+/**
+ * exynos5_dmc_chip_revision_settings() - Chooses proper DMC's configuration
+ * @dmc: device for which is going to be checked and configured
+ *
+ * Function checks the HW product information in order to choose proper
+ * configuration for DMC frequency, voltage and DRAM timings.
+ */
+static int exynos5_dmc_chip_revision_settings(struct exynos5_dmc *dmc)
+{
+ unsigned int val;
+
+ val = readl(dmc->chip_id + EXYNOS5_CHIP_PROD_ID);
+ dmc->prod_rev = val;
+
+ val = readl(dmc->chip_id + EXYNOS5_CHIP_PKG_ID);
+ dmc->pkg_rev = val;
+
+ dmc->mem_info = EXYNOS5_POP_OPTIONS(val);
+ dmc->mem_info |= EXYNOS5_DDR_TYPE(val);
+
+ if (!IS_MEM_2GB(dmc->mem_info)) {
+ dev_warn(dmc->dev, "DRAM memory type not supported\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+/**
+ * exynos5_init_freq_table() - Initialized PM OPP framework
+ * @dev: devfreq device for which the OPP table is going to be
+ * initialized
+ * @dmc: DMC device for which the frequencies are used for OPP init
+ * @profile: devfreq device's profile
+ *
+ * Populate the devfreq device's OPP table based on current frequency, voltage.
+ */
+static int exynos5_init_freq_table(struct device *dev, struct exynos5_dmc *dmc,
+ struct devfreq_dev_profile *profile)
+{
+ int i, ret;
+ int idx;
+ unsigned long freq;
+
+ ret = dev_pm_opp_of_add_table(dev);
+ if (ret < 0) {
+ dev_err(dev, "Failed to get OPP table\n");
+ return ret;
+ }
+
+ dmc->opp_count = dev_pm_opp_get_opp_count(dev);
+
+ dmc->opp = devm_kmalloc_array(dmc->dev, dmc->opp_count,
+ sizeof(struct dmc_opp_table), GFP_KERNEL);
+ if (!dmc->opp)
+ goto err_opp;
+
+ idx = dmc->opp_count - 1;
+ for (i = 0, freq = ULONG_MAX; i < dmc->opp_count; i++, freq--) {
+ struct dev_pm_opp *opp;
+
+ opp = dev_pm_opp_find_freq_floor(dev, &freq);
+ if (IS_ERR(opp))
+ goto err_free_tables;
+
+ dmc->opp[idx - i].freq_hz = freq;
+ dmc->opp[idx - i].volt_uv = dev_pm_opp_get_voltage(opp);
+
+ dev_pm_opp_put(opp);
+ }
+
+ return 0;
+
+err_free_tables:
+ kfree(dmc->opp);
+err_opp:
+ dev_pm_opp_of_remove_table(dev);
+
+ return -EINVAL;
+}
+
+/**
+ * exynos5_set_bypass_dram_timings() - Low-level changes of the DRAM timings
+ * @dmc: device for which the new settings is going to be applied
+ * @param: DRAM parameters which passes timing data
+ *
+ * Low-level function for changing timings for DRAM memory clocking from
+ * 'bypass' clock source (fixed frequency @400MHz).
+ * It uses timing bank registers set 1.
+ */
+static void exynos5_set_bypass_dram_timings(struct exynos5_dmc *dmc)
+{
+ writel(EXYNOS5_AREF_NORMAL,
+ dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGAREF);
+
+ writel(dmc->bypass_timing_row,
+ dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGROW1);
+ writel(dmc->bypass_timing_row,
+ dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGROW1);
+ writel(dmc->bypass_timing_data,
+ dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGDATA1);
+ writel(dmc->bypass_timing_data,
+ dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGDATA1);
+ writel(dmc->bypass_timing_power,
+ dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGPOWER1);
+ writel(dmc->bypass_timing_power,
+ dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGPOWER1);
+}
+
+/**
+ * exynos5_dram_change_timings() - Low-level changes of the DRAM final timings
+ * @dmc: device for which the new settings is going to be applied
+ * @target_rate: target frequency of the DMC
+ *
+ * Low-level function for changing timings for DRAM memory operating from main
+ * clock source (BPLL), which can have different frequencies. Thus, each
+ * frequency must have corresponding timings register values in order to keep
+ * the needed delays.
+ * It uses timing bank registers set 0.
+ */
+static int exynos5_dram_change_timings(struct exynos5_dmc *dmc,
+ unsigned long target_rate)
+{
+ int idx;
+
+ for (idx = dmc->opp_count - 1; idx >= 0; idx--)
+ if (dmc->opp[idx].freq_hz <= target_rate)
+ break;
+
+ if (idx < 0)
+ return -EINVAL;
+
+ writel(EXYNOS5_AREF_NORMAL,
+ dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGAREF);
+
+ writel(dmc->timing_row[idx],
+ dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGROW0);
+ writel(dmc->timing_row[idx],
+ dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGROW0);
+ writel(dmc->timing_data[idx],
+ dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGDATA0);
+ writel(dmc->timing_data[idx],
+ dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGDATA0);
+ writel(dmc->timing_power[idx],
+ dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGPOWER0);
+ writel(dmc->timing_power[idx],
+ dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGPOWER0);
+
+ return 0;
+}
+
+/**
+ * exynos5_dmc_align_target_voltage() - Sets the final voltage for the DMC
+ * @dmc: device for which it is going to be set
+ * @target_volt: new voltage which is chosen to be final
+ *
+ * Function tries to align voltage to the safe level for 'normal' mode.
+ * It checks the need of higher voltage and changes the value. The target
+ * voltage might be lower that currently set and still the system will be
+ * stable.
+ */
+static int exynos5_dmc_align_target_voltage(struct exynos5_dmc *dmc,
+ unsigned long target_volt)
+{
+ int ret = 0;
+
+ if (dmc->curr_volt > target_volt) {
+ ret = regulator_set_voltage(dmc->vdd_mif, target_volt,
+ target_volt);
+ if (!ret)
+ dmc->curr_volt = target_volt;
+ }
+
+ return ret;
+}
+
+/**
+ * exynos5_dmc_align_bypass_voltage() - Sets the voltage for the DMC
+ * @dmc: device for which it is going to be set
+ * @target_volt: new voltage which is chosen to be final
+ *
+ * Function tries to align voltage to the safe level for the 'bypass' mode.
+ * It checks the need of higher voltage and changes the value.
+ * The target voltage must not be less than currently needed, because
+ * for current frequency the device might become unstable.
+ */
+static int exynos5_dmc_align_bypass_voltage(struct exynos5_dmc *dmc,
+ unsigned long target_volt)
+{
+ int ret = 0;
+ unsigned long bypass_volt = dmc->opp_bypass.volt_uv;
+
+ target_volt = max(bypass_volt, target_volt);
+
+ if (dmc->curr_volt >= target_volt)
+ return 0;
+
+ ret = regulator_set_voltage(dmc->vdd_mif, target_volt,
+ target_volt);
+ if (!ret)
+ dmc->curr_volt = target_volt;
+
+ return ret;
+}
+
+/**
+ * exynos5_dmc_align_bypass_dram_timings() - Chooses and sets DRAM timings
+ * @dmc: device for which it is going to be set
+ * @target_rate: new frequency which is chosen to be final
+ *
+ * Function changes the DRAM timings for the temporary 'bypass' mode.
+ */
+static int exynos5_dmc_align_bypass_dram_timings(struct exynos5_dmc *dmc,
+ unsigned long target_rate)
+{
+ int idx = find_target_freq_idx(dmc, target_rate);
+
+ if (idx < 0)
+ return -EINVAL;
+
+ exynos5_set_bypass_dram_timings(dmc);
+
+ return 0;
+}
+
+/**
+ * exynos5_dmc_switch_to_bypass_configuration() - Switching to temporary clock
+ * @dmc: DMC device for which the switching is going to happen
+ * @target_rate: new frequency which is going to be set as a final
+ * @target_volt: new voltage which is going to be set as a final
+ *
+ * Function configures DMC and clocks for operating in temporary 'bypass' mode.
+ * This mode is used only temporary but if required, changes voltage and timings
+ * for DRAM chips. It switches the main clock to stable clock source for the
+ * period of the main PLL reconfiguration.
+ */
+static int exynos5_dmc_switch_to_bypass_configuration(struct exynos5_dmc *dmc,
+ unsigned long target_rate,
+ unsigned long target_volt)
+{
+ int ret;
+
+ /*
+ * Having higher voltage for a particular frequency does not harm
+ * the chip. Use it for the temporary frequency change when one
+ * voltage manipulation might be avoided.
+ */
+ ret = exynos5_dmc_align_bypass_voltage(dmc, target_volt);
+ if (ret)
+ return ret;
+
+ /*
+ * Longer delays for DRAM does not cause crash, the opposite does.
+ */
+ ret = exynos5_dmc_align_bypass_dram_timings(dmc, target_rate);
+ if (ret)
+ return ret;
+
+ clk_enable(dmc->timing_set);
+
+ /*
+ * Voltage is set at least to a level needed for this frequency,
+ * so switching clock source is safe now.
+ */
+ clk_prepare_enable(dmc->fout_spll);
+ clk_prepare_enable(dmc->mout_spll);
+ clk_prepare_enable(dmc->mout_mx_mspll_ccore);
+
+ ret = clk_set_parent(dmc->mout_mclk_cdrex, dmc->mout_mx_mspll_ccore);
+
+ return ret;
+}
+
+/**
+ * exynos5_dmc_change_freq_and_volt() - Changes voltage and frequency of the DMC
+ * using safe procedure
+ * @dmc: device for which the frequency is going to be changed
+ * @target_rate: requested new frequency
+ * @target_volt: requested voltage which corresponds to the new frequency
+ *
+ * The DMC frequency change procedure requires a few steps.
+ * The main requirement is to change the clock source in the clk mux
+ * for the time of main clock PLL locking. The assumption is that the
+ * alternative clock source set as parent is stable.
+ * The second parent's clock frequency is fixed to 400MHz, it is named 'bypass'
+ * clock. This requires alignment in DRAM timing parameters for the new
+ * T-period. There is two bank sets for keeping DRAM
+ * timings: set 0 and set 1. The set 0 is used when main clock source is
+ * chosen. The 2nd set of regs is used for 'bypass' clock. Switching between
+ * the two bank sets is part of the process.
+ * The voltage must also be aligned to the minimum required level. There is
+ * this intermediate step with switching to 'bypass' parent clock source.
+ * if the old voltage is lower, it requires an increase of the voltage level.
+ * The complexity of the voltage manipulation is hidden in low level function.
+ * In this function there is last alignment of the voltage level at the end.
+ */
+static int
+exynos5_dmc_change_freq_and_volt(struct exynos5_dmc *dmc,
+ unsigned long target_rate,
+ unsigned long target_volt)
+{
+ int ret;
+
+ ret = exynos5_dmc_switch_to_bypass_configuration(dmc, target_rate,
+ target_volt);
+ if (ret)
+ return ret;
+
+ /* We are safe to increase the timings for current bypass frequency.
+ * Thanks to this the settings we be ready for the upcoming clock source
+ * change.
+ */
+ exynos5_dram_change_timings(dmc, target_rate);
+
+ clk_set_rate(dmc->fout_bpll, target_rate);
+
+ clk_disable(dmc->timing_set);
+
+ ret = clk_set_parent(dmc->mout_mclk_cdrex, dmc->mout_bpll);
+ if (ret)
+ return ret;
+
+ clk_disable_unprepare(dmc->mout_mx_mspll_ccore);
+ clk_disable_unprepare(dmc->mout_spll);
+ clk_disable_unprepare(dmc->fout_spll);
+ /* Make sure if the voltage is not from 'bypass' settings and align to
+ * the right level for power efficiency.
+ */
+ ret = exynos5_dmc_align_target_voltage(dmc, target_volt);
+
+ return ret;
+}
+
+/**
+ * exynos5_dmc_get_volt_freq() - Gets the frequency and voltage from the OPP
+ * table.
+ * @dev: device for which the frequency is going to be changed
+ * @freq: requested frequency in KHz
+ * @target_rate: returned frequency which is the same or lower than
+ * requested
+ * @target_volt: returned voltage which corresponds to the returned
+ * frequency
+ *
+ * Function gets requested frequency and checks OPP framework for needed
+ * frequency and voltage. It populates the values 'target_rate' and
+ * 'target_volt' or returns error value when OPP framework fails.
+ */
+static int exynos5_dmc_get_volt_freq(struct device *dev, unsigned long *freq,
+ unsigned long *target_rate,
+ unsigned long *target_volt, u32 flags)
+{
+ struct dev_pm_opp *opp;
+
+ opp = devfreq_recommended_opp(dev, freq, flags);
+ if (IS_ERR(opp))
+ return PTR_ERR(opp);
+
+ *target_rate = dev_pm_opp_get_freq(opp);
+ *target_volt = dev_pm_opp_get_voltage(opp);
+ dev_pm_opp_put(opp);
+
+ return 0;
+}
+
+/**
+ * exynos5_dmc_target() - Function responsible for changing frequency of DMC
+ * @dev: device for which the frequency is going to be changed
+ * @freq: requested frequency in KHz
+ * @flags: flags provided for this frequency change request
+ *
+ * An entry function provided to the devfreq framework which provides frequency
+ * change of the DMC. The function gets the possible rate from OPP table based
+ * on requested frequency. It calls the next function responsible for the
+ * frequency and voltage change. In case of failure, does not set 'curr_rate'
+ * and returns error value to the framework.
+ */
+static int exynos5_dmc_target(struct device *dev, unsigned long *freq,
+ u32 flags)
+{
+ struct exynos5_dmc *dmc = dev_get_drvdata(dev);
+ unsigned long target_rate = 0;
+ unsigned long target_volt = 0;
+ int ret;
+
+ ret = exynos5_dmc_get_volt_freq(dev, freq, &target_rate, &target_volt,
+ flags);
+ if (ret)
+ return ret;
+
+ if (target_rate == dmc->curr_rate)
+ return 0;
+
+ mutex_lock(&dmc->lock);
+
+ ret = exynos5_dmc_change_freq_and_volt(dmc, target_rate, target_volt);
+
+ if (ret) {
+ mutex_unlock(&dmc->lock);
+ return ret;
+ }
+
+ dmc->curr_rate = target_rate;
+
+ mutex_unlock(&dmc->lock);
+ return 0;
+}
+
+/**
+ * exynos5_cnt_name_match() - Tries to match 'edev' with the right device index
+ * @edev: event device for which the name is going to be matched
+ *
+ * Function matches the name of the 'edev' counter device with known devices
+ * with configured ratios and shares of the DMC channels.
+ * When the name is matched, it returns the index for the proper device.
+ */
+static int exynos5_cnt_name_match(struct devfreq_event_dev *edev)
+{
+ int i;
+ int id = -ENODEV;
+
+ for (i = 0; i < ARRAY_SIZE(dmc_slot); i++) {
+ if (strstr(edev->desc->name, dmc_slot[i].name))
+ return i;
+ }
+
+ return id;
+}
+
+/**
+ * exynos5_cnt_calculate() - Calculates the values of performance counters.
+ * @edev: event device for which the counter is used for calculation
+ * @cnt: raw counter value
+ * @cnt_norm: counter value normalized to DMC performance ratio for a proper
+ * channel or virtual channel
+ *
+ * Function calculates normalized value for the raw counter. The raw counter
+ * value does not show real channel usage. The DMC splits not equally the
+ * bandwidth for the channels. The function checks the type of the 'edev'
+ * counter and calculates the normalized value based on the 'shares' of the
+ * bandwidth set in the controller.
+ */
+static int exynos5_cnt_calculate(struct devfreq_event_dev *edev,
+ unsigned long cnt, u64 *cnt_norm)
+{
+ int idx;
+
+ idx = exynos5_cnt_name_match(edev);
+ if (idx < 0)
+ return idx;
+
+ *cnt_norm = cnt;
+
+ if (!(dmc_slot[idx].ratio_mul == dmc_slot[idx].ratio_div)) {
+ *cnt_norm = *cnt_norm * dmc_slot[idx].ratio_mul;
+ *cnt_norm = div_u64(*cnt_norm, dmc_slot[idx].ratio_div);
+ }
+
+ *cnt_norm = *cnt_norm * PPMU_PMCNT_CONST_RATIO_MUL;
+ *cnt_norm = div_u64(*cnt_norm, PPMU_PMCNT_CONST_RATIO_DIV);
+
+ return idx;
+}
+
+/**
+ * exynos5_counters_get() - Gets the performance counters values.
+ * @dmc: device for which the counters are going to be checked
+ * @load_count: variable which is populated with counter value
+ * @total_count: variable which is used as 'wall clock' reference
+ *
+ * Function which provides performance counters values. It sums up counters for
+ * two DMC channels. The 'total_count' is used as a reference and max value.
+ * The ratio 'load_count/total_count' shows the busy percentage [0%, 100%].
+ */
+static int exynos5_counters_get(struct exynos5_dmc *dmc,
+ unsigned long *load_count,
+ unsigned long *total_count)
+{
+ unsigned long load_dmc[2] = {0, 0};
+ unsigned long total = 0;
+ u64 load = 0;
+ struct devfreq_event_data event;
+ int ret, i, idx;
+
+ for (i = 0; i < dmc->num_counters; i++) {
+ if (!dmc->counter[i])
+ continue;
+
+ ret = devfreq_event_get_event(dmc->counter[i], &event);
+ if (ret < 0)
+ return ret;
+
+ idx = exynos5_cnt_calculate(dmc->counter[i], event.load_count,
+ &load);
+ if (idx < 0)
+ continue;
+
+ if (idx == DMC0_0 || idx == DMC0_1)
+ load_dmc[0] += load;
+ else
+ load_dmc[1] += load;
+
+ if (total < event.total_count)
+ total = event.total_count;
+ }
+
+ *load_count = load_dmc[0] + load_dmc[1];
+ *total_count = total;
+
+ return 0;
+}
+
+/**
+ * exynos5_dmc_get_status() - Read current DMC performance statistics.
+ * @dev: device for which the statistics are requested
+ * @stat: structure which has statistic fields
+ *
+ * Function reads the DMC performance counters and calculates 'busy_time'
+ * and 'total_time'. To protect from overflow, the values are shifted right
+ * by 10. After read out the counters are setup to count again.
+ */
+static int exynos5_dmc_get_status(struct device *dev,
+ struct devfreq_dev_status *stat)
+{
+ struct exynos5_dmc *dmc = dev_get_drvdata(dev);
+ unsigned long load, total;
+ int ret;
+ bool cnt_en;
+
+ mutex_lock(&dmc->lock);
+ cnt_en = dmc->counters_enabled;
+ mutex_unlock(&dmc->lock);
+ if (!cnt_en) {
+ dev_warn(dev, "performance counters needed, but not present\n");
+ return -EAGAIN;
+ }
+
+ ret = exynos5_counters_get(dmc, &load, &total);
+ if (ret < 0)
+ return -EINVAL;
+
+ /* To protect from overflow in calculation ratios, divide by 1024 */
+ stat->busy_time = load >> 10;
+ stat->total_time = total >> 10;
+
+ ret = exynos5_counters_set_event(dmc);
+ if (ret < 0) {
+ dev_err(dmc->dev, "could not set event counter\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+/**
+ * exynos5_dmc_get_cur_freq() - Function returns current DMC frequency
+ * @dev: device for which the framework checks operating frequency
+ * @freq: returned frequency value
+ *
+ * It returns the currently used frequency of the DMC. The real operating
+ * frequency might be lower when the clock source value could not be divided
+ * to the requested value.
+ */
+static int exynos5_dmc_get_cur_freq(struct device *dev, unsigned long *freq)
+{
+ struct exynos5_dmc *dmc = dev_get_drvdata(dev);
+
+ mutex_lock(&dmc->lock);
+ *freq = dmc->curr_rate;
+ mutex_unlock(&dmc->lock);
+
+ return 0;
+}
+
+/**
+ * exynos5_dmc_df_profile - Devfreq governor's profile structure
+ *
+ * It provides to the devfreq framework needed functions and polling period.
+ */
+static struct devfreq_dev_profile exynos5_dmc_df_profile = {
+ .polling_ms = 500,
+ .target = exynos5_dmc_target,
+ .get_dev_status = exynos5_dmc_get_status,
+ .get_cur_freq = exynos5_dmc_get_cur_freq,
+};
+
+/**
+ * exynos5_dmc_align_initial_frequency() - Align initial frequency value
+ * @dmc: device for which the frequency is going to be set
+ * @bootloader_init_freq: initial frequency set by the bootloader in KHz
+ *
+ * The initial bootloader frequency, which is present during boot, might be
+ * different that supported frequency values in the driver. It is possible
+ * due to different PLL settings or used PLL as a source.
+ * This function provides the 'initial_freq' for the devfreq framework
+ * statistics engine which supports only registered values. Thus, some alignment
+ * must be made.
+ */
+unsigned long
+exynos5_dmc_align_init_freq(struct exynos5_dmc *dmc,
+ unsigned long bootloader_init_freq)
+{
+ unsigned long aligned_freq;
+ int idx;
+
+ idx = find_target_freq_idx(dmc, bootloader_init_freq);
+ if (idx >= 0)
+ aligned_freq = dmc->opp[idx].freq_hz;
+ else
+ aligned_freq = dmc->opp[dmc->opp_count - 1].freq_hz;
+
+ return aligned_freq;
+}
+
+/**
+ * of_get_dram_timings() - helper function for parsing DT settings for DRAM
+ * @dmc: device for which the frequency is going to be set
+ *
+ * The function parses DT entries with DRAM information.
+ */
+static int of_get_dram_timings(struct exynos5_dmc *dmc)
+{
+ int ret = 0;
+ int count;
+ struct device_node *np;
+
+ np = of_find_compatible_node(NULL, NULL, "samsung,dram-timing");
+ if (!np)
+ return -EINVAL;
+
+ count = of_property_count_strings(np, "dram-timing-names");
+ if (count < 1)
+ return -EINVAL;
+
+ dmc->timing_row = devm_kmalloc_array(dmc->dev, count, sizeof(u32),
+ GFP_KERNEL);
+ if (!dmc->timing_row)
+ return -ENOMEM;
+
+ ret = of_property_read_u32_array(np, "dram-timing-row",
+ dmc->timing_row, count);
+
+ if (ret) {
+ dev_warn(dmc->dev, "failed parcing dram-timing-row\n");
+ return -EINVAL;
+ }
+
+ dmc->timing_data = devm_kmalloc_array(dmc->dev, count, sizeof(u32),
+ GFP_KERNEL);
+ if (!dmc->timing_data)
+ return -ENOMEM;
+
+ ret = of_property_read_u32_array(np, "dram-timing-data",
+ dmc->timing_data, count);
+ if (ret) {
+ dev_warn(dmc->dev, "failed parcing dram-timing-data\n");
+ return -EINVAL;
+ }
+
+ dmc->timing_power = devm_kmalloc_array(dmc->dev, count, sizeof(u32),
+ GFP_KERNEL);
+ if (!dmc->timing_power)
+ return -ENOMEM;
+
+ ret = of_property_read_u32_array(np, "dram-timing-power",
+ dmc->timing_power, count);
+ if (ret) {
+ dev_warn(dmc->dev, "failed parcing dram-timing-power\n");
+ return -EINVAL;
+ }
+
+ of_node_put(np);
+
+ np = of_find_compatible_node(NULL, NULL, "samsung,dmc-bypass-mode");
+ if (!np)
+ return -EINVAL;
+
+ ret = of_property_read_u32(np, "freq-hz",
+ &dmc->opp_bypass.freq_hz);
+
+ ret |= of_property_read_u32(np, "volt-uv",
+ &dmc->opp_bypass.volt_uv);
+
+ ret |= of_property_read_u32(np, "dram-timing-row",
+ &dmc->bypass_timing_row);
+
+ ret |= of_property_read_u32(np, "dram-timing-data",
+ &dmc->bypass_timing_data);
+
+ ret |= of_property_read_u32(np, "dram-timing-power",
+ &dmc->bypass_timing_power);
+
+ of_node_put(np);
+
+ return ret;
+}
+
+/**
+ * exynos5_dmc_init_clks() - Initialize clocks needed for DMC operation.
+ * @dev: device for which the clocks are setup
+ * @dmc: DMC structure containing needed fields
+ *
+ * Get the needed clocks defined in DT device, enable and set the right parents.
+ * Read current frequency and initialize the initial rate for governor.
+ */
+static int exynos5_dmc_init_clks(struct device *dev, struct exynos5_dmc *dmc)
+{
+ int ret;
+ unsigned long target_volt = 0;
+ unsigned long target_rate = 0;
+
+ dmc->fout_spll = devm_clk_get(dev, "fout_spll");
+ if (IS_ERR(dmc->fout_spll))
+ return PTR_ERR(dmc->fout_spll);
+
+ dmc->fout_bpll = devm_clk_get(dev, "fout_bpll");
+ if (IS_ERR(dmc->fout_bpll))
+ return PTR_ERR(dmc->fout_bpll);
+
+ dmc->mout_mclk_cdrex = devm_clk_get(dev, "mout_mclk_cdrex");
+ if (IS_ERR(dmc->mout_mclk_cdrex))
+ return PTR_ERR(dmc->mout_mclk_cdrex);
+
+ dmc->mout_bpll = devm_clk_get(dev, "mout_bpll");
+ if (IS_ERR(dmc->mout_bpll))
+ return PTR_ERR(dmc->mout_bpll);
+
+ dmc->mout_mx_mspll_ccore = devm_clk_get(dev, "mout_mx_mspll_ccore");
+ if (IS_ERR(dmc->mout_mx_mspll_ccore))
+ return PTR_ERR(dmc->mout_mx_mspll_ccore);
+
+ dmc->dout_clk2x_phy0 = devm_clk_get(dev, "dout_clk2x_phy0");
+ if (IS_ERR(dmc->dout_clk2x_phy0))
+ return PTR_ERR(dmc->dout_clk2x_phy0);
+
+ dmc->mout_spll = devm_clk_get(dev, "ff_dout_spll2");
+ if (IS_ERR(dmc->mout_spll))
+ return PTR_ERR(dmc->mout_spll);
+
+ dmc->cdrex_pause = devm_clk_get(dev, "clk_cdrex_pause");
+ if (IS_ERR(dmc->cdrex_pause))
+ return PTR_ERR(dmc->cdrex_pause);
+
+ dmc->timing_set = devm_clk_get(dev, "clk_cdrex_timing_set");
+ if (IS_ERR(dmc->timing_set))
+ return PTR_ERR(dmc->timing_set);
+ /*
+ * Convert frequency to KHz values and set it for the governor.
+ */
+ dmc->curr_rate = clk_get_rate(dmc->mout_mclk_cdrex);
+ dmc->curr_rate = exynos5_dmc_align_init_freq(dmc, dmc->curr_rate);
+ exynos5_dmc_df_profile.initial_freq = dmc->curr_rate;
+
+ ret = exynos5_dmc_get_volt_freq(dev, &dmc->curr_rate, &target_rate,
+ &target_volt, 0);
+ if (ret)
+ return ret;
+
+ dmc->curr_volt = target_volt;
+
+ clk_prepare_enable(dmc->mout_spll);
+ clk_set_parent(dmc->mout_mx_mspll_ccore, dmc->mout_spll);
+ clk_prepare_enable(dmc->mout_mx_mspll_ccore);
+
+ clk_prepare_enable(dmc->fout_bpll);
+ clk_prepare_enable(dmc->mout_bpll);
+
+ clk_prepare_enable(dmc->cdrex_pause);
+ clk_prepare(dmc->timing_set);
+
+ return 0;
+}
+
+/**
+ * exynos5_performance_counters_init() - Initializes performance DMC's counters
+ * @dmc: DMC for which it does the setup
+ *
+ * Initialization of performance counters in DMC for estimating usage.
+ * The counter's values are used for calculation of a memory bandwidth and based
+ * on that the governor changes the frequency.
+ * The counters are not used when the governor is GOVERNOR_USERSPACE.
+ */
+static int exynos5_performance_counters_init(struct exynos5_dmc *dmc)
+{
+ int counters_size;
+ int ret, i;
+
+ dmc->num_counters = devfreq_event_get_edev_count(dmc->dev);
+ if (dmc->num_counters < 0) {
+ dev_err(dmc->dev, "could not get devfreq-event counters\n");
+ return dmc->num_counters;
+ }
+
+ counters_size = sizeof(struct devfreq_event_dev) * dmc->num_counters;
+ dmc->counter = devm_kzalloc(dmc->dev, counters_size, GFP_KERNEL);
+ if (!dmc->counter)
+ return -ENOMEM;
+
+ for (i = 0; i < dmc->num_counters; i++) {
+ dmc->counter[i] =
+ devfreq_event_get_edev_by_phandle(dmc->dev, i);
+ if (IS_ERR_OR_NULL(dmc->counter[i]))
+ return -EPROBE_DEFER;
+ }
+
+ ret = exynos5_counters_enable_edev(dmc);
+ if (ret < 0) {
+ dev_err(dmc->dev, "could not enable event counter\n");
+ return ret;
+ }
+
+ ret = exynos5_counters_set_event(dmc);
+ if (ret < 0) {
+ dev_err(dmc->dev, "counld not set event counter\n");
+ return ret;
+ }
+
+ mutex_lock(&dmc->lock);
+ dmc->counters_enabled = true;
+ mutex_unlock(&dmc->lock);
+
+ return 0;
+}
+
+/**
+ * exynos5_dmc_probe() - Probe function for the DMC driver
+ * @pdev: platform device for which the driver is going to be initialized
+ *
+ * Initialize basic components: clocks, regulators, performance counters, etc.
+ * Read out product version and based on the information setup
+ * internal structures for the controller (frequency and voltage) and for DRAM
+ * memory parameters: timings for each operating frequency.
+ * Register new devfreq device for controlling DVFS of the DMC.
+ */
+static int exynos5_dmc_probe(struct platform_device *pdev)
+{
+ int ret = 0;
+ struct exynos5_dmc *dmc;
+ struct device *dev = &pdev->dev;
+ struct resource *res;
+
+ dmc = devm_kzalloc(dev, sizeof(*dmc), GFP_KERNEL);
+ if (!dmc)
+ return -ENOMEM;
+
+ mutex_init(&dmc->lock);
+
+ dmc->dev = dev;
+ platform_set_drvdata(pdev, dmc);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ dmc->base_drexi0 = devm_ioremap_resource(dev, res);
+ if (IS_ERR(dmc->base_drexi0))
+ return PTR_ERR(dmc->base_drexi0);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ dmc->base_drexi1 = devm_ioremap_resource(dev, res);
+ if (IS_ERR(dmc->base_drexi1))
+ return PTR_ERR(dmc->base_drexi1);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
+ dmc->chip_id = devm_ioremap_resource(dev, res);
+ if (IS_ERR(dmc->chip_id))
+ return PTR_ERR(dmc->chip_id);
+
+ ret = exynos5_dmc_chip_revision_settings(dmc);
+ if (ret)
+ return ret;
+
+ ret = exynos5_init_freq_table(dev, dmc, &exynos5_dmc_df_profile);
+ if (ret)
+ return ret;
+
+ ret = of_get_dram_timings(dmc);
+ if (ret)
+ return ret;
+
+ dmc->vdd_mif = devm_regulator_get(dev, "vdd_mif");
+ if (IS_ERR(dmc->vdd_mif)) {
+ ret = PTR_ERR(dmc->vdd_mif);
+ dev_warn(dev, "couldn't get regulator\n");
+ return ret;
+ }
+
+ ret = exynos5_dmc_init_clks(dev, dmc);
+ if (ret) {
+ dev_warn(dev, "couldn't initialize clocks\n");
+ return ret;
+ }
+
+ ret = exynos5_performance_counters_init(dmc);
+ if (ret) {
+ dev_warn(dev, "couldn't probe performance counters\n");
+ goto remove_clocks;
+ }
+ /*
+ * Setup default thresholds for the devfreq governor.
+ * The values are chosen based on experiments.
+ */
+ dmc->gov_data.upthreshold = 30;
+ dmc->gov_data.downdifferential = 5;
+
+ dmc->df = devm_devfreq_add_device(dev, &exynos5_dmc_df_profile,
+ DEVFREQ_GOV_USERSPACE,
+ &dmc->gov_data);
+
+ if (IS_ERR(dmc->df)) {
+ ret = PTR_ERR(dmc->df);
+ goto err_devfreq_add;
+ }
+
+ dev_info(&pdev->dev, "DMC init for prod_id=0x%08x pkg_id=0x%08x\n",
+ dmc->prod_rev, dmc->pkg_rev);
+
+ return 0;
+
+err_devfreq_add:
+ exynos5_counters_disable_edev(dmc);
+remove_clocks:
+ clk_disable_unprepare(dmc->mout_mx_mspll_ccore);
+ clk_disable_unprepare(dmc->mout_spll);
+
+ return ret;
+}
+
+/**
+ * exynos5_dmc_remove() - Remove function for the platform device
+ * @pdev: platform device which is going to be removed
+ *
+ * The function relies on 'devm' framework function which automatically
+ * clean the device's resources. It just calls explicitly disable function for
+ * the performance counters.
+ */
+static int exynos5_dmc_remove(struct platform_device *pdev)
+{
+ struct exynos5_dmc *dmc = dev_get_drvdata(&pdev->dev);
+
+ exynos5_counters_disable_edev(dmc);
+
+ clk_disable_unprepare(dmc->mout_mx_mspll_ccore);
+ clk_disable_unprepare(dmc->mout_spll);
+
+ dev_pm_opp_remove_table(&pdev->dev);
+
+ dev_info(&pdev->dev, "DMC removed\n");
+
+ return 0;
+}
+
+static const struct of_device_id exynos5_dmc_of_match[] = {
+ { .compatible = "samsung,exynos5422-dmc", },
+ { },
+};
+MODULE_DEVICE_TABLE(of, exynos5_dmc_of_match);
+
+static struct platform_driver exynos5_dmc_platdrv = {
+ .probe = exynos5_dmc_probe,
+ .remove = exynos5_dmc_remove,
+ .driver = {
+ .name = "exynos5-dmc",
+ .of_match_table = exynos5_dmc_of_match,
+ },
+};
+module_platform_driver(exynos5_dmc_platdrv);
+MODULE_DESCRIPTION("Driver for Exynos5422 Dynamic Memory Controller dynamic frequency and voltage change"
+);
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Samsung");
--
2.7.4
This patch provides support for clocks needed for Dynamic Memory Controller
in Exynos5422 SoC. It adds CDREX base register addresses, new DIV, MUX and
GATE entries.
Signed-off-by: Lukasz Luba <[email protected]>
---
drivers/clk/samsung/clk-exynos5420.c | 54 +++++++++++++++++++++++++++++++++---
1 file changed, 50 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 34cce3c..6da5875 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -134,6 +134,10 @@
#define SRC_CDREX 0x20200
#define DIV_CDREX0 0x20500
#define DIV_CDREX1 0x20504
+#define GATE_BUS_CDREX0 0x20700
+#define GATE_BUS_CDREX1 0x20704
+#define CDREX_PAUSE 0x2091c
+#define CDREX_LPDDR3PHY_CON3 0x20a20
#define KPLL_LOCK 0x28000
#define KPLL_CON0 0x28100
#define SRC_KFC 0x28200
@@ -248,6 +252,10 @@ static const unsigned long exynos5x_clk_regs[] __initconst = {
DIV_CDREX1,
SRC_KFC,
DIV_KFC0,
+ GATE_BUS_CDREX0,
+ GATE_BUS_CDREX1,
+ CDREX_PAUSE,
+ CDREX_LPDDR3PHY_CON3,
};
static const unsigned long exynos5800_clk_regs[] __initconst = {
@@ -425,6 +433,9 @@ PNAME(mout_group13_5800_p) = { "dout_osc_div", "mout_sw_aclkfl1_550_cam" };
PNAME(mout_group14_5800_p) = { "dout_aclk550_cam", "dout_sclk_sw" };
PNAME(mout_group15_5800_p) = { "dout_osc_div", "mout_sw_aclk550_cam" };
PNAME(mout_group16_5800_p) = { "dout_osc_div", "mout_mau_epll_clk" };
+PNAME(mout_mx_mspll_ccore_phy_p) = { "sclk_bpll", "mout_sclk_dpll",
+ "mout_sclk_mpll", "ff_dout_spll2",
+ "mout_sclk_spll", "mout_sclk_epll"};
/* fixed rate clocks generated outside the soc */
static struct samsung_fixed_rate_clock
@@ -450,7 +461,7 @@ static const struct samsung_fixed_factor_clock
static const struct samsung_fixed_factor_clock
exynos5800_fixed_factor_clks[] __initconst = {
FFACTOR(0, "ff_dout_epll2", "mout_sclk_epll", 1, 2, 0),
- FFACTOR(0, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0),
+ FFACTOR(CLK_FF_DOUT_SPLL2, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0),
};
static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
@@ -472,11 +483,14 @@ static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
MUX(0, "mout_aclk300_disp1", mout_group5_5800_p, SRC_TOP2, 24, 2),
MUX(0, "mout_aclk300_gscl", mout_group5_5800_p, SRC_TOP2, 28, 2),
+ MUX(CLK_MOUT_MX_MSPLL_CCORE_PHY, "mout_mx_mspll_ccore_phy",
+ mout_mx_mspll_ccore_phy_p, SRC_TOP7, 0, 3),
+
MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore",
- mout_mx_mspll_ccore_p, SRC_TOP7, 16, 2),
+ mout_mx_mspll_ccore_p, SRC_TOP7, 16, 3),
MUX_F(CLK_MOUT_MAU_EPLL, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p,
SRC_TOP7, 20, 2, CLK_SET_RATE_PARENT, 0),
- MUX(0, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1),
+ MUX(CLK_SCLK_BPLL, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1),
MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1),
MUX(0, "mout_aclk550_cam", mout_group3_5800_p, SRC_TOP8, 16, 3),
@@ -648,7 +662,7 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1),
MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1),
- MUX(0, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1),
+ MUX(CLK_MOUT_SCLK_SPLL, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1),
MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1),
MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1),
MUX_F(CLK_MOUT_EPLL, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1,
@@ -817,6 +831,8 @@ static const struct samsung_div_clock exynos5x_div_clks[] __initconst = {
DIV(CLK_DOUT_CLK2X_PHY0, "dout_clk2x_phy0", "dout_sclk_cdrex",
DIV_CDREX0, 3, 5),
+ DIV(0, "dout_pclk_drex0", "dout_cclk_drex0", DIV_CDREX0, 28, 3),
+
DIV(CLK_DOUT_PCLK_CORE_MEM, "dout_pclk_core_mem", "mout_mclk_cdrex",
DIV_CDREX1, 8, 3),
@@ -1170,6 +1186,36 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0),
GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0),
+
+ /* CDREX */
+ GATE(CLK_CLKM_PHY0, "clkm_phy0", "dout_sclk_cdrex",
+ GATE_BUS_CDREX0, 0, 0, 0),
+ GATE(CLK_CLKM_PHY1, "clkm_phy1", "dout_sclk_cdrex",
+ GATE_BUS_CDREX0, 1, 0, 0),
+ GATE(0, "mx_mspll_ccore_phy", "mout_mx_mspll_ccore_phy",
+ SRC_MASK_TOP7, 0, CLK_IGNORE_UNUSED, 0),
+
+ GATE(CLK_ACLK_PPMU_DREX1_1, "aclk_ppmu_drex1_1", "dout_aclk_cdrex1",
+ GATE_BUS_CDREX1, 12, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_PPMU_DREX1_0, "aclk_ppmu_drex1_0", "dout_aclk_cdrex1",
+ GATE_BUS_CDREX1, 13, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_PPMU_DREX0_1, "aclk_ppmu_drex0_1", "dout_aclk_cdrex1",
+ GATE_BUS_CDREX1, 14, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_PPMU_DREX0_0, "aclk_ppmu_drex0_0", "dout_aclk_cdrex1",
+ GATE_BUS_CDREX1, 15, CLK_IGNORE_UNUSED, 0),
+
+ GATE(CLK_PCLK_PPMU_DREX1_1, "pclk_ppmu_drex1_1", "dout_pclk_cdrex",
+ GATE_BUS_CDREX1, 26, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_PPMU_DREX1_0, "pclk_ppmu_drex1_0", "dout_pclk_cdrex",
+ GATE_BUS_CDREX1, 27, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_PPMU_DREX0_1, "pclk_ppmu_drex0_1", "dout_pclk_cdrex",
+ GATE_BUS_CDREX1, 28, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_PPMU_DREX0_0, "pclk_ppmu_drex0_0", "dout_pclk_cdrex",
+ GATE_BUS_CDREX1, 29, CLK_IGNORE_UNUSED, 0),
+
+ GATE(CLK_CDREX_PAUSE, "clk_cdrex_pause", NULL, CDREX_PAUSE, 0, 0, 0),
+ GATE(CLK_CDREX_TIMING_SET, "clk_cdrex_timing_set", NULL,
+ CDREX_LPDDR3PHY_CON3, 28, 0, 0),
};
static const struct samsung_div_clock exynos5x_disp_div_clks[] __initconst = {
--
2.7.4
On Tue, 5 Mar 2019 at 11:19, Lukasz Luba <[email protected]> wrote:
>
> The patch adds description for DT binding for a new Exynos5422 Dynamic
> Memory Controller device.
>
> Signed-off-by: Lukasz Luba <[email protected]>
> ---
> .../devicetree/bindings/devfreq/exynos5422-dmc.txt | 177 +++++++++++++++++++++
> 1 file changed, 177 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/devfreq/exynos5422-dmc.txt
>
> diff --git a/Documentation/devicetree/bindings/devfreq/exynos5422-dmc.txt b/Documentation/devicetree/bindings/devfreq/exynos5422-dmc.txt
> new file mode 100644
> index 0000000..0e73e98
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/devfreq/exynos5422-dmc.txt
> @@ -0,0 +1,177 @@
> +* Exynos5422 frequency and voltage scaling for Dynamic Memory Controller device
> +
> +The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the DRAM
> +memory chips are connected. The driver is to monitor the controller in runtime
> +and switch frequency and voltage. To monitor the usage of the controller in
> +runtime, the driver uses the PPMU (Platform Performance Monitoring Unit), which
> +is able to measure the current load of the memory.
> +When 'userspace' governor is used for the driver, an application is able to
> +switch the DMC frequency.
> +
> +Required properties for DMC device for Exynos5422:
> +- compatible: Should be "samsung,exynos5422-bus".
> +- clock-names : the name of clock used by the bus, "bus".
> +- clocks : phandles for clock specified in "clock-names" property.
> +- devfreq-events : phandles for PPMU devices connected to this DMC.
> +
> +The example definition of a DMC and PPMU devices declared in DT is shown below:
> +
> + ppmu_dmc0_0: ppmu@10d00000 {
> + compatible = "samsung,exynos-ppmu";
> + reg = <0x10d00000 0x2000>;
> + clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;
> + clock-names = "ppmu";
> + status = "okay";
> + events {
> + ppmu_event_dmc0_0: ppmu-event3-dmc0_0 {
> + event-name = "ppmu-event3-dmc0_0";
> + };
> + };
> + };
> +
> +
> + ppmu_dmc0_1: ppmu@10d10000 {
> + compatible = "samsung,exynos-ppmu";
> + reg = <0x10d10000 0x2000>;
> + clocks = <&clock CLK_PCLK_PPMU_DREX0_1>;
> + clock-names = "ppmu";
> + status = "okay";
> + events {
> + ppmu_event_dmc0_1: ppmu-event3-dmc0_1 {
> + event-name = "ppmu-event3-dmc0_1";
> + };
> + };
> + };
> +
> + ppmu_dmc1_0: ppmu@10d10000 {
> + compatible = "samsung,exynos-ppmu";
> + reg = <0x10d60000 0x2000>;
> + clocks = <&clock CLK_PCLK_PPMU_DREX1_0>;
> + clock-names = "ppmu";
> + status = "okay";
> + events {
> + ppmu_event_dmc1_0: ppmu-event3-dmc1_0 {
> + event-name = "ppmu-event3-dmc1_0";
> + };
> + };
> + };
> +
> + ppmu_dmc1_1: ppmu@10d70000 {
> + compatible = "samsung,exynos-ppmu";
> + reg = <0x10d70000 0x2000>;
> + clocks = <&clock CLK_PCLK_PPMU_DREX1_1>;
> + clock-names = "ppmu";
> + status = "okay";
> + events {
> + ppmu_event_dmc1_1: ppmu-event3-dmc1_1 {
> + event-name = "ppmu-event3-dmc1_1";
> + };
> + };
> + };
> +
> + dmc: memory-controller@10c20000 {
> + compatible = "samsung,exynos5422-dmc";
> + reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>,
> + <0x10000000 0x1000>;
> + clocks = <&clock CLK_FOUT_SPLL>,
> + <&clock CLK_MOUT_SCLK_SPLL>,
> + <&clock CLK_FF_DOUT_SPLL2>,
> + <&clock CLK_FOUT_BPLL>,
> + <&clock CLK_MOUT_BPLL>,
> + <&clock CLK_SCLK_BPLL>,
> + <&clock CLK_MOUT_MX_MSPLL_CCORE>,
> + <&clock CLK_MOUT_MX_MSPLL_CCORE_PHY>,
> + <&clock CLK_MOUT_MCLK_CDREX>,
> + <&clock CLK_DOUT_CLK2X_PHY0>,
> + <&clock CLK_CLKM_PHY0>,
> + <&clock CLK_CLKM_PHY1>,
> + <&clock CLK_CDREX_PAUSE>,
> + <&clock CLK_CDREX_TIMING_SET>;
> + clock-names = "fout_spll",
> + "mout_sclk_spll",
> + "ff_dout_spll2",
> + "fout_bpll",
> + "mout_bpll",
> + "sclk_bpll",
> + "mout_mx_mspll_ccore",
> + "mout_mx_mspll_ccore_phy",
> + "mout_mclk_cdrex",
> + "dout_clk2x_phy0",
> + "clkm_phy0",
> + "clkm_phy1",
> + "clk_cdrex_pause",
> + "clk_cdrex_timing_set";
> + status = "okay";
> + operating-points-v2 = <&dmc_opp_table>;
> + devfreq-events = <&ppmu_dmc0_0>, <&ppmu_dmc0_1>,
> + <&ppmu_dmc1_0>, <&ppmu_dmc1_1>;
> + };
> +
> +The needed timings of DRAM memory are stored in dedicated nodes.
> +There are two nodes with regular timings and for bypass mode.
> +
> + dmc_bypass_mode: bypass_mode {
> + compatible = "samsung,dmc-bypass-mode";
This looks like an example, not bindings.
> +
> + freq-hz = <400000000>;
> + volt-uv = <887500>;
-microvolt
Documentation/devicetree/bindings/property-units.txt
> + dram-timing-row = <0x365a9713>;
> + dram-timing-data = <0x4740085e>;
> + dram-timing-power = <0x543a0446>;
> + };
> +
> + dram_timing: timing {
> + compatible = "samsung,dram-timing";
Probably you should use timings from Documentation/devicetree/bindings/lpddr2/
If not, all the fields below should be described.
All these bindings (memory-controller, timings) look like description
of memory controller so maybe they should go into
Documentation/devicetree/bindings/memory-controllers ?
Best regards,
Krzysztof
> +
> + dram-timing-names = "165MHz", "206MHz", "275MHz", "413MHz",
> + "543MHz", "633MHz", "728MHz", "825MHz";
> + dram-timing-row = <0x11223185>, <0x112331C6>, <0x12244287>,
> + <0x1B35538A>, <0x244764CD>, <0x2A48758F>,
> + <0x30598651>, <0x365A9713>;
> + dram-timing-data = <0x2720085E>, <0x2720085E>, <0x2720085E>,
> + <0x2720085E>, <0x3730085E>, <0x3730085E>,
> + <0x3730085E>, <0x4740085E>;
> + dram-timing-power = <0x140C0225>, <0x180F0225>, <0x1C140225>,
> + <0x2C1D0225>, <0x38270335>, <0x402D0335>,
> + <0x4C330336>, <0x543A0446>;
> + };
> +
> +The frequencies supported by the DMC are stored in OPP table v2.
> +
> + dmc_opp_table: opp_table2 {
> + compatible = "operating-points-v2";
> +
> + opp00 {
> + opp-hz = /bits/ 64 <165000000>;
> + opp-microvolt = <875000>;
> + };
> + opp01 {
> + opp-hz = /bits/ 64 <206000000>;
> + opp-microvolt = <875000>;
> + };
> + opp02 {
> + opp-hz = /bits/ 64 <275000000>;
> + opp-microvolt = <875000>;
> + };
> + opp03 {
> + opp-hz = /bits/ 64 <413000000>;
> + opp-microvolt = <887500>;
> + };
> + opp04 {
> + opp-hz = /bits/ 64 <543000000>;
> + opp-microvolt = <937500>;
> + };
> + opp05 {
> + opp-hz = /bits/ 64 <633000000>;
> + opp-microvolt = <1012500>;
> + };
> + opp06 {
> + opp-hz = /bits/ 64 <728000000>;
> + opp-microvolt = <1037500>;
> + };
> + opp07 {
> + opp-hz = /bits/ 64 <825000000>;
> + opp-microvolt = <1050000>;
> + };
> + };
> +
> --
> 2.7.4
>
On Tue, 5 Mar 2019 at 11:19, Lukasz Luba <[email protected]>
wrote:>> Add description of Dynamic Memory Controller and PPMU
counters.> They are used by exynos5422-dmc driver.>> Signed-off-by:
Lukasz Luba <[email protected]>In previous email I asked to
fix the subject prefix in case of resend. Please fix it.
> ---
> arch/arm/boot/dts/exynos5420.dtsi | 83 +++++++++++++++++++++++++
> arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 87 +++++++++++++++++++++++++++
> 2 files changed, 170 insertions(+)
>
> diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
> index aaff158..fc00fda 100644
> --- a/arch/arm/boot/dts/exynos5420.dtsi
> +++ b/arch/arm/boot/dts/exynos5420.dtsi
> @@ -235,6 +235,41 @@
> status = "disabled";
> };
>
> + dmc: memory-controller@10c20000 {
> + compatible = "samsung,exynos5422-dmc";
> + reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>,
> + <0x10000000 0x1000>;
> + clocks = <&clock CLK_FOUT_SPLL>,
> + <&clock CLK_MOUT_SCLK_SPLL>,
> + <&clock CLK_FF_DOUT_SPLL2>,
> + <&clock CLK_FOUT_BPLL>,
> + <&clock CLK_MOUT_BPLL>,
> + <&clock CLK_SCLK_BPLL>,
> + <&clock CLK_MOUT_MX_MSPLL_CCORE>,
> + <&clock CLK_MOUT_MX_MSPLL_CCORE_PHY>,
> + <&clock CLK_MOUT_MCLK_CDREX>,
> + <&clock CLK_DOUT_CLK2X_PHY0>,
> + <&clock CLK_CLKM_PHY0>,
> + <&clock CLK_CLKM_PHY1>,
> + <&clock CLK_CDREX_PAUSE>,
> + <&clock CLK_CDREX_TIMING_SET>;
> + clock-names = "fout_spll",
> + "mout_sclk_spll",
> + "ff_dout_spll2",
> + "fout_bpll",
> + "mout_bpll",
> + "sclk_bpll",
> + "mout_mx_mspll_ccore",
> + "mout_mx_mspll_ccore_phy",
> + "mout_mclk_cdrex",
> + "dout_clk2x_phy0",
> + "clkm_phy0",
> + "clkm_phy1",
> + "clk_cdrex_pause",
> + "clk_cdrex_timing_set";
> + status = "disabled";
> + };
> +
> nocp_mem0_0: nocp@10ca1000 {
> compatible = "samsung,exynos5420-nocp";
> reg = <0x10CA1000 0x200>;
> @@ -271,6 +306,54 @@
> status = "disabled";
> };
>
> + ppmu_dmc0_0: ppmu@10d00000 {
> + compatible = "samsung,exynos-ppmu";
> + reg = <0x10d00000 0x2000>;
> + clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;
> + clock-names = "ppmu";
> + events {
> + ppmu_event_dmc0_0: ppmu-event3-dmc0_0 {
> + event-name = "ppmu-event3-dmc0_0";
> + };
> + };
> + };
> +
> + ppmu_dmc0_1: ppmu@10d10000 {
> + compatible = "samsung,exynos-ppmu";
> + reg = <0x10d10000 0x2000>;
> + clocks = <&clock CLK_PCLK_PPMU_DREX0_1>;
> + clock-names = "ppmu";
> + events {
> + ppmu_event_dmc0_1: ppmu-event3-dmc0_1 {
> + event-name = "ppmu-event3-dmc0_1";
> + };
> + };
> + };
> +
> + ppmu_dmc1_0: ppmu@10d10000 {
> + compatible = "samsung,exynos-ppmu";
> + reg = <0x10d60000 0x2000>;
> + clocks = <&clock CLK_PCLK_PPMU_DREX1_0>;
> + clock-names = "ppmu";
> + events {
> + ppmu_event_dmc1_0: ppmu-event3-dmc1_0 {
> + event-name = "ppmu-event3-dmc1_0";
> + };
> + };
> + };
> +
> + ppmu_dmc1_1: ppmu@10d70000 {
> + compatible = "samsung,exynos-ppmu";
> + reg = <0x10d70000 0x2000>;
> + clocks = <&clock CLK_PCLK_PPMU_DREX1_1>;
> + clock-names = "ppmu";
> + events {
> + ppmu_event_dmc1_1: ppmu-event3-dmc1_1 {
> + event-name = "ppmu-event3-dmc1_1";
> + };
> + };
> + };
> +
> gsc_pd: power-domain@10044000 {
> compatible = "samsung,exynos4210-pd";
> reg = <0x10044000 0x20>;
> diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
> index bf09eab..6b28fb3 100644
> --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
> +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
> @@ -34,6 +34,69 @@
> clock-frequency = <24000000>;
> };
> };
> +
> + dmc_opp_table: opp_table2 {
> + compatible = "operating-points-v2";
> +
> + opp00 {
> + opp-hz = /bits/ 64 <165000000>;
> + opp-microvolt = <875000>;
> + };
> + opp01 {
> + opp-hz = /bits/ 64 <206000000>;
> + opp-microvolt = <875000>;
> + };
> + opp02 {
> + opp-hz = /bits/ 64 <275000000>;
> + opp-microvolt = <875000>;
> + };
> + opp03 {
> + opp-hz = /bits/ 64 <413000000>;
> + opp-microvolt = <887500>;
> + };
> + opp04 {
> + opp-hz = /bits/ 64 <543000000>;
> + opp-microvolt = <937500>;
> + };
> + opp05 {
> + opp-hz = /bits/ 64 <633000000>;
> + opp-microvolt = <1012500>;
> + };
> + opp06 {
> + opp-hz = /bits/ 64 <728000000>;
> + opp-microvolt = <1037500>;
> + };
> + opp07 {
> + opp-hz = /bits/ 64 <825000000>;
> + opp-microvolt = <1050000>;
> + };
> + };
> +
> + dmc_bypass_mode: bypass_mode {
> + compatible = "samsung,dmc-bypass-mode";
> +
> + freq-hz = <400000000>;
> + volt-uv = <887500>;
> + dram-timing-row = <0x365a9713>;
> + dram-timing-data = <0x4740085e>;
> + dram-timing-power = <0x543a0446>;
> + };
> +
> + dram_timing: timing {
> + compatible = "samsung,dram-timing";
> +
> + dram-timing-names = "165MHz", "206MHz", "275MHz", "413MHz",
> + "543MHz", "633MHz", "728MHz", "825MHz";
> + dram-timing-row = <0x11223185>, <0x112331C6>, <0x12244287>,
> + <0x1B35538A>, <0x244764CD>, <0x2A48758F>,
> + <0x30598651>, <0x365A9713>;
> + dram-timing-data = <0x2720085E>, <0x2720085E>, <0x2720085E>,
> + <0x2720085E>, <0x3730085E>, <0x3730085E>,
> + <0x3730085E>, <0x4740085E>;
> + dram-timing-power = <0x140C0225>, <0x180F0225>, <0x1C140225>,
> + <0x2C1D0225>, <0x38270335>, <0x402D0335>,
> + <0x4C330336>, <0x543A0446>;
> + };
> };
>
> &bus_wcore {
> @@ -127,6 +190,14 @@
> cpu-supply = <&buck2_reg>;
> };
>
> +&dmc {
> + devfreq-events = <&ppmu_dmc0_0>, <&ppmu_dmc0_1>,
> + <&ppmu_dmc1_0>, <&ppmu_dmc1_1>;
> +
> + operating-points-v2 = <&dmc_opp_table>;
The opp-tables have voltage entry but I do not see the regulator
supply. How do you change the voltage?
Best regards,
Krzysztof
Hi Lukasz,
I'm talking about it repeatedly. How many times already, I mentioned
that you have to resend the patch after completed the discussion.
I replied this v3 patch[2]. But, you didn't reply or answer anything
and then just send the same patch without any consent.
- Re: [PATCH v3 3/8] clk: samsung: add BPLL rate table for Exynos 5422 SoC
[2] https://lkml.org/lkml/2019/2/11/198
On 19. 3. 5. 오후 7:19, Lukasz Luba wrote:
> Add new table rate for BPLL for Exynos5422 SoC supporting Dynamic Memory
> Controller frequencies for driver's DRAM timings.
>
> Signed-off-by: Lukasz Luba <[email protected]>
> ---
> drivers/clk/samsung/clk-exynos5420.c | 13 ++++++++++++-
> 1 file changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
> index 6da5875..6f5db70 100644
> --- a/drivers/clk/samsung/clk-exynos5420.c
> +++ b/drivers/clk/samsung/clk-exynos5420.c
> @@ -1331,6 +1331,17 @@ static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __ini
> PLL_35XX_RATE(24 * MHZ, 200000000, 200, 3, 3),
> };
>
> +static const struct samsung_pll_rate_table exynos5422_bpll_rate_table[] = {
> + PLL_35XX_RATE(24 * MHZ, 825000000, 275, 4, 1),
> + PLL_35XX_RATE(24 * MHZ, 728000000, 182, 3, 1),
> + PLL_35XX_RATE(24 * MHZ, 633000000, 211, 4, 1),
> + PLL_35XX_RATE(24 * MHZ, 543000000, 181, 2, 2),
> + PLL_35XX_RATE(24 * MHZ, 413000000, 413, 6, 2),
> + PLL_35XX_RATE(24 * MHZ, 275000000, 275, 3, 3),
> + PLL_35XX_RATE(24 * MHZ, 206000000, 206, 3, 3),
> + PLL_35XX_RATE(24 * MHZ, 165000000, 110, 2, 3),
> +};
> +
> static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = {
> PLL_36XX_RATE(24 * MHZ, 600000000U, 100, 2, 1, 0),
> PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0),
> @@ -1473,7 +1484,7 @@ static void __init exynos5x_clk_init(struct device_node *np,
> exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl;
> exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl;
> exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
> - exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
> + exynos5x_plls[bpll].rate_table = exynos5422_bpll_rate_table;
> }
>
> samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls),
>
--
Best Regards,
Chanwoo Choi
Samsung Electronics
Hi Lukasz,
On 19. 3. 5. 오후 7:19, Lukasz Luba wrote:
> The patch adds description for DT binding for a new Exynos5422 Dynamic
> Memory Controller device.
>
> Signed-off-by: Lukasz Luba <[email protected]>
> ---
> .../devicetree/bindings/devfreq/exynos5422-dmc.txt | 177 +++++++++++++++++++++
> 1 file changed, 177 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/devfreq/exynos5422-dmc.txt
>
> diff --git a/Documentation/devicetree/bindings/devfreq/exynos5422-dmc.txt b/Documentation/devicetree/bindings/devfreq/exynos5422-dmc.txt
> new file mode 100644
> index 0000000..0e73e98
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/devfreq/exynos5422-dmc.txt
> @@ -0,0 +1,177 @@
> +* Exynos5422 frequency and voltage scaling for Dynamic Memory Controller device
> +
> +The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the DRAM
> +memory chips are connected. The driver is to monitor the controller in runtime
> +and switch frequency and voltage. To monitor the usage of the controller in
> +runtime, the driver uses the PPMU (Platform Performance Monitoring Unit), which
> +is able to measure the current load of the memory.
> +When 'userspace' governor is used for the driver, an application is able to
> +switch the DMC frequency.
> +
> +Required properties for DMC device for Exynos5422:
> +- compatible: Should be "samsung,exynos5422-bus".
> +- clock-names : the name of clock used by the bus, "bus".
> +- clocks : phandles for clock specified in "clock-names" property.
> +- devfreq-events : phandles for PPMU devices connected to this DMC.
I already replied with following comments on v4 patch[1].
But, you didn't reply anything. We can reduce the duplicate
review by keeping the basic review rule.
- Re: [PATCH v4 5/8] dt-bindings: devfreq: add Exynos5422 DMC device description
[1] https://do-db2.lkml.org/lkml/2019/2/3/64
[Following comments were replied on v4 patch[1]]
> +- compatible: Should be "samsung,exynos5422-bus".
The compatible name is wrong.
- exynos5422-bus -> exynos5422-dmc
> +- clock-names : the name of clock used by the bus, "bus".
'bus' is right?
> +- clocks : phandles for clock specified in "clock-names" property.
> +- devfreq-events : phandles for PPMU devices connected to this DMC.
The dt-binging file doesn't contain the any description for 'reg' properties.
> +
> +The example definition of a DMC and PPMU devices declared in DT is shown below:
> +
> + ppmu_dmc0_0: ppmu@10d00000 {
> + compatible = "samsung,exynos-ppmu";
> + reg = <0x10d00000 0x2000>;
> + clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;
> + clock-names = "ppmu";
> + status = "okay";
> + events {
> + ppmu_event_dmc0_0: ppmu-event3-dmc0_0 {
> + event-name = "ppmu-event3-dmc0_0";
> + };
> + };
> + };
> +
> +
> + ppmu_dmc0_1: ppmu@10d10000 {
> + compatible = "samsung,exynos-ppmu";
> + reg = <0x10d10000 0x2000>;
> + clocks = <&clock CLK_PCLK_PPMU_DREX0_1>;
> + clock-names = "ppmu";
> + status = "okay";
> + events {
> + ppmu_event_dmc0_1: ppmu-event3-dmc0_1 {
> + event-name = "ppmu-event3-dmc0_1";
> + };
> + };
> + };
> +
> + ppmu_dmc1_0: ppmu@10d10000 {
> + compatible = "samsung,exynos-ppmu";
> + reg = <0x10d60000 0x2000>;
> + clocks = <&clock CLK_PCLK_PPMU_DREX1_0>;
> + clock-names = "ppmu";
> + status = "okay";
> + events {
> + ppmu_event_dmc1_0: ppmu-event3-dmc1_0 {
> + event-name = "ppmu-event3-dmc1_0";
> + };
> + };
> + };
> +
> + ppmu_dmc1_1: ppmu@10d70000 {
> + compatible = "samsung,exynos-ppmu";
> + reg = <0x10d70000 0x2000>;
> + clocks = <&clock CLK_PCLK_PPMU_DREX1_1>;
> + clock-names = "ppmu";
> + status = "okay";
> + events {
> + ppmu_event_dmc1_1: ppmu-event3-dmc1_1 {
> + event-name = "ppmu-event3-dmc1_1";
> + };
> + };
> + };
> +
> + dmc: memory-controller@10c20000 {
> + compatible = "samsung,exynos5422-dmc";
> + reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>,
> + <0x10000000 0x1000>;
> + clocks = <&clock CLK_FOUT_SPLL>,
> + <&clock CLK_MOUT_SCLK_SPLL>,
> + <&clock CLK_FF_DOUT_SPLL2>,
> + <&clock CLK_FOUT_BPLL>,
> + <&clock CLK_MOUT_BPLL>,
> + <&clock CLK_SCLK_BPLL>,
> + <&clock CLK_MOUT_MX_MSPLL_CCORE>,
> + <&clock CLK_MOUT_MX_MSPLL_CCORE_PHY>,
> + <&clock CLK_MOUT_MCLK_CDREX>,
> + <&clock CLK_DOUT_CLK2X_PHY0>,
> + <&clock CLK_CLKM_PHY0>,
> + <&clock CLK_CLKM_PHY1>,
> + <&clock CLK_CDREX_PAUSE>,
> + <&clock CLK_CDREX_TIMING_SET>;
> + clock-names = "fout_spll",
> + "mout_sclk_spll",
> + "ff_dout_spll2",
> + "fout_bpll",
> + "mout_bpll",
> + "sclk_bpll",
> + "mout_mx_mspll_ccore",
> + "mout_mx_mspll_ccore_phy",
> + "mout_mclk_cdrex",
> + "dout_clk2x_phy0",
> + "clkm_phy0",
> + "clkm_phy1",
> + "clk_cdrex_pause",
> + "clk_cdrex_timing_set";
> + status = "okay";
> + operating-points-v2 = <&dmc_opp_table>;
> + devfreq-events = <&ppmu_dmc0_0>, <&ppmu_dmc0_1>,
> + <&ppmu_dmc1_0>, <&ppmu_dmc1_1>;
> + };
> +
> +The needed timings of DRAM memory are stored in dedicated nodes.
> +There are two nodes with regular timings and for bypass mode.
> +
> + dmc_bypass_mode: bypass_mode {
> + compatible = "samsung,dmc-bypass-mode";
> +
> + freq-hz = <400000000>;
> + volt-uv = <887500>;
> + dram-timing-row = <0x365a9713>;
> + dram-timing-data = <0x4740085e>;
> + dram-timing-power = <0x543a0446>;
> + };
> +
> + dram_timing: timing {
> + compatible = "samsung,dram-timing";
> +
> + dram-timing-names = "165MHz", "206MHz", "275MHz", "413MHz",
> + "543MHz", "633MHz", "728MHz", "825MHz";
> + dram-timing-row = <0x11223185>, <0x112331C6>, <0x12244287>,
> + <0x1B35538A>, <0x244764CD>, <0x2A48758F>,
> + <0x30598651>, <0x365A9713>;
> + dram-timing-data = <0x2720085E>, <0x2720085E>, <0x2720085E>,
> + <0x2720085E>, <0x3730085E>, <0x3730085E>,
> + <0x3730085E>, <0x4740085E>;
> + dram-timing-power = <0x140C0225>, <0x180F0225>, <0x1C140225>,
> + <0x2C1D0225>, <0x38270335>, <0x402D0335>,
> + <0x4C330336>, <0x543A0446>;
> + };
> +
> +The frequencies supported by the DMC are stored in OPP table v2.
> +
> + dmc_opp_table: opp_table2 {
> + compatible = "operating-points-v2";
> +
> + opp00 {
> + opp-hz = /bits/ 64 <165000000>;
> + opp-microvolt = <875000>;
> + };
> + opp01 {
> + opp-hz = /bits/ 64 <206000000>;
> + opp-microvolt = <875000>;
> + };
> + opp02 {
> + opp-hz = /bits/ 64 <275000000>;
> + opp-microvolt = <875000>;
> + };
> + opp03 {
> + opp-hz = /bits/ 64 <413000000>;
> + opp-microvolt = <887500>;
> + };
> + opp04 {
> + opp-hz = /bits/ 64 <543000000>;
> + opp-microvolt = <937500>;
> + };
> + opp05 {
> + opp-hz = /bits/ 64 <633000000>;
> + opp-microvolt = <1012500>;
> + };
> + opp06 {
> + opp-hz = /bits/ 64 <728000000>;
> + opp-microvolt = <1037500>;
> + };
> + opp07 {
> + opp-hz = /bits/ 64 <825000000>;
> + opp-microvolt = <1050000>;
> + };
> + };
> +
>
--
Best Regards,
Chanwoo Choi
Samsung Electronics
Hi Chanwoo,
On 3/6/19 5:18 AM, Chanwoo Choi wrote:
> Hi Lukasz,
>
> On 19. 3. 5. 오후 7:19, Lukasz Luba wrote:
>> The patch adds description for DT binding for a new Exynos5422 Dynamic
>> Memory Controller device.
>>
>> Signed-off-by: Lukasz Luba <[email protected]>
>> ---
>> .../devicetree/bindings/devfreq/exynos5422-dmc.txt | 177 +++++++++++++++++++++
>> 1 file changed, 177 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/devfreq/exynos5422-dmc.txt
>>
>> diff --git a/Documentation/devicetree/bindings/devfreq/exynos5422-dmc.txt b/Documentation/devicetree/bindings/devfreq/exynos5422-dmc.txt
>> new file mode 100644
>> index 0000000..0e73e98
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/devfreq/exynos5422-dmc.txt
>> @@ -0,0 +1,177 @@
>> +* Exynos5422 frequency and voltage scaling for Dynamic Memory Controller device
>> +
>> +The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the DRAM
>> +memory chips are connected. The driver is to monitor the controller in runtime
>> +and switch frequency and voltage. To monitor the usage of the controller in
>> +runtime, the driver uses the PPMU (Platform Performance Monitoring Unit), which
>> +is able to measure the current load of the memory.
>> +When 'userspace' governor is used for the driver, an application is able to
>> +switch the DMC frequency.
>> +
>> +Required properties for DMC device for Exynos5422:
>> +- compatible: Should be "samsung,exynos5422-bus".
>> +- clock-names : the name of clock used by the bus, "bus".
>> +- clocks : phandles for clock specified in "clock-names" property.
>> +- devfreq-events : phandles for PPMU devices connected to this DMC.
>
>
> I already replied with following comments on v4 patch[1].
> But, you didn't reply anything. We can reduce the duplicate
> review by keeping the basic review rule.
I have lost these changes while I was adding the OPPs, timings into the
dt-binding.
>
> - Re: [PATCH v4 5/8] dt-bindings: devfreq: add Exynos5422 DMC device description
> [1] https://do-db2.lkml.org/lkml/2019/2/3/64
>
>
> [Following comments were replied on v4 patch[1]]
>
>> +- compatible: Should be "samsung,exynos5422-bus".
>
> The compatible name is wrong.
> - exynos5422-bus -> exynos5422-dmc
>
>> +- clock-names : the name of clock used by the bus, "bus".
>
> 'bus' is right?
right
>
>> +- clocks : phandles for clock specified in "clock-names" property.
>> +- devfreq-events : phandles for PPMU devices connected to this DMC.
>
> The dt-binging file doesn't contain the any description for 'reg' properties.
There are 3 regs: cdrex0, cdrex1, chip_id. I will add this description.
The patch set has this OPPs and timings coming from DT as you requested
but I am not sure if it is in the right place in the DT.
Thus dt-binding you may consider as 'in-progress' till the DT entries
are fixed
Regards,
Lukasz
>
>
>
>> +
>> +The example definition of a DMC and PPMU devices declared in DT is shown below:
>> +
>> + ppmu_dmc0_0: ppmu@10d00000 {
>> + compatible = "samsung,exynos-ppmu";
>> + reg = <0x10d00000 0x2000>;
>> + clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;
>> + clock-names = "ppmu";
>> + status = "okay";
>> + events {
>> + ppmu_event_dmc0_0: ppmu-event3-dmc0_0 {
>> + event-name = "ppmu-event3-dmc0_0";
>> + };
>> + };
>> + };
>> +
>> +
>> + ppmu_dmc0_1: ppmu@10d10000 {
>> + compatible = "samsung,exynos-ppmu";
>> + reg = <0x10d10000 0x2000>;
>> + clocks = <&clock CLK_PCLK_PPMU_DREX0_1>;
>> + clock-names = "ppmu";
>> + status = "okay";
>> + events {
>> + ppmu_event_dmc0_1: ppmu-event3-dmc0_1 {
>> + event-name = "ppmu-event3-dmc0_1";
>> + };
>> + };
>> + };
>> +
>> + ppmu_dmc1_0: ppmu@10d10000 {
>> + compatible = "samsung,exynos-ppmu";
>> + reg = <0x10d60000 0x2000>;
>> + clocks = <&clock CLK_PCLK_PPMU_DREX1_0>;
>> + clock-names = "ppmu";
>> + status = "okay";
>> + events {
>> + ppmu_event_dmc1_0: ppmu-event3-dmc1_0 {
>> + event-name = "ppmu-event3-dmc1_0";
>> + };
>> + };
>> + };
>> +
>> + ppmu_dmc1_1: ppmu@10d70000 {
>> + compatible = "samsung,exynos-ppmu";
>> + reg = <0x10d70000 0x2000>;
>> + clocks = <&clock CLK_PCLK_PPMU_DREX1_1>;
>> + clock-names = "ppmu";
>> + status = "okay";
>> + events {
>> + ppmu_event_dmc1_1: ppmu-event3-dmc1_1 {
>> + event-name = "ppmu-event3-dmc1_1";
>> + };
>> + };
>> + };
>> +
>> + dmc: memory-controller@10c20000 {
>> + compatible = "samsung,exynos5422-dmc";
>> + reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>,
>> + <0x10000000 0x1000>;
>> + clocks = <&clock CLK_FOUT_SPLL>,
>> + <&clock CLK_MOUT_SCLK_SPLL>,
>> + <&clock CLK_FF_DOUT_SPLL2>,
>> + <&clock CLK_FOUT_BPLL>,
>> + <&clock CLK_MOUT_BPLL>,
>> + <&clock CLK_SCLK_BPLL>,
>> + <&clock CLK_MOUT_MX_MSPLL_CCORE>,
>> + <&clock CLK_MOUT_MX_MSPLL_CCORE_PHY>,
>> + <&clock CLK_MOUT_MCLK_CDREX>,
>> + <&clock CLK_DOUT_CLK2X_PHY0>,
>> + <&clock CLK_CLKM_PHY0>,
>> + <&clock CLK_CLKM_PHY1>,
>> + <&clock CLK_CDREX_PAUSE>,
>> + <&clock CLK_CDREX_TIMING_SET>;
>> + clock-names = "fout_spll",
>> + "mout_sclk_spll",
>> + "ff_dout_spll2",
>> + "fout_bpll",
>> + "mout_bpll",
>> + "sclk_bpll",
>> + "mout_mx_mspll_ccore",
>> + "mout_mx_mspll_ccore_phy",
>> + "mout_mclk_cdrex",
>> + "dout_clk2x_phy0",
>> + "clkm_phy0",
>> + "clkm_phy1",
>> + "clk_cdrex_pause",
>> + "clk_cdrex_timing_set";
>> + status = "okay";
>> + operating-points-v2 = <&dmc_opp_table>;
>> + devfreq-events = <&ppmu_dmc0_0>, <&ppmu_dmc0_1>,
>> + <&ppmu_dmc1_0>, <&ppmu_dmc1_1>;
>> + };
>> +
>> +The needed timings of DRAM memory are stored in dedicated nodes.
>> +There are two nodes with regular timings and for bypass mode.
>> +
>> + dmc_bypass_mode: bypass_mode {
>> + compatible = "samsung,dmc-bypass-mode";
>> +
>> + freq-hz = <400000000>;
>> + volt-uv = <887500>;
>> + dram-timing-row = <0x365a9713>;
>> + dram-timing-data = <0x4740085e>;
>> + dram-timing-power = <0x543a0446>;
>> + };
>> +
>> + dram_timing: timing {
>> + compatible = "samsung,dram-timing";
>> +
>> + dram-timing-names = "165MHz", "206MHz", "275MHz", "413MHz",
>> + "543MHz", "633MHz", "728MHz", "825MHz";
>> + dram-timing-row = <0x11223185>, <0x112331C6>, <0x12244287>,
>> + <0x1B35538A>, <0x244764CD>, <0x2A48758F>,
>> + <0x30598651>, <0x365A9713>;
>> + dram-timing-data = <0x2720085E>, <0x2720085E>, <0x2720085E>,
>> + <0x2720085E>, <0x3730085E>, <0x3730085E>,
>> + <0x3730085E>, <0x4740085E>;
>> + dram-timing-power = <0x140C0225>, <0x180F0225>, <0x1C140225>,
>> + <0x2C1D0225>, <0x38270335>, <0x402D0335>,
>> + <0x4C330336>, <0x543A0446>;
>> + };
>> +
>> +The frequencies supported by the DMC are stored in OPP table v2.
>> +
>> + dmc_opp_table: opp_table2 {
>> + compatible = "operating-points-v2";
>> +
>> + opp00 {
>> + opp-hz = /bits/ 64 <165000000>;
>> + opp-microvolt = <875000>;
>> + };
>> + opp01 {
>> + opp-hz = /bits/ 64 <206000000>;
>> + opp-microvolt = <875000>;
>> + };
>> + opp02 {
>> + opp-hz = /bits/ 64 <275000000>;
>> + opp-microvolt = <875000>;
>> + };
>> + opp03 {
>> + opp-hz = /bits/ 64 <413000000>;
>> + opp-microvolt = <887500>;
>> + };
>> + opp04 {
>> + opp-hz = /bits/ 64 <543000000>;
>> + opp-microvolt = <937500>;
>> + };
>> + opp05 {
>> + opp-hz = /bits/ 64 <633000000>;
>> + opp-microvolt = <1012500>;
>> + };
>> + opp06 {
>> + opp-hz = /bits/ 64 <728000000>;
>> + opp-microvolt = <1037500>;
>> + };
>> + opp07 {
>> + opp-hz = /bits/ 64 <825000000>;
>> + opp-microvolt = <1050000>;
>> + };
>> + };
>> +
>>
>
>
Hi Chanwoo,
On 3/6/19 2:31 AM, Chanwoo Choi wrote:
> Hi Lukasz,
>
> I'm talking about it repeatedly. How many times already, I mentioned
> that you have to resend the patch after completed the discussion.
>
>
> I replied this v3 patch[2]. But, you didn't reply or answer anything
> and then just send the same patch without any consent.
>
> - Re: [PATCH v3 3/8] clk: samsung: add BPLL rate table for Exynos 5422 SoC
> [2] https://lkml.org/lkml/2019/2/11/198
The second table from the example is not compiled and never be.
The rates where tested and they work. As I said the BPLL is used only
for DMC, thus it can be used instead of the default
exynos5420_pll2550x_24mhz_tbl.
It is worth to keep it as a separate table because adding
these entries to generic PLL table might cause issues for other PLLs.
Regards,
Lukasz
>
>
>
> On 19. 3. 5. 오후 7:19, Lukasz Luba wrote:
>> Add new table rate for BPLL for Exynos5422 SoC supporting Dynamic Memory
>> Controller frequencies for driver's DRAM timings.
>>
>> Signed-off-by: Lukasz Luba <[email protected]>
>> ---
>> drivers/clk/samsung/clk-exynos5420.c | 13 ++++++++++++-
>> 1 file changed, 12 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
>> index 6da5875..6f5db70 100644
>> --- a/drivers/clk/samsung/clk-exynos5420.c
>> +++ b/drivers/clk/samsung/clk-exynos5420.c
>> @@ -1331,6 +1331,17 @@ static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __ini
>> PLL_35XX_RATE(24 * MHZ, 200000000, 200, 3, 3),
>> };
>>
>> +static const struct samsung_pll_rate_table exynos5422_bpll_rate_table[] = {
>> + PLL_35XX_RATE(24 * MHZ, 825000000, 275, 4, 1),
>> + PLL_35XX_RATE(24 * MHZ, 728000000, 182, 3, 1),
>> + PLL_35XX_RATE(24 * MHZ, 633000000, 211, 4, 1),
>> + PLL_35XX_RATE(24 * MHZ, 543000000, 181, 2, 2),
>> + PLL_35XX_RATE(24 * MHZ, 413000000, 413, 6, 2),
>> + PLL_35XX_RATE(24 * MHZ, 275000000, 275, 3, 3),
>> + PLL_35XX_RATE(24 * MHZ, 206000000, 206, 3, 3),
>> + PLL_35XX_RATE(24 * MHZ, 165000000, 110, 2, 3),
>> +};
>> +
>> static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = {
>> PLL_36XX_RATE(24 * MHZ, 600000000U, 100, 2, 1, 0),
>> PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0),
>> @@ -1473,7 +1484,7 @@ static void __init exynos5x_clk_init(struct device_node *np,
>> exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl;
>> exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl;
>> exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
>> - exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
>> + exynos5x_plls[bpll].rate_table = exynos5422_bpll_rate_table;
>> }
>>
>> samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls),
>>
>
>
Hi Krzysztof,
On 3/5/19 12:36 PM, Krzysztof Kozlowski wrote:
> On Tue, 5 Mar 2019 at 11:19, Lukasz Luba <[email protected]>
> wrote:>> Add description of Dynamic Memory Controller and PPMU
> counters.> They are used by exynos5422-dmc driver.>> Signed-off-by:
> Lukasz Luba <[email protected]>In previous email I asked to
> fix the subject prefix in case of resend. Please fix it.
>
>> ---
>> arch/arm/boot/dts/exynos5420.dtsi | 83 +++++++++++++++++++++++++
>> arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 87 +++++++++++++++++++++++++++
>> 2 files changed, 170 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
>> index aaff158..fc00fda 100644
>> --- a/arch/arm/boot/dts/exynos5420.dtsi
>> +++ b/arch/arm/boot/dts/exynos5420.dtsi
>> @@ -235,6 +235,41 @@
>> status = "disabled";
>> };
>>
>> + dmc: memory-controller@10c20000 {
>> + compatible = "samsung,exynos5422-dmc";
>> + reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>,
>> + <0x10000000 0x1000>;
>> + clocks = <&clock CLK_FOUT_SPLL>,
>> + <&clock CLK_MOUT_SCLK_SPLL>,
>> + <&clock CLK_FF_DOUT_SPLL2>,
>> + <&clock CLK_FOUT_BPLL>,
>> + <&clock CLK_MOUT_BPLL>,
>> + <&clock CLK_SCLK_BPLL>,
>> + <&clock CLK_MOUT_MX_MSPLL_CCORE>,
>> + <&clock CLK_MOUT_MX_MSPLL_CCORE_PHY>,
>> + <&clock CLK_MOUT_MCLK_CDREX>,
>> + <&clock CLK_DOUT_CLK2X_PHY0>,
>> + <&clock CLK_CLKM_PHY0>,
>> + <&clock CLK_CLKM_PHY1>,
>> + <&clock CLK_CDREX_PAUSE>,
>> + <&clock CLK_CDREX_TIMING_SET>;
>> + clock-names = "fout_spll",
>> + "mout_sclk_spll",
>> + "ff_dout_spll2",
>> + "fout_bpll",
>> + "mout_bpll",
>> + "sclk_bpll",
>> + "mout_mx_mspll_ccore",
>> + "mout_mx_mspll_ccore_phy",
>> + "mout_mclk_cdrex",
>> + "dout_clk2x_phy0",
>> + "clkm_phy0",
>> + "clkm_phy1",
>> + "clk_cdrex_pause",
>> + "clk_cdrex_timing_set";
>> + status = "disabled";
>> + };
>> +
>> nocp_mem0_0: nocp@10ca1000 {
>> compatible = "samsung,exynos5420-nocp";
>> reg = <0x10CA1000 0x200>;
>> @@ -271,6 +306,54 @@
>> status = "disabled";
>> };
>>
>> + ppmu_dmc0_0: ppmu@10d00000 {
>> + compatible = "samsung,exynos-ppmu";
>> + reg = <0x10d00000 0x2000>;
>> + clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;
>> + clock-names = "ppmu";
>> + events {
>> + ppmu_event_dmc0_0: ppmu-event3-dmc0_0 {
>> + event-name = "ppmu-event3-dmc0_0";
>> + };
>> + };
>> + };
>> +
>> + ppmu_dmc0_1: ppmu@10d10000 {
>> + compatible = "samsung,exynos-ppmu";
>> + reg = <0x10d10000 0x2000>;
>> + clocks = <&clock CLK_PCLK_PPMU_DREX0_1>;
>> + clock-names = "ppmu";
>> + events {
>> + ppmu_event_dmc0_1: ppmu-event3-dmc0_1 {
>> + event-name = "ppmu-event3-dmc0_1";
>> + };
>> + };
>> + };
>> +
>> + ppmu_dmc1_0: ppmu@10d10000 {
>> + compatible = "samsung,exynos-ppmu";
>> + reg = <0x10d60000 0x2000>;
>> + clocks = <&clock CLK_PCLK_PPMU_DREX1_0>;
>> + clock-names = "ppmu";
>> + events {
>> + ppmu_event_dmc1_0: ppmu-event3-dmc1_0 {
>> + event-name = "ppmu-event3-dmc1_0";
>> + };
>> + };
>> + };
>> +
>> + ppmu_dmc1_1: ppmu@10d70000 {
>> + compatible = "samsung,exynos-ppmu";
>> + reg = <0x10d70000 0x2000>;
>> + clocks = <&clock CLK_PCLK_PPMU_DREX1_1>;
>> + clock-names = "ppmu";
>> + events {
>> + ppmu_event_dmc1_1: ppmu-event3-dmc1_1 {
>> + event-name = "ppmu-event3-dmc1_1";
>> + };
>> + };
>> + };
>> +
>> gsc_pd: power-domain@10044000 {
>> compatible = "samsung,exynos4210-pd";
>> reg = <0x10044000 0x20>;
>> diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
>> index bf09eab..6b28fb3 100644
>> --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
>> +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
>> @@ -34,6 +34,69 @@
>> clock-frequency = <24000000>;
>> };
>> };
>> +
>> + dmc_opp_table: opp_table2 {
>> + compatible = "operating-points-v2";
>> +
>> + opp00 {
>> + opp-hz = /bits/ 64 <165000000>;
>> + opp-microvolt = <875000>;
>> + };
>> + opp01 {
>> + opp-hz = /bits/ 64 <206000000>;
>> + opp-microvolt = <875000>;
>> + };
>> + opp02 {
>> + opp-hz = /bits/ 64 <275000000>;
>> + opp-microvolt = <875000>;
>> + };
>> + opp03 {
>> + opp-hz = /bits/ 64 <413000000>;
>> + opp-microvolt = <887500>;
>> + };
>> + opp04 {
>> + opp-hz = /bits/ 64 <543000000>;
>> + opp-microvolt = <937500>;
>> + };
>> + opp05 {
>> + opp-hz = /bits/ 64 <633000000>;
>> + opp-microvolt = <1012500>;
>> + };
>> + opp06 {
>> + opp-hz = /bits/ 64 <728000000>;
>> + opp-microvolt = <1037500>;
>> + };
>> + opp07 {
>> + opp-hz = /bits/ 64 <825000000>;
>> + opp-microvolt = <1050000>;
>> + };
>> + };
>> +
>> + dmc_bypass_mode: bypass_mode {
>> + compatible = "samsung,dmc-bypass-mode";
>> +
>> + freq-hz = <400000000>;
>> + volt-uv = <887500>;
>> + dram-timing-row = <0x365a9713>;
>> + dram-timing-data = <0x4740085e>;
>> + dram-timing-power = <0x543a0446>;
>> + };
>> +
>> + dram_timing: timing {
>> + compatible = "samsung,dram-timing";
>> +
>> + dram-timing-names = "165MHz", "206MHz", "275MHz", "413MHz",
>> + "543MHz", "633MHz", "728MHz", "825MHz";
>> + dram-timing-row = <0x11223185>, <0x112331C6>, <0x12244287>,
>> + <0x1B35538A>, <0x244764CD>, <0x2A48758F>,
>> + <0x30598651>, <0x365A9713>;
>> + dram-timing-data = <0x2720085E>, <0x2720085E>, <0x2720085E>,
>> + <0x2720085E>, <0x3730085E>, <0x3730085E>,
>> + <0x3730085E>, <0x4740085E>;
>> + dram-timing-power = <0x140C0225>, <0x180F0225>, <0x1C140225>,
>> + <0x2C1D0225>, <0x38270335>, <0x402D0335>,
>> + <0x4C330336>, <0x543A0446>;
>> + };
>> };
>>
>> &bus_wcore {
>> @@ -127,6 +190,14 @@
>> cpu-supply = <&buck2_reg>;
>> };
>>
>> +&dmc {
>> + devfreq-events = <&ppmu_dmc0_0>, <&ppmu_dmc0_1>,
>> + <&ppmu_dmc1_0>, <&ppmu_dmc1_1>;
>> +
>> + operating-points-v2 = <&dmc_opp_table>;
>
> The opp-tables have voltage entry but I do not see the regulator
> supply. How do you change the voltage?
Right. There is a missing entry in &dmc node
vdd-supply = <&buck1_reg>;
In the driver code it is taken by name "vdd_mif".
Regards,
Lukasz
>
> Best regards,
> Krzysztof
>
>
Hi Krzysztof,
On 3/5/19 12:35 PM, Krzysztof Kozlowski wrote:
> On Tue, 5 Mar 2019 at 11:19, Lukasz Luba <[email protected]> wrote:
>>
>> The patch adds description for DT binding for a new Exynos5422 Dynamic
>> Memory Controller device.
>>
>> Signed-off-by: Lukasz Luba <[email protected]>
>> ---
>> .../devicetree/bindings/devfreq/exynos5422-dmc.txt | 177 +++++++++++++++++++++
>> 1 file changed, 177 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/devfreq/exynos5422-dmc.txt
>>
>> diff --git a/Documentation/devicetree/bindings/devfreq/exynos5422-dmc.txt b/Documentation/devicetree/bindings/devfreq/exynos5422-dmc.txt
>> new file mode 100644
>> index 0000000..0e73e98
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/devfreq/exynos5422-dmc.txt
>> @@ -0,0 +1,177 @@
>> +* Exynos5422 frequency and voltage scaling for Dynamic Memory Controller device
>> +
>> +The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the DRAM
>> +memory chips are connected. The driver is to monitor the controller in runtime
>> +and switch frequency and voltage. To monitor the usage of the controller in
>> +runtime, the driver uses the PPMU (Platform Performance Monitoring Unit), which
>> +is able to measure the current load of the memory.
>> +When 'userspace' governor is used for the driver, an application is able to
>> +switch the DMC frequency.
>> +
>> +Required properties for DMC device for Exynos5422:
>> +- compatible: Should be "samsung,exynos5422-bus".
>> +- clock-names : the name of clock used by the bus, "bus".
>> +- clocks : phandles for clock specified in "clock-names" property.
>> +- devfreq-events : phandles for PPMU devices connected to this DMC.
>> +
>> +The example definition of a DMC and PPMU devices declared in DT is shown below:
>> +
>> + ppmu_dmc0_0: ppmu@10d00000 {
>> + compatible = "samsung,exynos-ppmu";
>> + reg = <0x10d00000 0x2000>;
>> + clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;
>> + clock-names = "ppmu";
>> + status = "okay";
>> + events {
>> + ppmu_event_dmc0_0: ppmu-event3-dmc0_0 {
>> + event-name = "ppmu-event3-dmc0_0";
>> + };
>> + };
>> + };
>> +
>> +
>> + ppmu_dmc0_1: ppmu@10d10000 {
>> + compatible = "samsung,exynos-ppmu";
>> + reg = <0x10d10000 0x2000>;
>> + clocks = <&clock CLK_PCLK_PPMU_DREX0_1>;
>> + clock-names = "ppmu";
>> + status = "okay";
>> + events {
>> + ppmu_event_dmc0_1: ppmu-event3-dmc0_1 {
>> + event-name = "ppmu-event3-dmc0_1";
>> + };
>> + };
>> + };
>> +
>> + ppmu_dmc1_0: ppmu@10d10000 {
>> + compatible = "samsung,exynos-ppmu";
>> + reg = <0x10d60000 0x2000>;
>> + clocks = <&clock CLK_PCLK_PPMU_DREX1_0>;
>> + clock-names = "ppmu";
>> + status = "okay";
>> + events {
>> + ppmu_event_dmc1_0: ppmu-event3-dmc1_0 {
>> + event-name = "ppmu-event3-dmc1_0";
>> + };
>> + };
>> + };
>> +
>> + ppmu_dmc1_1: ppmu@10d70000 {
>> + compatible = "samsung,exynos-ppmu";
>> + reg = <0x10d70000 0x2000>;
>> + clocks = <&clock CLK_PCLK_PPMU_DREX1_1>;
>> + clock-names = "ppmu";
>> + status = "okay";
>> + events {
>> + ppmu_event_dmc1_1: ppmu-event3-dmc1_1 {
>> + event-name = "ppmu-event3-dmc1_1";
>> + };
>> + };
>> + };
>> +
>> + dmc: memory-controller@10c20000 {
>> + compatible = "samsung,exynos5422-dmc";
>> + reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>,
>> + <0x10000000 0x1000>;
>> + clocks = <&clock CLK_FOUT_SPLL>,
>> + <&clock CLK_MOUT_SCLK_SPLL>,
>> + <&clock CLK_FF_DOUT_SPLL2>,
>> + <&clock CLK_FOUT_BPLL>,
>> + <&clock CLK_MOUT_BPLL>,
>> + <&clock CLK_SCLK_BPLL>,
>> + <&clock CLK_MOUT_MX_MSPLL_CCORE>,
>> + <&clock CLK_MOUT_MX_MSPLL_CCORE_PHY>,
>> + <&clock CLK_MOUT_MCLK_CDREX>,
>> + <&clock CLK_DOUT_CLK2X_PHY0>,
>> + <&clock CLK_CLKM_PHY0>,
>> + <&clock CLK_CLKM_PHY1>,
>> + <&clock CLK_CDREX_PAUSE>,
>> + <&clock CLK_CDREX_TIMING_SET>;
>> + clock-names = "fout_spll",
>> + "mout_sclk_spll",
>> + "ff_dout_spll2",
>> + "fout_bpll",
>> + "mout_bpll",
>> + "sclk_bpll",
>> + "mout_mx_mspll_ccore",
>> + "mout_mx_mspll_ccore_phy",
>> + "mout_mclk_cdrex",
>> + "dout_clk2x_phy0",
>> + "clkm_phy0",
>> + "clkm_phy1",
>> + "clk_cdrex_pause",
>> + "clk_cdrex_timing_set";
>> + status = "okay";
>> + operating-points-v2 = <&dmc_opp_table>;
>> + devfreq-events = <&ppmu_dmc0_0>, <&ppmu_dmc0_1>,
>> + <&ppmu_dmc1_0>, <&ppmu_dmc1_1>;
>> + };
>> +
>> +The needed timings of DRAM memory are stored in dedicated nodes.
>> +There are two nodes with regular timings and for bypass mode.
>> +
>> + dmc_bypass_mode: bypass_mode {
>> + compatible = "samsung,dmc-bypass-mode";
>
> This looks like an example, not bindings.
I have not seen similar, since it is not just 'timing' but other
Exynos register specific stuff in the register.
>
>> +
>> + freq-hz = <400000000>;
>> + volt-uv = <887500>;
>
> -microvolt
> Documentation/devicetree/bindings/property-units.txt
Thanks
>
>> + dram-timing-row = <0x365a9713>;
>> + dram-timing-data = <0x4740085e>;
>> + dram-timing-power = <0x543a0446>;
>> + };
>> +
>> + dram_timing: timing {
>> + compatible = "samsung,dram-timing";
>
> Probably you should use timings from Documentation/devicetree/bindings/lpddr2/
> If not, all the fields below should be described.
It is not just 'timing'. It is a whole register specific value for the
Exynos5422. It could be named 'dram-config-regs' to avoid confusion.
The regs are called 'row', 'data' and 'power' and adding a procedure
in the driver which takes ~30 values for each speed-grade and combines
into a reg value makes no sense.
>
> All these bindings (memory-controller, timings) look like description
> of memory controller so maybe they should go into
> Documentation/devicetree/bindings/memory-controllers ?
I don't know, maybe Chanwoo has some opinion since he requested to put
these register values into DT.
Regards,
Lukasz
>
> Best regards,
> Krzysztof
>
>> +
>> + dram-timing-names = "165MHz", "206MHz", "275MHz", "413MHz",
>> + "543MHz", "633MHz", "728MHz", "825MHz";
>> + dram-timing-row = <0x11223185>, <0x112331C6>, <0x12244287>,
>> + <0x1B35538A>, <0x244764CD>, <0x2A48758F>,
>> + <0x30598651>, <0x365A9713>;
>> + dram-timing-data = <0x2720085E>, <0x2720085E>, <0x2720085E>,
>> + <0x2720085E>, <0x3730085E>, <0x3730085E>,
>> + <0x3730085E>, <0x4740085E>;
>> + dram-timing-power = <0x140C0225>, <0x180F0225>, <0x1C140225>,
>> + <0x2C1D0225>, <0x38270335>, <0x402D0335>,
>> + <0x4C330336>, <0x543A0446>;
>> + };
>> +
>> +The frequencies supported by the DMC are stored in OPP table v2.
>> +
>> + dmc_opp_table: opp_table2 {
>> + compatible = "operating-points-v2";
>> +
>> + opp00 {
>> + opp-hz = /bits/ 64 <165000000>;
>> + opp-microvolt = <875000>;
>> + };
>> + opp01 {
>> + opp-hz = /bits/ 64 <206000000>;
>> + opp-microvolt = <875000>;
>> + };
>> + opp02 {
>> + opp-hz = /bits/ 64 <275000000>;
>> + opp-microvolt = <875000>;
>> + };
>> + opp03 {
>> + opp-hz = /bits/ 64 <413000000>;
>> + opp-microvolt = <887500>;
>> + };
>> + opp04 {
>> + opp-hz = /bits/ 64 <543000000>;
>> + opp-microvolt = <937500>;
>> + };
>> + opp05 {
>> + opp-hz = /bits/ 64 <633000000>;
>> + opp-microvolt = <1012500>;
>> + };
>> + opp06 {
>> + opp-hz = /bits/ 64 <728000000>;
>> + opp-microvolt = <1037500>;
>> + };
>> + opp07 {
>> + opp-hz = /bits/ 64 <825000000>;
>> + opp-microvolt = <1050000>;
>> + };
>> + };
>> +
>> --
>> 2.7.4
>>
>
>
Hi Lukasz,
On 19. 3. 6. 오후 4:14, Lukasz Luba wrote:
> Hi Chanwoo,
>
> On 3/6/19 5:18 AM, Chanwoo Choi wrote:
>> Hi Lukasz,
>>
>> On 19. 3. 5. 오후 7:19, Lukasz Luba wrote:
>>> The patch adds description for DT binding for a new Exynos5422 Dynamic
>>> Memory Controller device.
>>>
>>> Signed-off-by: Lukasz Luba <[email protected]>
>>> ---
>>> .../devicetree/bindings/devfreq/exynos5422-dmc.txt | 177 +++++++++++++++++++++
>>> 1 file changed, 177 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/devfreq/exynos5422-dmc.txt
>>>
>>> diff --git a/Documentation/devicetree/bindings/devfreq/exynos5422-dmc.txt b/Documentation/devicetree/bindings/devfreq/exynos5422-dmc.txt
>>> new file mode 100644
>>> index 0000000..0e73e98
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/devfreq/exynos5422-dmc.txt
>>> @@ -0,0 +1,177 @@
>>> +* Exynos5422 frequency and voltage scaling for Dynamic Memory Controller device
>>> +
>>> +The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the DRAM
>>> +memory chips are connected. The driver is to monitor the controller in runtime
>>> +and switch frequency and voltage. To monitor the usage of the controller in
>>> +runtime, the driver uses the PPMU (Platform Performance Monitoring Unit), which
>>> +is able to measure the current load of the memory.
>>> +When 'userspace' governor is used for the driver, an application is able to
>>> +switch the DMC frequency.
>>> +
>>> +Required properties for DMC device for Exynos5422:
>>> +- compatible: Should be "samsung,exynos5422-bus".
>>> +- clock-names : the name of clock used by the bus, "bus".
>>> +- clocks : phandles for clock specified in "clock-names" property.
>>> +- devfreq-events : phandles for PPMU devices connected to this DMC.
>>
>>
>> I already replied with following comments on v4 patch[1].
>> But, you didn't reply anything. We can reduce the duplicate
>> review by keeping the basic review rule.
> I have lost these changes while I was adding the OPPs, timings into the
> dt-binding.
>>
>> - Re: [PATCH v4 5/8] dt-bindings: devfreq: add Exynos5422 DMC device description
>> [1] https://do-db2.lkml.org/lkml/2019/2/3/64
>>
>>
>> [Following comments were replied on v4 patch[1]]
>>
>>> +- compatible: Should be "samsung,exynos5422-bus".
>>
>> The compatible name is wrong.
>> - exynos5422-bus -> exynos5422-dmc
>>
>>> +- clock-names : the name of clock used by the bus, "bus".
>>
>> 'bus' is right?
> right
As I knew, the clocks of exynos5422-dmc is for DMC.
Why do you think 'bus' is right insted of DMC?.
I think that it is not a 'bus' driver.
>>
>>> +- clocks : phandles for clock specified in "clock-names" property.
>>> +- devfreq-events : phandles for PPMU devices connected to this DMC.
>>
>> The dt-binging file doesn't contain the any description for 'reg' properties.
> There are 3 regs: cdrex0, cdrex1, chip_id. I will add this description.
>
> The patch set has this OPPs and timings coming from DT as you requested
> but I am not sure if it is in the right place in the DT.
> Thus dt-binding you may consider as 'in-progress' till the DT entries
> are fixed
>
> Regards,
> Lukasz
>>
>>
>>
>>> +
>>> +The example definition of a DMC and PPMU devices declared in DT is shown below:
>>> +
>>> + ppmu_dmc0_0: ppmu@10d00000 {
>>> + compatible = "samsung,exynos-ppmu";
>>> + reg = <0x10d00000 0x2000>;
>>> + clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;
>>> + clock-names = "ppmu";
>>> + status = "okay";
>>> + events {
>>> + ppmu_event_dmc0_0: ppmu-event3-dmc0_0 {
>>> + event-name = "ppmu-event3-dmc0_0";
>>> + };
>>> + };
>>> + };
>>> +
>>> +
>>> + ppmu_dmc0_1: ppmu@10d10000 {
>>> + compatible = "samsung,exynos-ppmu";
>>> + reg = <0x10d10000 0x2000>;
>>> + clocks = <&clock CLK_PCLK_PPMU_DREX0_1>;
>>> + clock-names = "ppmu";
>>> + status = "okay";
>>> + events {
>>> + ppmu_event_dmc0_1: ppmu-event3-dmc0_1 {
>>> + event-name = "ppmu-event3-dmc0_1";
>>> + };
>>> + };
>>> + };
>>> +
>>> + ppmu_dmc1_0: ppmu@10d10000 {
>>> + compatible = "samsung,exynos-ppmu";
>>> + reg = <0x10d60000 0x2000>;
>>> + clocks = <&clock CLK_PCLK_PPMU_DREX1_0>;
>>> + clock-names = "ppmu";
>>> + status = "okay";
>>> + events {
>>> + ppmu_event_dmc1_0: ppmu-event3-dmc1_0 {
>>> + event-name = "ppmu-event3-dmc1_0";
>>> + };
>>> + };
>>> + };
>>> +
>>> + ppmu_dmc1_1: ppmu@10d70000 {
>>> + compatible = "samsung,exynos-ppmu";
>>> + reg = <0x10d70000 0x2000>;
>>> + clocks = <&clock CLK_PCLK_PPMU_DREX1_1>;
>>> + clock-names = "ppmu";
>>> + status = "okay";
>>> + events {
>>> + ppmu_event_dmc1_1: ppmu-event3-dmc1_1 {
>>> + event-name = "ppmu-event3-dmc1_1";
>>> + };
>>> + };
>>> + };
>>> +
>>> + dmc: memory-controller@10c20000 {
>>> + compatible = "samsung,exynos5422-dmc";
>>> + reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>,
>>> + <0x10000000 0x1000>;
>>> + clocks = <&clock CLK_FOUT_SPLL>,
>>> + <&clock CLK_MOUT_SCLK_SPLL>,
>>> + <&clock CLK_FF_DOUT_SPLL2>,
>>> + <&clock CLK_FOUT_BPLL>,
>>> + <&clock CLK_MOUT_BPLL>,
>>> + <&clock CLK_SCLK_BPLL>,
>>> + <&clock CLK_MOUT_MX_MSPLL_CCORE>,
>>> + <&clock CLK_MOUT_MX_MSPLL_CCORE_PHY>,
>>> + <&clock CLK_MOUT_MCLK_CDREX>,
>>> + <&clock CLK_DOUT_CLK2X_PHY0>,
>>> + <&clock CLK_CLKM_PHY0>,
>>> + <&clock CLK_CLKM_PHY1>,
>>> + <&clock CLK_CDREX_PAUSE>,
>>> + <&clock CLK_CDREX_TIMING_SET>;
>>> + clock-names = "fout_spll",
>>> + "mout_sclk_spll",
>>> + "ff_dout_spll2",
>>> + "fout_bpll",
>>> + "mout_bpll",
>>> + "sclk_bpll",
>>> + "mout_mx_mspll_ccore",
>>> + "mout_mx_mspll_ccore_phy",
>>> + "mout_mclk_cdrex",
>>> + "dout_clk2x_phy0",
>>> + "clkm_phy0",
>>> + "clkm_phy1",
>>> + "clk_cdrex_pause",
>>> + "clk_cdrex_timing_set";
>>> + status = "okay";
>>> + operating-points-v2 = <&dmc_opp_table>;
>>> + devfreq-events = <&ppmu_dmc0_0>, <&ppmu_dmc0_1>,
>>> + <&ppmu_dmc1_0>, <&ppmu_dmc1_1>;
>>> + };
>>> +
>>> +The needed timings of DRAM memory are stored in dedicated nodes.
>>> +There are two nodes with regular timings and for bypass mode.
>>> +
>>> + dmc_bypass_mode: bypass_mode {
>>> + compatible = "samsung,dmc-bypass-mode";
>>> +
>>> + freq-hz = <400000000>;
>>> + volt-uv = <887500>;
>>> + dram-timing-row = <0x365a9713>;
>>> + dram-timing-data = <0x4740085e>;
>>> + dram-timing-power = <0x543a0446>;
>>> + };
>>> +
>>> + dram_timing: timing {
>>> + compatible = "samsung,dram-timing";
>>> +
>>> + dram-timing-names = "165MHz", "206MHz", "275MHz", "413MHz",
>>> + "543MHz", "633MHz", "728MHz", "825MHz";
>>> + dram-timing-row = <0x11223185>, <0x112331C6>, <0x12244287>,
>>> + <0x1B35538A>, <0x244764CD>, <0x2A48758F>,
>>> + <0x30598651>, <0x365A9713>;
>>> + dram-timing-data = <0x2720085E>, <0x2720085E>, <0x2720085E>,
>>> + <0x2720085E>, <0x3730085E>, <0x3730085E>,
>>> + <0x3730085E>, <0x4740085E>;
>>> + dram-timing-power = <0x140C0225>, <0x180F0225>, <0x1C140225>,
>>> + <0x2C1D0225>, <0x38270335>, <0x402D0335>,
>>> + <0x4C330336>, <0x543A0446>;
>>> + };
>>> +
>>> +The frequencies supported by the DMC are stored in OPP table v2.
>>> +
>>> + dmc_opp_table: opp_table2 {
>>> + compatible = "operating-points-v2";
>>> +
>>> + opp00 {
>>> + opp-hz = /bits/ 64 <165000000>;
>>> + opp-microvolt = <875000>;
>>> + };
>>> + opp01 {
>>> + opp-hz = /bits/ 64 <206000000>;
>>> + opp-microvolt = <875000>;
>>> + };
>>> + opp02 {
>>> + opp-hz = /bits/ 64 <275000000>;
>>> + opp-microvolt = <875000>;
>>> + };
>>> + opp03 {
>>> + opp-hz = /bits/ 64 <413000000>;
>>> + opp-microvolt = <887500>;
>>> + };
>>> + opp04 {
>>> + opp-hz = /bits/ 64 <543000000>;
>>> + opp-microvolt = <937500>;
>>> + };
>>> + opp05 {
>>> + opp-hz = /bits/ 64 <633000000>;
>>> + opp-microvolt = <1012500>;
>>> + };
>>> + opp06 {
>>> + opp-hz = /bits/ 64 <728000000>;
>>> + opp-microvolt = <1037500>;
>>> + };
>>> + opp07 {
>>> + opp-hz = /bits/ 64 <825000000>;
>>> + opp-microvolt = <1050000>;
>>> + };
>>> + };
>>> +
>>>
>>
>>
>
>
--
Best Regards,
Chanwoo Choi
Samsung Electronics
Hi Lukasz,
As you knew, I replied the comments on v4 patch[1].
But, this patch does apply some comments from me
and some comments doesn't not applied.
My comments may not be always right. But, If you pick up some comments
and drop the some comments without discussion, it makes the confusion
for the review.
So, on v4 patch[1], please reply why do you agree some comments
and disagree some comments.
- [v4,4/8] drivers: devfreq: add DMC driver for Exynos542
[1] https://patchwork.kernel.org/patch/10793297/
On 19. 3. 5. 오후 7:19, Lukasz Luba wrote:
> This patch adds driver for Exynos5422 Dynamic Memory Controller.
> The driver provides support for dynamic frequency and voltage scaling for
> DMC and DRAM. It supports changing timings of DRAM running with different
> frequency.
> The patch also contains needed MAINTAINERS file update.
>
> Signed-off-by: Lukasz Luba <[email protected]>
> ---
> MAINTAINERS | 8 +
> drivers/devfreq/Kconfig | 13 +
> drivers/devfreq/Makefile | 1 +
> drivers/devfreq/exynos5422-dmc.c | 1154 ++++++++++++++++++++++++++++++++++++++
> 4 files changed, 1176 insertions(+)
> create mode 100644 drivers/devfreq/exynos5422-dmc.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index dce5c09..e20172b 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -3323,6 +3323,14 @@ S: Maintained
> F: drivers/devfreq/exynos-bus.c
> F: Documentation/devicetree/bindings/devfreq/exynos-bus.txt
>
> +DMC FREQUENCY DRIVER FOR SAMSUNG EXYNOS5422
> +M: Lukasz Luba <[email protected]>
> +L: [email protected]
> +L: [email protected]
> +S: Maintained
> +F: drivers/devfreq/exynos5422-dmc.c
> +F: Documentation/devicetree/bindings/devfreq/exynos5422-dmc.txt
> +
> BUSLOGIC SCSI DRIVER
> M: Khalid Aziz <[email protected]>
> L: [email protected]
> diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
> index 6a172d3..a476477 100644
> --- a/drivers/devfreq/Kconfig
> +++ b/drivers/devfreq/Kconfig
> @@ -113,6 +113,19 @@ config ARM_RK3399_DMC_DEVFREQ
> It sets the frequency for the memory controller and reads the usage counts
> from hardware.
>
> +config ARM_EXYNOS5422_DMC_DEVFREQ
> + tristate "ARM EXYNOS5422 DMC DEVFREQ Driver"
> + depends on ARCH_EXYNOS || COMPILE_TEST
> + select DEVFREQ_GOV_SIMPLE_ONDEMAND
> + select DEVFREQ_GOV_USERSPACE
> + select PM_DEVFREQ_EVENT
> + select PM_OPP
> + help
> + This adds DEVFREQ driver for Exynos5422 DMC (Dynamic Memory Controller).
> + The driver provides support for Dynamic Voltage and Frequency Scaling in
> + DMC and DRAM. It also supports changing timings of DRAM running with
> + different frequency.
> +
> source "drivers/devfreq/event/Kconfig"
>
> endif # PM_DEVFREQ
> diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile
> index 32b8d4d..e3620ff 100644
> --- a/drivers/devfreq/Makefile
> +++ b/drivers/devfreq/Makefile
> @@ -9,6 +9,7 @@ obj-$(CONFIG_DEVFREQ_GOV_PASSIVE) += governor_passive.o
>
> # DEVFREQ Drivers
> obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ) += exynos-bus.o
> +obj-$(CONFIG_ARM_EXYNOS5422_DMC_DEVFREQ) += exynos5422-dmc.o
> obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o
> obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra-devfreq.o
>
> diff --git a/drivers/devfreq/exynos5422-dmc.c b/drivers/devfreq/exynos5422-dmc.c
> new file mode 100644
> index 0000000..0505a99
> --- /dev/null
> +++ b/drivers/devfreq/exynos5422-dmc.c
> @@ -0,0 +1,1154 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2019 Samsung Electronics Co., Ltd.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/devfreq.h>
> +#include <linux/devfreq-event.h>
> +#include <linux/device.h>
> +#include <linux/export.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/pm_opp.h>
> +#include <linux/platform_device.h>
> +#include <linux/regulator/consumer.h>
> +#include <linux/slab.h>
> +
> +#define EXYNOS5_DREXI_TIMINGAREF (0x0030)
> +#define EXYNOS5_DREXI_TIMINGROW0 (0x0034)
> +#define EXYNOS5_DREXI_TIMINGDATA0 (0x0038)
> +#define EXYNOS5_DREXI_TIMINGPOWER0 (0x003C)
> +#define EXYNOS5_DREXI_TIMINGROW1 (0x00E4)
> +#define EXYNOS5_DREXI_TIMINGDATA1 (0x00E8)
> +#define EXYNOS5_DREXI_TIMINGPOWER1 (0x00EC)
> +
> +#define EXYNOS5_AREF_NORMAL (0x2e)
> +
> +#define IS_MEM_2GB(val) \
> + ( \
> + (((val) & 0xf0) & 0x20) ? 1 : \
> + (((val) & 0xf0) & 0x30) ? 1 : 0 \
> + )
> +
> +#define EXYNOS5_POP_OPTIONS(val) (((val >> 4) & 0x3UL) << 4)
> +#define EXYNOS5_DDR_TYPE(val) (((val >> 14) & 0x1UL))
> +
> +#define EXYNOS5_CHIP_PROD_ID (0)
> +#define EXYNOS5_CHIP_PKG_ID (4)
> +
> +#define PPMU_PMCNT_CONST_RATIO_MUL 15
> +#define PPMU_PMCNT_CONST_RATIO_DIV 10
> +
> +/**
> + * enum dmc_slot_id - An enum with slots in DMC
> + */
> +enum dmc_slot_id {
> + DMC0_0,
> + DMC0_1,
> + DMC1_0,
> + DMC1_1,
> + DMC_SLOTS_END
> +};
> +
> +/**
> + * struct dmc_slot_info - Describes DMC's slot
> + *
> + * The structure holds DMC's slot name which is part of the device name
> + * provided in DT. Each slot has particular share of the DMC bandwidth.
> + * To abstract the model performance and values in performance counters,
> + * fields 'ratio_mul' and 'ratio_div' are used in calculation algorithm
> + * for each slot. Please check the corresponding function with the algorithm,
> + * to see how these variables are used.
> + */
> +struct dmc_slot_info {
> + char *name;
> + int id;
> + int ratio_mul;
> + int ratio_div;
> +};
> +
> +/**
> + * struct dmc_opp_table - Operating level desciption
> + *
> + * Covers frequency and voltage settings of the DMC operating mode.
> + */
> +struct dmc_opp_table {
> + u32 freq_hz;
> + u32 volt_uv;
> +};
> +
> +/**
> + * struct exynos5_dmc - main structure describing DMC device
> + *
> + * The main structure for the Dynamic Memory Controller which covers clocks,
> + * memory regions, HW information, parameters and current operating mode.
> + */
> +struct exynos5_dmc {
> + struct device *dev;
> + struct devfreq *df;
> + struct devfreq_simple_ondemand_data gov_data;
> + void __iomem *base_drexi0;
> + void __iomem *base_drexi1;
> + void __iomem *chip_id;
> + struct mutex lock;
> + unsigned long curr_rate;
> + unsigned long curr_volt;
> + struct dmc_opp_table *opp;
> + struct dmc_opp_table opp_bypass;
> + int opp_count;
> + u32 *timing_row;
> + u32 *timing_data;
> + u32 *timing_power;
> + u32 bypass_timing_row;
> + u32 bypass_timing_data;
> + u32 bypass_timing_power;
> + unsigned int prod_rev;
> + unsigned int pkg_rev;
> + unsigned int mem_info;
> + struct regulator *vdd_mif;
> + struct clk *fout_spll;
> + struct clk *fout_bpll;
> + struct clk *mout_spll;
> + struct clk *mout_bpll;
> + struct clk *mout_mclk_cdrex;
> + struct clk *dout_clk2x_phy0;
> + struct clk *mout_mx_mspll_ccore;
> + struct clk *mx_mspll_ccore_phy;
> + struct clk *mout_mx_mspll_ccore_phy;
> + struct clk *cdrex_pause;
> + struct clk *timing_set;
> + struct devfreq_event_dev **counter;
> + int num_counters;
> + bool counters_enabled;
> +};
> +
> +/**
> + * exynos5_counters_fname() - Macro generating function for event devices
> + * @f: function name suffix
> + *
> + * Macro which generates needed function for manipulation of event devices.
> + * It aims to avoid code duplication relaying on similar prefix and function
> + * parameters in the devfreq event device framework functions.
> + */
> +#define exynos5_counters_fname(f) \
> +static int exynos5_counters_##f(struct exynos5_dmc *dmc) \
> +{ \
> + int i, ret; \
> + \
> + for (i = 0; i < dmc->num_counters; i++) { \
> + if (!dmc->counter[i]) \
> + continue; \
> + ret = devfreq_event_##f(dmc->counter[i]); \
> + if (ret < 0) \
> + return ret; \
> + } \
> + return 0; \
> +}
> +exynos5_counters_fname(set_event);
> +exynos5_counters_fname(enable_edev);
> +exynos5_counters_fname(disable_edev);
> +
> +/**
> + * dmc_slot - An array which holds DMC's slots information
> + *
> + * The array is used in algorithm calculating slots performance and usage
> + * based on performance counters' values. The values i.e. 15/10=1.5 correspond
> + * to slot share in the DMC channel, which has 2.0 abstract width.
> + */
> +static const struct dmc_slot_info dmc_slot[] = {
> + {"dmc0_0", DMC0_0, 15, 10},
> + {"dmc0_1", DMC0_1, 5, 10},
> + {"dmc1_0", DMC1_0, 10, 10},
> + {"dmc1_1", DMC1_0, 10, 10},
> +};
> +
> +/**
> + * find_target_freq_id() - Finds requested frequency in local DMC configuration
> + * @dmc: device for which the information is checked
> + * @target_rate: requested frequency in KHz
> + *
> + * Seeks in the local DMC driver structure for the requested frequency value
> + * and returns index or error value.
> + */
> +static int find_target_freq_idx(struct exynos5_dmc *dmc,
> + unsigned long target_rate)
> +{
> + int i;
> +
> + for (i = dmc->opp_count - 1; i >= 0; i--)
> + if (dmc->opp[i].freq_hz <= target_rate)
> + return i;
> +
> + return -EINVAL;
> +}
> +
> +/**
> + * exynos5_dmc_chip_revision_settings() - Chooses proper DMC's configuration
> + * @dmc: device for which is going to be checked and configured
> + *
> + * Function checks the HW product information in order to choose proper
> + * configuration for DMC frequency, voltage and DRAM timings.
> + */
> +static int exynos5_dmc_chip_revision_settings(struct exynos5_dmc *dmc)
> +{
> + unsigned int val;
> +
> + val = readl(dmc->chip_id + EXYNOS5_CHIP_PROD_ID);
> + dmc->prod_rev = val;
> +
> + val = readl(dmc->chip_id + EXYNOS5_CHIP_PKG_ID);
> + dmc->pkg_rev = val;
> +
> + dmc->mem_info = EXYNOS5_POP_OPTIONS(val);
> + dmc->mem_info |= EXYNOS5_DDR_TYPE(val);
> +
> + if (!IS_MEM_2GB(dmc->mem_info)) {
> + dev_warn(dmc->dev, "DRAM memory type not supported\n");
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +/**
> + * exynos5_init_freq_table() - Initialized PM OPP framework
> + * @dev: devfreq device for which the OPP table is going to be
> + * initialized
> + * @dmc: DMC device for which the frequencies are used for OPP init
> + * @profile: devfreq device's profile
> + *
> + * Populate the devfreq device's OPP table based on current frequency, voltage.
> + */
> +static int exynos5_init_freq_table(struct device *dev, struct exynos5_dmc *dmc,
> + struct devfreq_dev_profile *profile)
> +{
> + int i, ret;
> + int idx;
> + unsigned long freq;
> +
> + ret = dev_pm_opp_of_add_table(dev);
> + if (ret < 0) {
> + dev_err(dev, "Failed to get OPP table\n");
> + return ret;
> + }
> +
> + dmc->opp_count = dev_pm_opp_get_opp_count(dev);
> +
> + dmc->opp = devm_kmalloc_array(dmc->dev, dmc->opp_count,
> + sizeof(struct dmc_opp_table), GFP_KERNEL);
> + if (!dmc->opp)
> + goto err_opp;
> +
> + idx = dmc->opp_count - 1;
> + for (i = 0, freq = ULONG_MAX; i < dmc->opp_count; i++, freq--) {
> + struct dev_pm_opp *opp;
> +
> + opp = dev_pm_opp_find_freq_floor(dev, &freq);
> + if (IS_ERR(opp))
> + goto err_free_tables;
> +
> + dmc->opp[idx - i].freq_hz = freq;
> + dmc->opp[idx - i].volt_uv = dev_pm_opp_get_voltage(opp);
> +
> + dev_pm_opp_put(opp);
> + }
> +
> + return 0;
> +
> +err_free_tables:
> + kfree(dmc->opp);
> +err_opp:
> + dev_pm_opp_of_remove_table(dev);
> +
> + return -EINVAL;
> +}
> +
> +/**
> + * exynos5_set_bypass_dram_timings() - Low-level changes of the DRAM timings
> + * @dmc: device for which the new settings is going to be applied
> + * @param: DRAM parameters which passes timing data
> + *
> + * Low-level function for changing timings for DRAM memory clocking from
> + * 'bypass' clock source (fixed frequency @400MHz).
> + * It uses timing bank registers set 1.
> + */
> +static void exynos5_set_bypass_dram_timings(struct exynos5_dmc *dmc)
> +{
> + writel(EXYNOS5_AREF_NORMAL,
> + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGAREF);
> +
> + writel(dmc->bypass_timing_row,
> + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGROW1);
> + writel(dmc->bypass_timing_row,
> + dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGROW1);
> + writel(dmc->bypass_timing_data,
> + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGDATA1);
> + writel(dmc->bypass_timing_data,
> + dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGDATA1);
> + writel(dmc->bypass_timing_power,
> + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGPOWER1);
> + writel(dmc->bypass_timing_power,
> + dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGPOWER1);
> +}
> +
> +/**
> + * exynos5_dram_change_timings() - Low-level changes of the DRAM final timings
> + * @dmc: device for which the new settings is going to be applied
> + * @target_rate: target frequency of the DMC
> + *
> + * Low-level function for changing timings for DRAM memory operating from main
> + * clock source (BPLL), which can have different frequencies. Thus, each
> + * frequency must have corresponding timings register values in order to keep
> + * the needed delays.
> + * It uses timing bank registers set 0.
> + */
> +static int exynos5_dram_change_timings(struct exynos5_dmc *dmc,
> + unsigned long target_rate)
> +{
> + int idx;
> +
> + for (idx = dmc->opp_count - 1; idx >= 0; idx--)
> + if (dmc->opp[idx].freq_hz <= target_rate)
> + break;
> +
> + if (idx < 0)
> + return -EINVAL;
> +
> + writel(EXYNOS5_AREF_NORMAL,
> + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGAREF);
> +
> + writel(dmc->timing_row[idx],
> + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGROW0);
> + writel(dmc->timing_row[idx],
> + dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGROW0);
> + writel(dmc->timing_data[idx],
> + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGDATA0);
> + writel(dmc->timing_data[idx],
> + dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGDATA0);
> + writel(dmc->timing_power[idx],
> + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGPOWER0);
> + writel(dmc->timing_power[idx],
> + dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGPOWER0);
> +
> + return 0;
> +}
> +
> +/**
> + * exynos5_dmc_align_target_voltage() - Sets the final voltage for the DMC
> + * @dmc: device for which it is going to be set
> + * @target_volt: new voltage which is chosen to be final
> + *
> + * Function tries to align voltage to the safe level for 'normal' mode.
> + * It checks the need of higher voltage and changes the value. The target
> + * voltage might be lower that currently set and still the system will be
> + * stable.
> + */
> +static int exynos5_dmc_align_target_voltage(struct exynos5_dmc *dmc,
> + unsigned long target_volt)
> +{
> + int ret = 0;
> +
> + if (dmc->curr_volt > target_volt) {
> + ret = regulator_set_voltage(dmc->vdd_mif, target_volt,
> + target_volt);
> + if (!ret)
> + dmc->curr_volt = target_volt;
> + }
> +
> + return ret;
> +}
> +
> +/**
> + * exynos5_dmc_align_bypass_voltage() - Sets the voltage for the DMC
> + * @dmc: device for which it is going to be set
> + * @target_volt: new voltage which is chosen to be final
> + *
> + * Function tries to align voltage to the safe level for the 'bypass' mode.
> + * It checks the need of higher voltage and changes the value.
> + * The target voltage must not be less than currently needed, because
> + * for current frequency the device might become unstable.
> + */
> +static int exynos5_dmc_align_bypass_voltage(struct exynos5_dmc *dmc,
> + unsigned long target_volt)
> +{
> + int ret = 0;
> + unsigned long bypass_volt = dmc->opp_bypass.volt_uv;
> +
> + target_volt = max(bypass_volt, target_volt);
> +
> + if (dmc->curr_volt >= target_volt)
> + return 0;
> +
> + ret = regulator_set_voltage(dmc->vdd_mif, target_volt,
> + target_volt);
> + if (!ret)
> + dmc->curr_volt = target_volt;
> +
> + return ret;
> +}
> +
> +/**
> + * exynos5_dmc_align_bypass_dram_timings() - Chooses and sets DRAM timings
> + * @dmc: device for which it is going to be set
> + * @target_rate: new frequency which is chosen to be final
> + *
> + * Function changes the DRAM timings for the temporary 'bypass' mode.
> + */
> +static int exynos5_dmc_align_bypass_dram_timings(struct exynos5_dmc *dmc,
> + unsigned long target_rate)
> +{
> + int idx = find_target_freq_idx(dmc, target_rate);
> +
> + if (idx < 0)
> + return -EINVAL;
> +
> + exynos5_set_bypass_dram_timings(dmc);
> +
> + return 0;
> +}
> +
> +/**
> + * exynos5_dmc_switch_to_bypass_configuration() - Switching to temporary clock
> + * @dmc: DMC device for which the switching is going to happen
> + * @target_rate: new frequency which is going to be set as a final
> + * @target_volt: new voltage which is going to be set as a final
> + *
> + * Function configures DMC and clocks for operating in temporary 'bypass' mode.
> + * This mode is used only temporary but if required, changes voltage and timings
> + * for DRAM chips. It switches the main clock to stable clock source for the
> + * period of the main PLL reconfiguration.
> + */
> +static int exynos5_dmc_switch_to_bypass_configuration(struct exynos5_dmc *dmc,
> + unsigned long target_rate,
> + unsigned long target_volt)
> +{
> + int ret;
> +
> + /*
> + * Having higher voltage for a particular frequency does not harm
> + * the chip. Use it for the temporary frequency change when one
> + * voltage manipulation might be avoided.
> + */
> + ret = exynos5_dmc_align_bypass_voltage(dmc, target_volt);
> + if (ret)
> + return ret;
> +
> + /*
> + * Longer delays for DRAM does not cause crash, the opposite does.
> + */
> + ret = exynos5_dmc_align_bypass_dram_timings(dmc, target_rate);
> + if (ret)
> + return ret;
> +
> + clk_enable(dmc->timing_set);
> +
> + /*
> + * Voltage is set at least to a level needed for this frequency,
> + * so switching clock source is safe now.
> + */
> + clk_prepare_enable(dmc->fout_spll);
> + clk_prepare_enable(dmc->mout_spll);
> + clk_prepare_enable(dmc->mout_mx_mspll_ccore);
> +
> + ret = clk_set_parent(dmc->mout_mclk_cdrex, dmc->mout_mx_mspll_ccore);
> +
> + return ret;
> +}
> +
> +/**
> + * exynos5_dmc_change_freq_and_volt() - Changes voltage and frequency of the DMC
> + * using safe procedure
> + * @dmc: device for which the frequency is going to be changed
> + * @target_rate: requested new frequency
> + * @target_volt: requested voltage which corresponds to the new frequency
> + *
> + * The DMC frequency change procedure requires a few steps.
> + * The main requirement is to change the clock source in the clk mux
> + * for the time of main clock PLL locking. The assumption is that the
> + * alternative clock source set as parent is stable.
> + * The second parent's clock frequency is fixed to 400MHz, it is named 'bypass'
> + * clock. This requires alignment in DRAM timing parameters for the new
> + * T-period. There is two bank sets for keeping DRAM
> + * timings: set 0 and set 1. The set 0 is used when main clock source is
> + * chosen. The 2nd set of regs is used for 'bypass' clock. Switching between
> + * the two bank sets is part of the process.
> + * The voltage must also be aligned to the minimum required level. There is
> + * this intermediate step with switching to 'bypass' parent clock source.
> + * if the old voltage is lower, it requires an increase of the voltage level.
> + * The complexity of the voltage manipulation is hidden in low level function.
> + * In this function there is last alignment of the voltage level at the end.
> + */
> +static int
> +exynos5_dmc_change_freq_and_volt(struct exynos5_dmc *dmc,
> + unsigned long target_rate,
> + unsigned long target_volt)
> +{
> + int ret;
> +
> + ret = exynos5_dmc_switch_to_bypass_configuration(dmc, target_rate,
> + target_volt);
> + if (ret)
> + return ret;
> +
> + /* We are safe to increase the timings for current bypass frequency.
> + * Thanks to this the settings we be ready for the upcoming clock source
> + * change.
> + */
> + exynos5_dram_change_timings(dmc, target_rate);
> +
> + clk_set_rate(dmc->fout_bpll, target_rate);
> +
> + clk_disable(dmc->timing_set);
> +
> + ret = clk_set_parent(dmc->mout_mclk_cdrex, dmc->mout_bpll);
> + if (ret)
> + return ret;
> +
> + clk_disable_unprepare(dmc->mout_mx_mspll_ccore);
> + clk_disable_unprepare(dmc->mout_spll);
> + clk_disable_unprepare(dmc->fout_spll);
> + /* Make sure if the voltage is not from 'bypass' settings and align to
> + * the right level for power efficiency.
> + */
> + ret = exynos5_dmc_align_target_voltage(dmc, target_volt);
> +
> + return ret;
> +}
> +
> +/**
> + * exynos5_dmc_get_volt_freq() - Gets the frequency and voltage from the OPP
> + * table.
> + * @dev: device for which the frequency is going to be changed
> + * @freq: requested frequency in KHz
> + * @target_rate: returned frequency which is the same or lower than
> + * requested
> + * @target_volt: returned voltage which corresponds to the returned
> + * frequency
> + *
> + * Function gets requested frequency and checks OPP framework for needed
> + * frequency and voltage. It populates the values 'target_rate' and
> + * 'target_volt' or returns error value when OPP framework fails.
> + */
> +static int exynos5_dmc_get_volt_freq(struct device *dev, unsigned long *freq,
> + unsigned long *target_rate,
> + unsigned long *target_volt, u32 flags)
> +{
> + struct dev_pm_opp *opp;
> +
> + opp = devfreq_recommended_opp(dev, freq, flags);
> + if (IS_ERR(opp))
> + return PTR_ERR(opp);
> +
> + *target_rate = dev_pm_opp_get_freq(opp);
> + *target_volt = dev_pm_opp_get_voltage(opp);
> + dev_pm_opp_put(opp);
> +
> + return 0;
> +}
> +
> +/**
> + * exynos5_dmc_target() - Function responsible for changing frequency of DMC
> + * @dev: device for which the frequency is going to be changed
> + * @freq: requested frequency in KHz
> + * @flags: flags provided for this frequency change request
> + *
> + * An entry function provided to the devfreq framework which provides frequency
> + * change of the DMC. The function gets the possible rate from OPP table based
> + * on requested frequency. It calls the next function responsible for the
> + * frequency and voltage change. In case of failure, does not set 'curr_rate'
> + * and returns error value to the framework.
> + */
> +static int exynos5_dmc_target(struct device *dev, unsigned long *freq,
> + u32 flags)
> +{
> + struct exynos5_dmc *dmc = dev_get_drvdata(dev);
> + unsigned long target_rate = 0;
> + unsigned long target_volt = 0;
> + int ret;
> +
> + ret = exynos5_dmc_get_volt_freq(dev, freq, &target_rate, &target_volt,
> + flags);
> + if (ret)
> + return ret;
> +
> + if (target_rate == dmc->curr_rate)
> + return 0;
> +
> + mutex_lock(&dmc->lock);
> +
> + ret = exynos5_dmc_change_freq_and_volt(dmc, target_rate, target_volt);
> +
> + if (ret) {
> + mutex_unlock(&dmc->lock);
> + return ret;
> + }
> +
> + dmc->curr_rate = target_rate;
> +
> + mutex_unlock(&dmc->lock);
> + return 0;
> +}
> +
> +/**
> + * exynos5_cnt_name_match() - Tries to match 'edev' with the right device index
> + * @edev: event device for which the name is going to be matched
> + *
> + * Function matches the name of the 'edev' counter device with known devices
> + * with configured ratios and shares of the DMC channels.
> + * When the name is matched, it returns the index for the proper device.
> + */
> +static int exynos5_cnt_name_match(struct devfreq_event_dev *edev)
> +{
> + int i;
> + int id = -ENODEV;
> +
> + for (i = 0; i < ARRAY_SIZE(dmc_slot); i++) {
> + if (strstr(edev->desc->name, dmc_slot[i].name))
> + return i;
> + }
> +
> + return id;
> +}
> +
> +/**
> + * exynos5_cnt_calculate() - Calculates the values of performance counters.
> + * @edev: event device for which the counter is used for calculation
> + * @cnt: raw counter value
> + * @cnt_norm: counter value normalized to DMC performance ratio for a proper
> + * channel or virtual channel
> + *
> + * Function calculates normalized value for the raw counter. The raw counter
> + * value does not show real channel usage. The DMC splits not equally the
> + * bandwidth for the channels. The function checks the type of the 'edev'
> + * counter and calculates the normalized value based on the 'shares' of the
> + * bandwidth set in the controller.
> + */
> +static int exynos5_cnt_calculate(struct devfreq_event_dev *edev,
> + unsigned long cnt, u64 *cnt_norm)
> +{
> + int idx;
> +
> + idx = exynos5_cnt_name_match(edev);
> + if (idx < 0)
> + return idx;
> +
> + *cnt_norm = cnt;
> +
> + if (!(dmc_slot[idx].ratio_mul == dmc_slot[idx].ratio_div)) {
> + *cnt_norm = *cnt_norm * dmc_slot[idx].ratio_mul;
> + *cnt_norm = div_u64(*cnt_norm, dmc_slot[idx].ratio_div);
> + }
> +
> + *cnt_norm = *cnt_norm * PPMU_PMCNT_CONST_RATIO_MUL;
> + *cnt_norm = div_u64(*cnt_norm, PPMU_PMCNT_CONST_RATIO_DIV);
> +
> + return idx;
> +}
> +
> +/**
> + * exynos5_counters_get() - Gets the performance counters values.
> + * @dmc: device for which the counters are going to be checked
> + * @load_count: variable which is populated with counter value
> + * @total_count: variable which is used as 'wall clock' reference
> + *
> + * Function which provides performance counters values. It sums up counters for
> + * two DMC channels. The 'total_count' is used as a reference and max value.
> + * The ratio 'load_count/total_count' shows the busy percentage [0%, 100%].
> + */
> +static int exynos5_counters_get(struct exynos5_dmc *dmc,
> + unsigned long *load_count,
> + unsigned long *total_count)
> +{
> + unsigned long load_dmc[2] = {0, 0};
> + unsigned long total = 0;
> + u64 load = 0;
> + struct devfreq_event_data event;
> + int ret, i, idx;
> +
> + for (i = 0; i < dmc->num_counters; i++) {
> + if (!dmc->counter[i])
> + continue;
> +
> + ret = devfreq_event_get_event(dmc->counter[i], &event);
> + if (ret < 0)
> + return ret;
> +
> + idx = exynos5_cnt_calculate(dmc->counter[i], event.load_count,
> + &load);
> + if (idx < 0)
> + continue;
> +
> + if (idx == DMC0_0 || idx == DMC0_1)
> + load_dmc[0] += load;
> + else
> + load_dmc[1] += load;
> +
> + if (total < event.total_count)
> + total = event.total_count;
> + }
> +
> + *load_count = load_dmc[0] + load_dmc[1];
> + *total_count = total;
> +
> + return 0;
> +}
> +
> +/**
> + * exynos5_dmc_get_status() - Read current DMC performance statistics.
> + * @dev: device for which the statistics are requested
> + * @stat: structure which has statistic fields
> + *
> + * Function reads the DMC performance counters and calculates 'busy_time'
> + * and 'total_time'. To protect from overflow, the values are shifted right
> + * by 10. After read out the counters are setup to count again.
> + */
> +static int exynos5_dmc_get_status(struct device *dev,
> + struct devfreq_dev_status *stat)
> +{
> + struct exynos5_dmc *dmc = dev_get_drvdata(dev);
> + unsigned long load, total;
> + int ret;
> + bool cnt_en;
> +
> + mutex_lock(&dmc->lock);
> + cnt_en = dmc->counters_enabled;
> + mutex_unlock(&dmc->lock);
> + if (!cnt_en) {
> + dev_warn(dev, "performance counters needed, but not present\n");
> + return -EAGAIN;
> + }
> +
> + ret = exynos5_counters_get(dmc, &load, &total);
> + if (ret < 0)
> + return -EINVAL;
> +
> + /* To protect from overflow in calculation ratios, divide by 1024 */
> + stat->busy_time = load >> 10;
> + stat->total_time = total >> 10;
> +
> + ret = exynos5_counters_set_event(dmc);
> + if (ret < 0) {
> + dev_err(dmc->dev, "could not set event counter\n");
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +/**
> + * exynos5_dmc_get_cur_freq() - Function returns current DMC frequency
> + * @dev: device for which the framework checks operating frequency
> + * @freq: returned frequency value
> + *
> + * It returns the currently used frequency of the DMC. The real operating
> + * frequency might be lower when the clock source value could not be divided
> + * to the requested value.
> + */
> +static int exynos5_dmc_get_cur_freq(struct device *dev, unsigned long *freq)
> +{
> + struct exynos5_dmc *dmc = dev_get_drvdata(dev);
> +
> + mutex_lock(&dmc->lock);
> + *freq = dmc->curr_rate;
> + mutex_unlock(&dmc->lock);
> +
> + return 0;
> +}
> +
> +/**
> + * exynos5_dmc_df_profile - Devfreq governor's profile structure
> + *
> + * It provides to the devfreq framework needed functions and polling period.
> + */
> +static struct devfreq_dev_profile exynos5_dmc_df_profile = {
> + .polling_ms = 500,
> + .target = exynos5_dmc_target,
> + .get_dev_status = exynos5_dmc_get_status,
> + .get_cur_freq = exynos5_dmc_get_cur_freq,
> +};
> +
> +/**
> + * exynos5_dmc_align_initial_frequency() - Align initial frequency value
> + * @dmc: device for which the frequency is going to be set
> + * @bootloader_init_freq: initial frequency set by the bootloader in KHz
> + *
> + * The initial bootloader frequency, which is present during boot, might be
> + * different that supported frequency values in the driver. It is possible
> + * due to different PLL settings or used PLL as a source.
> + * This function provides the 'initial_freq' for the devfreq framework
> + * statistics engine which supports only registered values. Thus, some alignment
> + * must be made.
> + */
> +unsigned long
> +exynos5_dmc_align_init_freq(struct exynos5_dmc *dmc,
> + unsigned long bootloader_init_freq)
> +{
> + unsigned long aligned_freq;
> + int idx;
> +
> + idx = find_target_freq_idx(dmc, bootloader_init_freq);
> + if (idx >= 0)
> + aligned_freq = dmc->opp[idx].freq_hz;
> + else
> + aligned_freq = dmc->opp[dmc->opp_count - 1].freq_hz;
> +
> + return aligned_freq;
> +}
> +
> +/**
> + * of_get_dram_timings() - helper function for parsing DT settings for DRAM
> + * @dmc: device for which the frequency is going to be set
> + *
> + * The function parses DT entries with DRAM information.
> + */
> +static int of_get_dram_timings(struct exynos5_dmc *dmc)
> +{
> + int ret = 0;
> + int count;
> + struct device_node *np;
> +
> + np = of_find_compatible_node(NULL, NULL, "samsung,dram-timing");
> + if (!np)
> + return -EINVAL;
> +
> + count = of_property_count_strings(np, "dram-timing-names");
> + if (count < 1)
> + return -EINVAL;
> +
> + dmc->timing_row = devm_kmalloc_array(dmc->dev, count, sizeof(u32),
> + GFP_KERNEL);
> + if (!dmc->timing_row)
> + return -ENOMEM;
> +
> + ret = of_property_read_u32_array(np, "dram-timing-row",
> + dmc->timing_row, count);
> +
> + if (ret) {
> + dev_warn(dmc->dev, "failed parcing dram-timing-row\n");
> + return -EINVAL;
> + }
> +
> + dmc->timing_data = devm_kmalloc_array(dmc->dev, count, sizeof(u32),
> + GFP_KERNEL);
> + if (!dmc->timing_data)
> + return -ENOMEM;
> +
> + ret = of_property_read_u32_array(np, "dram-timing-data",
> + dmc->timing_data, count);
> + if (ret) {
> + dev_warn(dmc->dev, "failed parcing dram-timing-data\n");
> + return -EINVAL;
> + }
> +
> + dmc->timing_power = devm_kmalloc_array(dmc->dev, count, sizeof(u32),
> + GFP_KERNEL);
> + if (!dmc->timing_power)
> + return -ENOMEM;
> +
> + ret = of_property_read_u32_array(np, "dram-timing-power",
> + dmc->timing_power, count);
> + if (ret) {
> + dev_warn(dmc->dev, "failed parcing dram-timing-power\n");
> + return -EINVAL;
> + }
> +
> + of_node_put(np);
> +
> + np = of_find_compatible_node(NULL, NULL, "samsung,dmc-bypass-mode");
> + if (!np)
> + return -EINVAL;
> +
> + ret = of_property_read_u32(np, "freq-hz",
> + &dmc->opp_bypass.freq_hz);
> +
> + ret |= of_property_read_u32(np, "volt-uv",
> + &dmc->opp_bypass.volt_uv);
> +
> + ret |= of_property_read_u32(np, "dram-timing-row",
> + &dmc->bypass_timing_row);
> +
> + ret |= of_property_read_u32(np, "dram-timing-data",
> + &dmc->bypass_timing_data);
> +
> + ret |= of_property_read_u32(np, "dram-timing-power",
> + &dmc->bypass_timing_power);
> +
> + of_node_put(np);
> +
> + return ret;
> +}
> +
> +/**
> + * exynos5_dmc_init_clks() - Initialize clocks needed for DMC operation.
> + * @dev: device for which the clocks are setup
> + * @dmc: DMC structure containing needed fields
> + *
> + * Get the needed clocks defined in DT device, enable and set the right parents.
> + * Read current frequency and initialize the initial rate for governor.
> + */
> +static int exynos5_dmc_init_clks(struct device *dev, struct exynos5_dmc *dmc)
> +{
> + int ret;
> + unsigned long target_volt = 0;
> + unsigned long target_rate = 0;
> +
> + dmc->fout_spll = devm_clk_get(dev, "fout_spll");
> + if (IS_ERR(dmc->fout_spll))
> + return PTR_ERR(dmc->fout_spll);
> +
> + dmc->fout_bpll = devm_clk_get(dev, "fout_bpll");
> + if (IS_ERR(dmc->fout_bpll))
> + return PTR_ERR(dmc->fout_bpll);
> +
> + dmc->mout_mclk_cdrex = devm_clk_get(dev, "mout_mclk_cdrex");
> + if (IS_ERR(dmc->mout_mclk_cdrex))
> + return PTR_ERR(dmc->mout_mclk_cdrex);
> +
> + dmc->mout_bpll = devm_clk_get(dev, "mout_bpll");
> + if (IS_ERR(dmc->mout_bpll))
> + return PTR_ERR(dmc->mout_bpll);
> +
> + dmc->mout_mx_mspll_ccore = devm_clk_get(dev, "mout_mx_mspll_ccore");
> + if (IS_ERR(dmc->mout_mx_mspll_ccore))
> + return PTR_ERR(dmc->mout_mx_mspll_ccore);
> +
> + dmc->dout_clk2x_phy0 = devm_clk_get(dev, "dout_clk2x_phy0");
> + if (IS_ERR(dmc->dout_clk2x_phy0))
> + return PTR_ERR(dmc->dout_clk2x_phy0);
> +
> + dmc->mout_spll = devm_clk_get(dev, "ff_dout_spll2");
> + if (IS_ERR(dmc->mout_spll))
> + return PTR_ERR(dmc->mout_spll);
> +
> + dmc->cdrex_pause = devm_clk_get(dev, "clk_cdrex_pause");
> + if (IS_ERR(dmc->cdrex_pause))
> + return PTR_ERR(dmc->cdrex_pause);
> +
> + dmc->timing_set = devm_clk_get(dev, "clk_cdrex_timing_set");
> + if (IS_ERR(dmc->timing_set))
> + return PTR_ERR(dmc->timing_set);
> + /*
> + * Convert frequency to KHz values and set it for the governor.
> + */
> + dmc->curr_rate = clk_get_rate(dmc->mout_mclk_cdrex);
> + dmc->curr_rate = exynos5_dmc_align_init_freq(dmc, dmc->curr_rate);
> + exynos5_dmc_df_profile.initial_freq = dmc->curr_rate;
> +
> + ret = exynos5_dmc_get_volt_freq(dev, &dmc->curr_rate, &target_rate,
> + &target_volt, 0);
> + if (ret)
> + return ret;
> +
> + dmc->curr_volt = target_volt;
> +
> + clk_prepare_enable(dmc->mout_spll);
> + clk_set_parent(dmc->mout_mx_mspll_ccore, dmc->mout_spll);
> + clk_prepare_enable(dmc->mout_mx_mspll_ccore);
> +
> + clk_prepare_enable(dmc->fout_bpll);
> + clk_prepare_enable(dmc->mout_bpll);
> +
> + clk_prepare_enable(dmc->cdrex_pause);
> + clk_prepare(dmc->timing_set);
> +
> + return 0;
> +}
> +
> +/**
> + * exynos5_performance_counters_init() - Initializes performance DMC's counters
> + * @dmc: DMC for which it does the setup
> + *
> + * Initialization of performance counters in DMC for estimating usage.
> + * The counter's values are used for calculation of a memory bandwidth and based
> + * on that the governor changes the frequency.
> + * The counters are not used when the governor is GOVERNOR_USERSPACE.
> + */
> +static int exynos5_performance_counters_init(struct exynos5_dmc *dmc)
> +{
> + int counters_size;
> + int ret, i;
> +
> + dmc->num_counters = devfreq_event_get_edev_count(dmc->dev);
> + if (dmc->num_counters < 0) {
> + dev_err(dmc->dev, "could not get devfreq-event counters\n");
> + return dmc->num_counters;
> + }
> +
> + counters_size = sizeof(struct devfreq_event_dev) * dmc->num_counters;
> + dmc->counter = devm_kzalloc(dmc->dev, counters_size, GFP_KERNEL);
> + if (!dmc->counter)
> + return -ENOMEM;
> +
> + for (i = 0; i < dmc->num_counters; i++) {
> + dmc->counter[i] =
> + devfreq_event_get_edev_by_phandle(dmc->dev, i);
> + if (IS_ERR_OR_NULL(dmc->counter[i]))
> + return -EPROBE_DEFER;
> + }
> +
> + ret = exynos5_counters_enable_edev(dmc);
> + if (ret < 0) {
> + dev_err(dmc->dev, "could not enable event counter\n");
> + return ret;
> + }
> +
> + ret = exynos5_counters_set_event(dmc);
> + if (ret < 0) {
> + dev_err(dmc->dev, "counld not set event counter\n");
> + return ret;
> + }
> +
> + mutex_lock(&dmc->lock);
> + dmc->counters_enabled = true;
> + mutex_unlock(&dmc->lock);
> +
> + return 0;
> +}
> +
> +/**
> + * exynos5_dmc_probe() - Probe function for the DMC driver
> + * @pdev: platform device for which the driver is going to be initialized
> + *
> + * Initialize basic components: clocks, regulators, performance counters, etc.
> + * Read out product version and based on the information setup
> + * internal structures for the controller (frequency and voltage) and for DRAM
> + * memory parameters: timings for each operating frequency.
> + * Register new devfreq device for controlling DVFS of the DMC.
> + */
> +static int exynos5_dmc_probe(struct platform_device *pdev)
> +{
> + int ret = 0;
> + struct exynos5_dmc *dmc;
> + struct device *dev = &pdev->dev;
> + struct resource *res;
> +
> + dmc = devm_kzalloc(dev, sizeof(*dmc), GFP_KERNEL);
> + if (!dmc)
> + return -ENOMEM;
> +
> + mutex_init(&dmc->lock);
> +
> + dmc->dev = dev;
> + platform_set_drvdata(pdev, dmc);
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + dmc->base_drexi0 = devm_ioremap_resource(dev, res);
> + if (IS_ERR(dmc->base_drexi0))
> + return PTR_ERR(dmc->base_drexi0);
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
> + dmc->base_drexi1 = devm_ioremap_resource(dev, res);
> + if (IS_ERR(dmc->base_drexi1))
> + return PTR_ERR(dmc->base_drexi1);
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
> + dmc->chip_id = devm_ioremap_resource(dev, res);
> + if (IS_ERR(dmc->chip_id))
> + return PTR_ERR(dmc->chip_id);
> +
> + ret = exynos5_dmc_chip_revision_settings(dmc);
> + if (ret)
> + return ret;
> +
> + ret = exynos5_init_freq_table(dev, dmc, &exynos5_dmc_df_profile);
> + if (ret)
> + return ret;
> +
> + ret = of_get_dram_timings(dmc);
> + if (ret)
> + return ret;
> +
> + dmc->vdd_mif = devm_regulator_get(dev, "vdd_mif");
> + if (IS_ERR(dmc->vdd_mif)) {
> + ret = PTR_ERR(dmc->vdd_mif);
> + dev_warn(dev, "couldn't get regulator\n");
> + return ret;
> + }
> +
> + ret = exynos5_dmc_init_clks(dev, dmc);
> + if (ret) {
> + dev_warn(dev, "couldn't initialize clocks\n");
> + return ret;
> + }
> +
> + ret = exynos5_performance_counters_init(dmc);
> + if (ret) {
> + dev_warn(dev, "couldn't probe performance counters\n");
> + goto remove_clocks;
> + }
> + /*
> + * Setup default thresholds for the devfreq governor.
> + * The values are chosen based on experiments.
> + */
> + dmc->gov_data.upthreshold = 30;
> + dmc->gov_data.downdifferential = 5;
> +
> + dmc->df = devm_devfreq_add_device(dev, &exynos5_dmc_df_profile,
> + DEVFREQ_GOV_USERSPACE,
> + &dmc->gov_data);
> +
> + if (IS_ERR(dmc->df)) {
> + ret = PTR_ERR(dmc->df);
> + goto err_devfreq_add;
> + }
> +
> + dev_info(&pdev->dev, "DMC init for prod_id=0x%08x pkg_id=0x%08x\n",
> + dmc->prod_rev, dmc->pkg_rev);
> +
> + return 0;
> +
> +err_devfreq_add:
> + exynos5_counters_disable_edev(dmc);
> +remove_clocks:
> + clk_disable_unprepare(dmc->mout_mx_mspll_ccore);
> + clk_disable_unprepare(dmc->mout_spll);
> +
> + return ret;
> +}
> +
> +/**
> + * exynos5_dmc_remove() - Remove function for the platform device
> + * @pdev: platform device which is going to be removed
> + *
> + * The function relies on 'devm' framework function which automatically
> + * clean the device's resources. It just calls explicitly disable function for
> + * the performance counters.
> + */
> +static int exynos5_dmc_remove(struct platform_device *pdev)
> +{
> + struct exynos5_dmc *dmc = dev_get_drvdata(&pdev->dev);
> +
> + exynos5_counters_disable_edev(dmc);
> +
> + clk_disable_unprepare(dmc->mout_mx_mspll_ccore);
> + clk_disable_unprepare(dmc->mout_spll);
> +
> + dev_pm_opp_remove_table(&pdev->dev);
> +
> + dev_info(&pdev->dev, "DMC removed\n");
> +
> + return 0;
> +}
> +
> +static const struct of_device_id exynos5_dmc_of_match[] = {
> + { .compatible = "samsung,exynos5422-dmc", },
> + { },
> +};
> +MODULE_DEVICE_TABLE(of, exynos5_dmc_of_match);
> +
> +static struct platform_driver exynos5_dmc_platdrv = {
> + .probe = exynos5_dmc_probe,
> + .remove = exynos5_dmc_remove,
> + .driver = {
> + .name = "exynos5-dmc",
> + .of_match_table = exynos5_dmc_of_match,
> + },
> +};
> +module_platform_driver(exynos5_dmc_platdrv);
> +MODULE_DESCRIPTION("Driver for Exynos5422 Dynamic Memory Controller dynamic frequency and voltage change"
> +);
> +MODULE_LICENSE("GPL v2");
> +MODULE_AUTHOR("Samsung");
>
--
Best Regards,
Chanwoo Choi
Samsung Electronics
Hi Lukasz,
You are missing some answer on v4 patch[1] and then
send the patch without modification. On many times,
I mentioned that please answer from the comment.
Please check the comments from reviewers
carefully without any lost.
- [v4,2/8] clk: samsung: add new clocks for DMC for Exynos5422 SoC
[1] https://lkml.org/lkml/2019/2/12/12
Please answer from the following comment.
[Following comments on v4 patch]
>>> + DIV(0, "dout_pclk_drex0", "dout_cclk_drex0", DIV_CDREX0, 28, 3),
>>
>> Before applied this patch, on line 809, DIV_CDREX0[28:30] was already
>> defined with "dout_pclk_cdrex" gate clock name.
> In my previous email, I have mentioned that the same bits
> (8 combinations) are controlling 3 dividers, which re-branch to 3 edges
> in the clock tree named:
> CLKDIV_PCLK_CDREX, CLKDIV_PCLK_DREX0, CLKDIV_PCLK_DREX1.
> It is in the Exynos5422_UM_REV0.10 documentation section:
> 7.9.6.7 CLK_DIV_CDREX0
It is my missing point. I checked it on Exynos5422 TRM.
I want to develop the clocks according to H/W clock.
Please keep it without removal.
Instead,
It is very strange case. So, you need to add
the detailed comment when defining the multiple clocks
with same register/same bits. Also, in order to reduce
the confusion of this strange case, IMO you better to
define the three clocks at the nearby in this driver.
(CLKDIV_PCLK_CDREX, CLKDIV_PCLK_DREX0, CLKDIV_PCLK_DREX1)
If they are scattered, it is difficult for understanding
why they are developed like this.
On 19. 3. 5. 오후 7:19, Lukasz Luba wrote:
> This patch provides support for clocks needed for Dynamic Memory Controller
> in Exynos5422 SoC. It adds CDREX base register addresses, new DIV, MUX and
> GATE entries.
>
> Signed-off-by: Lukasz Luba <[email protected]>
> ---
> drivers/clk/samsung/clk-exynos5420.c | 54 +++++++++++++++++++++++++++++++++---
> 1 file changed, 50 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
> index 34cce3c..6da5875 100644
> --- a/drivers/clk/samsung/clk-exynos5420.c
> +++ b/drivers/clk/samsung/clk-exynos5420.c
> @@ -134,6 +134,10 @@
> #define SRC_CDREX 0x20200
> #define DIV_CDREX0 0x20500
> #define DIV_CDREX1 0x20504
> +#define GATE_BUS_CDREX0 0x20700
> +#define GATE_BUS_CDREX1 0x20704
> +#define CDREX_PAUSE 0x2091c
> +#define CDREX_LPDDR3PHY_CON3 0x20a20
> #define KPLL_LOCK 0x28000
> #define KPLL_CON0 0x28100
> #define SRC_KFC 0x28200
> @@ -248,6 +252,10 @@ static const unsigned long exynos5x_clk_regs[] __initconst = {
> DIV_CDREX1,
> SRC_KFC,
> DIV_KFC0,
> + GATE_BUS_CDREX0,
> + GATE_BUS_CDREX1,
> + CDREX_PAUSE,
> + CDREX_LPDDR3PHY_CON3,
> };
>
> static const unsigned long exynos5800_clk_regs[] __initconst = {
> @@ -425,6 +433,9 @@ PNAME(mout_group13_5800_p) = { "dout_osc_div", "mout_sw_aclkfl1_550_cam" };
> PNAME(mout_group14_5800_p) = { "dout_aclk550_cam", "dout_sclk_sw" };
> PNAME(mout_group15_5800_p) = { "dout_osc_div", "mout_sw_aclk550_cam" };
> PNAME(mout_group16_5800_p) = { "dout_osc_div", "mout_mau_epll_clk" };
> +PNAME(mout_mx_mspll_ccore_phy_p) = { "sclk_bpll", "mout_sclk_dpll",
> + "mout_sclk_mpll", "ff_dout_spll2",
> + "mout_sclk_spll", "mout_sclk_epll"};
>
> /* fixed rate clocks generated outside the soc */
> static struct samsung_fixed_rate_clock
> @@ -450,7 +461,7 @@ static const struct samsung_fixed_factor_clock
> static const struct samsung_fixed_factor_clock
> exynos5800_fixed_factor_clks[] __initconst = {
> FFACTOR(0, "ff_dout_epll2", "mout_sclk_epll", 1, 2, 0),
> - FFACTOR(0, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0),
> + FFACTOR(CLK_FF_DOUT_SPLL2, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0),
> };
>
> static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
> @@ -472,11 +483,14 @@ static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
> MUX(0, "mout_aclk300_disp1", mout_group5_5800_p, SRC_TOP2, 24, 2),
> MUX(0, "mout_aclk300_gscl", mout_group5_5800_p, SRC_TOP2, 28, 2),
>
> + MUX(CLK_MOUT_MX_MSPLL_CCORE_PHY, "mout_mx_mspll_ccore_phy",
> + mout_mx_mspll_ccore_phy_p, SRC_TOP7, 0, 3),
> +
> MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore",
> - mout_mx_mspll_ccore_p, SRC_TOP7, 16, 2),
> + mout_mx_mspll_ccore_p, SRC_TOP7, 16, 3),
> MUX_F(CLK_MOUT_MAU_EPLL, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p,
> SRC_TOP7, 20, 2, CLK_SET_RATE_PARENT, 0),
> - MUX(0, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1),
> + MUX(CLK_SCLK_BPLL, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1),
> MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1),
>
> MUX(0, "mout_aclk550_cam", mout_group3_5800_p, SRC_TOP8, 16, 3),
> @@ -648,7 +662,7 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
>
> MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1),
> MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1),
> - MUX(0, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1),
> + MUX(CLK_MOUT_SCLK_SPLL, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1),
> MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1),
> MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1),
> MUX_F(CLK_MOUT_EPLL, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1,
> @@ -817,6 +831,8 @@ static const struct samsung_div_clock exynos5x_div_clks[] __initconst = {
> DIV(CLK_DOUT_CLK2X_PHY0, "dout_clk2x_phy0", "dout_sclk_cdrex",
> DIV_CDREX0, 3, 5),
>
> + DIV(0, "dout_pclk_drex0", "dout_cclk_drex0", DIV_CDREX0, 28, 3),
> +
> DIV(CLK_DOUT_PCLK_CORE_MEM, "dout_pclk_core_mem", "mout_mclk_cdrex",
> DIV_CDREX1, 8, 3),
>
> @@ -1170,6 +1186,36 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
> GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0),
>
> GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0),
> +
> + /* CDREX */
> + GATE(CLK_CLKM_PHY0, "clkm_phy0", "dout_sclk_cdrex",
> + GATE_BUS_CDREX0, 0, 0, 0),
> + GATE(CLK_CLKM_PHY1, "clkm_phy1", "dout_sclk_cdrex",
> + GATE_BUS_CDREX0, 1, 0, 0),
nitpick. Add the blank line because of clocks of the different register.
> + GATE(0, "mx_mspll_ccore_phy", "mout_mx_mspll_ccore_phy",
> + SRC_MASK_TOP7, 0, CLK_IGNORE_UNUSED, 0),
> +
> + GATE(CLK_ACLK_PPMU_DREX1_1, "aclk_ppmu_drex1_1", "dout_aclk_cdrex1",
> + GATE_BUS_CDREX1, 12, CLK_IGNORE_UNUSED, 0),
> + GATE(CLK_ACLK_PPMU_DREX1_0, "aclk_ppmu_drex1_0", "dout_aclk_cdrex1",
> + GATE_BUS_CDREX1, 13, CLK_IGNORE_UNUSED, 0),
> + GATE(CLK_ACLK_PPMU_DREX0_1, "aclk_ppmu_drex0_1", "dout_aclk_cdrex1",
> + GATE_BUS_CDREX1, 14, CLK_IGNORE_UNUSED, 0),
> + GATE(CLK_ACLK_PPMU_DREX0_0, "aclk_ppmu_drex0_0", "dout_aclk_cdrex1",
> + GATE_BUS_CDREX1, 15, CLK_IGNORE_UNUSED, 0),
> +
> + GATE(CLK_PCLK_PPMU_DREX1_1, "pclk_ppmu_drex1_1", "dout_pclk_cdrex",
> + GATE_BUS_CDREX1, 26, CLK_IGNORE_UNUSED, 0),
> + GATE(CLK_PCLK_PPMU_DREX1_0, "pclk_ppmu_drex1_0", "dout_pclk_cdrex",
> + GATE_BUS_CDREX1, 27, CLK_IGNORE_UNUSED, 0),
> + GATE(CLK_PCLK_PPMU_DREX0_1, "pclk_ppmu_drex0_1", "dout_pclk_cdrex",
> + GATE_BUS_CDREX1, 28, CLK_IGNORE_UNUSED, 0),
> + GATE(CLK_PCLK_PPMU_DREX0_0, "pclk_ppmu_drex0_0", "dout_pclk_cdrex",
> + GATE_BUS_CDREX1, 29, CLK_IGNORE_UNUSED, 0),
> +
> + GATE(CLK_CDREX_PAUSE, "clk_cdrex_pause", NULL, CDREX_PAUSE, 0, 0, 0),
nitpick. Add the blank line because of clocks of the different register.
> + GATE(CLK_CDREX_TIMING_SET, "clk_cdrex_timing_set", NULL,
> + CDREX_LPDDR3PHY_CON3, 28, 0, 0),
> };
>
> static const struct samsung_div_clock exynos5x_disp_div_clks[] __initconst = {
>
--
Best Regards,
Chanwoo Choi
Samsung Electronics
(Adding DT maintainers at Cc)
On 3/5/19 11:19, Lukasz Luba wrote:
> The patch adds description for DT binding for a new Exynos5422 Dynamic
> Memory Controller device.
>
> Signed-off-by: Lukasz Luba <[email protected]>
> ---
> .../devicetree/bindings/devfreq/exynos5422-dmc.txt | 177 +++++++++++++++++++++
> 1 file changed, 177 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/devfreq/exynos5422-dmc.txt
>
> diff --git a/Documentation/devicetree/bindings/devfreq/exynos5422-dmc.txt b/Documentation/devicetree/bindings/devfreq/exynos5422-dmc.txt
> new file mode 100644
> index 0000000..0e73e98
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/devfreq/exynos5422-dmc.txt
> @@ -0,0 +1,177 @@
> +* Exynos5422 frequency and voltage scaling for Dynamic Memory Controller device
> +
> +The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the DRAM
> +memory chips are connected. The driver is to monitor the controller in runtime
> +and switch frequency and voltage. To monitor the usage of the controller in
> +runtime, the driver uses the PPMU (Platform Performance Monitoring Unit), which
> +is able to measure the current load of the memory.
> +When 'userspace' governor is used for the driver, an application is able to
> +switch the DMC frequency.
I would avoid talking about "driver" and would focus more on describing actual
hardware here.
> +Required properties for DMC device for Exynos5422:
> +- compatible: Should be "samsung,exynos5422-bus".
> +- clock-names : the name of clock used by the bus, "bus".
> +- clocks : phandles for clock specified in "clock-names" property.
> +- devfreq-events : phandles for PPMU devices connected to this DMC.
Couldn't this simply be arm,ppmus or samsung,ppmus? devfreq-events sounds like
a Linux or software specific term rather than a hardware description.
> +The example definition of a DMC and PPMU devices declared in DT is shown below:
> +
> + ppmu_dmc0_0: ppmu@10d00000 {
> + compatible = "samsung,exynos-ppmu";
> + reg = <0x10d00000 0x2000>;
> + clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;
> + clock-names = "ppmu";
> + status = "okay";
> + events {
> + ppmu_event_dmc0_0: ppmu-event3-dmc0_0 {
> + event-name = "ppmu-event3-dmc0_0";
> + };
> + };
> + };
> +
> + dmc: memory-controller@10c20000 {
> + compatible = "samsung,exynos5422-dmc";
> + reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>,
> + <0x10000000 0x1000>;
> + clocks = <&clock CLK_FOUT_SPLL>,
> + <&clock CLK_MOUT_SCLK_SPLL>,
> + <&clock CLK_FF_DOUT_SPLL2>,
> + <&clock CLK_FOUT_BPLL>,
> + <&clock CLK_MOUT_BPLL>,
> + <&clock CLK_SCLK_BPLL>,
> + <&clock CLK_MOUT_MX_MSPLL_CCORE>,
> + <&clock CLK_MOUT_MX_MSPLL_CCORE_PHY>,
> + <&clock CLK_MOUT_MCLK_CDREX>,
> + <&clock CLK_DOUT_CLK2X_PHY0>,
> + <&clock CLK_CLKM_PHY0>,
> + <&clock CLK_CLKM_PHY1>,
> + <&clock CLK_CDREX_PAUSE>,
> + <&clock CLK_CDREX_TIMING_SET>;
> + clock-names = "fout_spll",
> + "mout_sclk_spll",
> + "ff_dout_spll2",
> + "fout_bpll",
> + "mout_bpll",
> + "sclk_bpll",
> + "mout_mx_mspll_ccore",
> + "mout_mx_mspll_ccore_phy",
> + "mout_mclk_cdrex",
> + "dout_clk2x_phy0",
> + "clkm_phy0",
> + "clkm_phy1",
> + "clk_cdrex_pause",
> + "clk_cdrex_timing_set";
> + status = "okay";
> + operating-points-v2 = <&dmc_opp_table>;
> + devfreq-events = <&ppmu_dmc0_0>, <&ppmu_dmc0_1>,
> + <&ppmu_dmc1_0>, <&ppmu_dmc1_1>;
> + };
> +
> +The needed timings of DRAM memory are stored in dedicated nodes.
> +There are two nodes with regular timings and for bypass mode.
> +
> + dmc_bypass_mode: bypass_mode {
> + compatible = "samsung,dmc-bypass-mode";
> +
> + freq-hz = <400000000>;
> + volt-uv = <887500>;
> + dram-timing-row = <0x365a9713>;
> + dram-timing-data = <0x4740085e>;
> + dram-timing-power = <0x543a0446>;
> + };
Couldn't this "bypass" case be included on the list within the "timing node"
(row/data/power values) and (freq-hz, volt-uv) as an OPP in dmc_opp_table
or new table?
> + dram_timing: timing {
> + compatible = "samsung,dram-timing";
> +
> + dram-timing-names = "165MHz", "206MHz", "275MHz", "413MHz",
> + "543MHz", "633MHz", "728MHz", "825MHz";
> + dram-timing-row = <0x11223185>, <0x112331C6>, <0x12244287>,
> + <0x1B35538A>, <0x244764CD>, <0x2A48758F>,
> + <0x30598651>, <0x365A9713>;
> + dram-timing-data = <0x2720085E>, <0x2720085E>, <0x2720085E>,
> + <0x2720085E>, <0x3730085E>, <0x3730085E>,
> + <0x3730085E>, <0x4740085E>;
> + dram-timing-power = <0x140C0225>, <0x180F0225>, <0x1C140225>,
> + <0x2C1D0225>, <0x38270335>, <0x402D0335>,
> + <0x4C330336>, <0x543A0446>;
> + };
We should have the meaning of each property described here and as these are
vendor specific properties there should be vendor prefix in the names.
However, I would rather see real DRAM timing parameters listed in DT and
the driver deriving those register values from such parameters. Until that's
possible it might be better to keep this raw data in the driver and avoid
pushing it to DT.
> +The frequencies supported by the DMC are stored in OPP table v2.
> +
> + dmc_opp_table: opp_table2 {
> + compatible = "operating-points-v2";
> +
> + opp00 {
> + opp-hz = /bits/ 64 <165000000>;
> + opp-microvolt = <875000>;
> + };
> + opp01 {
> + opp-hz = /bits/ 64 <206000000>;
> + opp-microvolt = <875000>;
> + };
> + opp02 {
> + opp-hz = /bits/ 64 <275000000>;
> + opp-microvolt = <875000>;
> + };
> + opp03 {
> + opp-hz = /bits/ 64 <413000000>;
> + opp-microvolt = <887500>;
> + };
> + opp04 {
> + opp-hz = /bits/ 64 <543000000>;
> + opp-microvolt = <937500>;
> + };
> + opp05 {
> + opp-hz = /bits/ 64 <633000000>;
> + opp-microvolt = <1012500>;
> + };
> + opp06 {
> + opp-hz = /bits/ 64 <728000000>;
> + opp-microvolt = <1037500>;
> + };
> + opp07 {
> + opp-hz = /bits/ 64 <825000000>;
> + opp-microvolt = <1050000>;
> + };
> + };
--
Regards,
Sylwester
On Tue, 5 Mar 2019 11:19:04 +0100, Lukasz Luba wrote:
> Define new IDs for clocks used by Dynamic Memory Controller in
> Exynos5422 SoC.
>
> Signed-off-by: Lukasz Luba <[email protected]>
> ---
> include/dt-bindings/clock/exynos5420.h | 18 +++++++++++++++++-
> 1 file changed, 17 insertions(+), 1 deletion(-)
>
Please add Acked-by/Reviewed-by tags when posting new versions. However,
there's no need to repost patches *only* to add the tags. The upstream
maintainer will do that for acks received on the version they apply.
If a tag was not added on purpose, please state why and what changed.
Hi Rob,
On 3/11/19 11:06 PM, Rob Herring wrote:
> On Tue, 5 Mar 2019 11:19:04 +0100, Lukasz Luba wrote:
>> Define new IDs for clocks used by Dynamic Memory Controller in
>> Exynos5422 SoC.
>>
>> Signed-off-by: Lukasz Luba <[email protected]>
>> ---
>> include/dt-bindings/clock/exynos5420.h | 18 +++++++++++++++++-
>> 1 file changed, 17 insertions(+), 1 deletion(-)
>>
>
> Please add Acked-by/Reviewed-by tags when posting new versions. However,
> there's no need to repost patches *only* to add the tags. The upstream
> maintainer will do that for acks received on the version they apply.
>
> If a tag was not added on purpose, please state why and what changed.
I have skipped your ACK because of the hack which is implemented in v5
clocks. Chanwoo refused the driver code because it uses 2 registers from
the clock register set without Common Clock Framework API.
He said that he will not accept this code and I have to figure out new
approach using CCF.
Thus, I have modeled these two registers as 'gates', but these registers
are for Dynamic Memory Controller PAUSE feature (which stops
transactions) and the other is for switching between
two set of registers with timings for the LPDDR3 memory (normal
operation and alternative clock source operation aka 'bypass').
These registers should be (in my opinion) in the DMC registers and not
in the clocks.
Sylwester pointed out offline that it could be done using regmap.
These are the problematic clocks added in v5:
+#define CLK_CDREX_PAUSE 531
+#define CLK_CDREX_TIMING_SET 532
I have mentioned about it in the cover letter, but you are right I could
also add a comment for this particular patch that I have skipped your
ACK.
Thank you for sharing the information about the process.
I will keep it in mind next time and will add a comment below the commit
message for a particular patch and explicit information in cover letter
that I am not including an ACK.
Regards,
Lukasz
>
>