Add APPS SMMU to SM6125 dtsi and use it in SDHCI/USB nodes.
Changes since v4:
- Use hexadecimal 0x0 for iommu mask;
- Add sm6125 to the dt-bindings list without clocks, now depending on:
https://lore.kernel.org/linux-arm-kernel/[email protected]/
v4: https://lore.kernel.org/linux-arm-msm/[email protected]/T/#u
Changes since v3:
- Drop driver patch in favour of using generic qcom,smmu-500 compatible;
- Add patches that use apps_smmu in USB and SDHCI nodes, reconfiguring
their streamID which otherwise gets lost (from the bootloader) as soon
as SMMU probes, breaking their functionality;
- Rebased on next-20221216 to solve dt-bindings conflict.
v3: https://lore.kernel.org/linux-iommu/[email protected]/T/#u
AngeloGioacchino Del Regno (1):
arm64: dts: qcom: sm6125: Add IOMMU context to DWC3
Marijn Suijten (1):
arm64: dts: qcom: sm6125: Add apps_smmu with streamID to SDHCI 1/2
nodes
Martin Botka (2):
dt-bindings: arm-smmu: Document smmu-500 binding for SM6125
arm64: dts: qcom: sm6125: Configure APPS SMMU
.../devicetree/bindings/iommu/arm,smmu.yaml | 2 +
arch/arm64/boot/dts/qcom/sm6125.dtsi | 76 +++++++++++++++++++
2 files changed, 78 insertions(+)
--
2.39.0
From: Martin Botka <[email protected]>
Document smmu-500 compatibility with the SM6125 SoC.
Signed-off-by: Martin Botka <[email protected]>
[Marijn: Move compatible to the new, generic, qcom,smmu-500 list]
Signed-off-by: Marijn Suijten <[email protected]>
---
Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
index 124253e84c02..9b4520aff92a 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
@@ -43,6 +43,7 @@ properties:
- qcom,sdm670-smmu-500
- qcom,sdm845-smmu-500
- qcom,sm6115-smmu-500
+ - qcom,sm6125-smmu-500
- qcom,sm6350-smmu-500
- qcom,sm6375-smmu-500
- qcom,sm8150-smmu-500
@@ -334,6 +335,7 @@ allOf:
- qcom,sdx55-smmu-500
- qcom,sdx65-smmu-500
- qcom,sm6115-smmu-500
+ - qcom,sm6125-smmu-500
- qcom,sm6350-smmu-500
- qcom,sm6375-smmu-500
- qcom,sm8350-smmu-500
--
2.39.0
When enabling the APPS SMMU the mainline driver reconfigures the SMMU
from its bootloader configuration, losing the stream mapping for (among
which) the SDHCI hardware and breaking its ADMA feature. This feature
can be disabled with:
sdhci.debug_quirks=0x40
But it is of course desired to have this feature enabled and working
through the SMMU.
Signed-off-by: Marijn Suijten <[email protected]>
Reviewed-by: Konrad Dybcio <[email protected]>
Reviewed-by: Martin Botka <[email protected]>
---
arch/arm64/boot/dts/qcom/sm6125.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
index 347665c2067c..32dd172ea104 100644
--- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
@@ -468,6 +468,7 @@ sdhc_1: mmc@4744000 {
<&gcc GCC_SDCC1_APPS_CLK>,
<&xo_board>;
clock-names = "iface", "core", "xo";
+ iommus = <&apps_smmu 0x160 0x0>;
power-domains = <&rpmpd SM6125_VDDCX>;
@@ -494,6 +495,7 @@ sdhc_2: mmc@4784000 {
<&gcc GCC_SDCC2_APPS_CLK>,
<&xo_board>;
clock-names = "iface", "core", "xo";
+ iommus = <&apps_smmu 0x180 0x0>;
pinctrl-0 = <&sdc2_on_state>;
pinctrl-1 = <&sdc2_off_state>;
--
2.39.0
From: AngeloGioacchino Del Regno <[email protected]>
Add an IOMMU context to the USB DWC3 controller, required to get USB
functionality upon enablement of apps_smmu.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Signed-off-by: Marijn Suijten <[email protected]>
Reviewed-by: Konrad Dybcio <[email protected]>
Reviewed-by: Martin Botka <[email protected]>
---
arch/arm64/boot/dts/qcom/sm6125.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
index 32dd172ea104..7c326368e30d 100644
--- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
@@ -542,6 +542,7 @@ usb3_dwc3: usb@4e00000 {
compatible = "snps,dwc3";
reg = <0x04e00000 0xcd00>;
interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
+ iommus = <&apps_smmu 0x100 0x0>;
phys = <&hsusb_phy1>;
phy-names = "usb2-phy";
snps,dis_u2_susphy_quirk;
--
2.39.0
From: Martin Botka <[email protected]>
Add a node for the APPS SMMU, to which various devices such as USB and
storage nodes are connected.
Signed-off-by: Martin Botka <[email protected]>
[Marijn: add the new, generic, "qcom,smmu-500" compatible, add patch
description, reorder # properties]
Signed-off-by: Marijn Suijten <[email protected]>
Reviewed-by: Konrad Dybcio <[email protected]>
---
arch/arm64/boot/dts/qcom/sm6125.dtsi | 73 ++++++++++++++++++++++++++++
1 file changed, 73 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
index bf9e8d45ee44..347665c2067c 100644
--- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
@@ -573,6 +573,79 @@ spmi_bus: spmi@1c40000 {
cell-index = <0>;
};
+ apps_smmu: iommu@c600000 {
+ compatible = "qcom,sm6125-smmu-500", "qcom,smmu-500", "arm,mmu-500";
+ reg = <0xc600000 0x80000>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+
+ #global-interrupts = <1>;
+ #iommu-cells = <2>;
+ };
+
apcs_glb: mailbox@f111000 {
compatible = "qcom,sm6125-apcs-hmss-global";
reg = <0x0f111000 0x1000>;
--
2.39.0
On 22/12/2022 20:32, Marijn Suijten wrote:
> From: Martin Botka <[email protected]>
>
> Document smmu-500 compatibility with the SM6125 SoC.
>
> Signed-off-by: Martin Botka <[email protected]>
> [Marijn: Move compatible to the new, generic, qcom,smmu-500 list]
> Signed-off-by: Marijn Suijten <[email protected]>
> ---
> Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
Acked-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On Thu, 22 Dec 2022 20:32:50 +0100, Marijn Suijten wrote:
> Add APPS SMMU to SM6125 dtsi and use it in SDHCI/USB nodes.
>
> Changes since v4:
>
> - Use hexadecimal 0x0 for iommu mask;
> - Add sm6125 to the dt-bindings list without clocks, now depending on:
> https://lore.kernel.org/linux-arm-kernel/[email protected]/
>
> [...]
Applied, thanks!
[2/4] arm64: dts: qcom: sm6125: Configure APPS SMMU
commit: 8ddb4bc3d3b52e0a560a18e4d739c83f56efe7c9
[3/4] arm64: dts: qcom: sm6125: Add apps_smmu with streamID to SDHCI 1/2 nodes
commit: 60f6c86fb4fd16bd86aa1b16bc51ef4ac0e20d4e
[4/4] arm64: dts: qcom: sm6125: Add IOMMU context to DWC3
commit: ac54563c27528ab9461899de7d99ee4e3858b858
Best regards,
--
Bjorn Andersson <[email protected]>
On Thu, 22 Dec 2022 20:32:50 +0100, Marijn Suijten wrote:
> Add APPS SMMU to SM6125 dtsi and use it in SDHCI/USB nodes.
>
> Changes since v4:
>
> - Use hexadecimal 0x0 for iommu mask;
> - Add sm6125 to the dt-bindings list without clocks, now depending on:
> https://lore.kernel.org/linux-arm-kernel/[email protected]/
>
> [...]
Applied first patch to will (for-joerg/arm-smmu/bindings), thanks!
[1/4] dt-bindings: arm-smmu: Document smmu-500 binding for SM6125
https://git.kernel.org/will/c/c940c8787929
Cheers,
--
Will
https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev