For i.MX6 SoloX, there is a mode of the SoC to shutdown all power
source of modules during system suspend and resume procedure. Thus,
SSI needs to save all the values of registers before the system
suspend and restore them after the system resume.
Signed-off-by: Zidan Wang <[email protected]>
---
sound/soc/fsl/fsl_ssi.c | 113 ++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 113 insertions(+)
diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c
index c7647e0..52b894f 100644
--- a/sound/soc/fsl/fsl_ssi.c
+++ b/sound/soc/fsl/fsl_ssi.c
@@ -111,12 +111,98 @@ struct fsl_ssi_rxtx_reg_val {
struct fsl_ssi_reg_val rx;
struct fsl_ssi_reg_val tx;
};
+
+static bool fsl_ssi_readable_reg(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case CCSR_SSI_STX0:
+ case CCSR_SSI_STX1:
+ case CCSR_SSI_SRX0:
+ case CCSR_SSI_SRX1:
+ case CCSR_SSI_SCR:
+ case CCSR_SSI_SISR:
+ case CCSR_SSI_SIER:
+ case CCSR_SSI_STCR:
+ case CCSR_SSI_SRCR:
+ case CCSR_SSI_STCCR:
+ case CCSR_SSI_SRCCR:
+ case CCSR_SSI_SFCSR:
+ case CCSR_SSI_STR:
+ case CCSR_SSI_SOR:
+ case CCSR_SSI_SACNT:
+ case CCSR_SSI_SACADD:
+ case CCSR_SSI_SACDAT:
+ case CCSR_SSI_SATAG:
+ case CCSR_SSI_STMSK:
+ case CCSR_SSI_SRMSK:
+ case CCSR_SSI_SACCST:
+ case CCSR_SSI_SACCEN:
+ case CCSR_SSI_SACCDIS:
+ return true;
+ default:
+ return false;
+ }
+}
+
+static bool fsl_ssi_volatile_reg(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case CCSR_SSI_STX0:
+ case CCSR_SSI_STX1:
+ case CCSR_SSI_SRX0:
+ case CCSR_SSI_SRX1:
+ case CCSR_SSI_SISR:
+ case CCSR_SSI_SFCSR:
+ case CCSR_SSI_SACADD:
+ case CCSR_SSI_SACDAT:
+ case CCSR_SSI_SATAG:
+ case CCSR_SSI_SACCST:
+ return true;
+ default:
+ return false;
+ }
+
+}
+
+static bool fsl_ssi_writeable_reg(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case CCSR_SSI_STX0:
+ case CCSR_SSI_STX1:
+ case CCSR_SSI_SCR:
+ case CCSR_SSI_SISR:
+ case CCSR_SSI_SIER:
+ case CCSR_SSI_STCR:
+ case CCSR_SSI_SRCR:
+ case CCSR_SSI_STCCR:
+ case CCSR_SSI_SRCCR:
+ case CCSR_SSI_SFCSR:
+ case CCSR_SSI_STR:
+ case CCSR_SSI_SOR:
+ case CCSR_SSI_SACNT:
+ case CCSR_SSI_SACADD:
+ case CCSR_SSI_SACDAT:
+ case CCSR_SSI_SATAG:
+ case CCSR_SSI_STMSK:
+ case CCSR_SSI_SRMSK:
+ case CCSR_SSI_SACCEN:
+ case CCSR_SSI_SACCDIS:
+ return true;
+ default:
+ return false;
+ }
+}
+
static const struct regmap_config fsl_ssi_regconfig = {
.max_register = CCSR_SSI_SACCDIS,
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.val_format_endian = REGMAP_ENDIAN_NATIVE,
+ .readable_reg = fsl_ssi_readable_reg,
+ .volatile_reg = fsl_ssi_volatile_reg,
+ .writeable_reg = fsl_ssi_writeable_reg,
+ .cache_type = REGCACHE_RBTREE,
};
struct fsl_ssi_soc_data {
@@ -1461,10 +1547,37 @@ static int fsl_ssi_remove(struct platform_device *pdev)
return 0;
}
+#ifdef CONFIG_PM_SLEEP
+static int fsl_ssi_suspend(struct device *dev)
+{
+ struct fsl_ssi_private *ssi_private = dev_get_drvdata(dev);
+ struct regmap *regs = ssi_private->regs;
+
+ regcache_cache_only(regs, true);
+ regcache_mark_dirty(regs);
+
+ return 0;
+}
+
+static int fsl_ssi_resume(struct device *dev)
+{
+ struct fsl_ssi_private *ssi_private = dev_get_drvdata(dev);
+ struct regmap *regs = ssi_private->regs;
+
+ regcache_cache_only(regs, false);
+ return regcache_sync(regs);
+}
+#endif /* CONFIG_PM_SLEEP */
+
+static const struct dev_pm_ops fsl_ssi_pm = {
+ SET_SYSTEM_SLEEP_PM_OPS(fsl_ssi_suspend, fsl_ssi_resume)
+};
+
static struct platform_driver fsl_ssi_driver = {
.driver = {
.name = "fsl-ssi-dai",
.of_match_table = fsl_ssi_ids,
+ .pm = &fsl_ssi_pm,
},
.probe = fsl_ssi_probe,
.remove = fsl_ssi_remove,
--
1.9.1
The register SFCSR is volatile, but some bits in it need to be
recovered after suspend/resume.
Signed-off-by: Zidan Wang <[email protected]>
---
sound/soc/fsl/fsl_ssi.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c
index 52b894f..e414f18 100644
--- a/sound/soc/fsl/fsl_ssi.c
+++ b/sound/soc/fsl/fsl_ssi.c
@@ -262,6 +262,9 @@ struct fsl_ssi_private {
unsigned int baudclk_streams;
unsigned int bitclk_freq;
+ /*regcache for SFCSR*/
+ u32 regcache_sfcsr;
+
/* DMA params */
struct snd_dmaengine_dai_dma_data dma_params_tx;
struct snd_dmaengine_dai_dma_data dma_params_rx;
@@ -1553,6 +1556,9 @@ static int fsl_ssi_suspend(struct device *dev)
struct fsl_ssi_private *ssi_private = dev_get_drvdata(dev);
struct regmap *regs = ssi_private->regs;
+ regmap_read(regs, CCSR_SSI_SFCSR,
+ &ssi_private->regcache_sfcsr);
+
regcache_cache_only(regs, true);
regcache_mark_dirty(regs);
@@ -1565,6 +1571,12 @@ static int fsl_ssi_resume(struct device *dev)
struct regmap *regs = ssi_private->regs;
regcache_cache_only(regs, false);
+
+ regmap_update_bits(regs, CCSR_SSI_SFCSR,
+ CCSR_SSI_SFCSR_RFWM1_MASK | CCSR_SSI_SFCSR_TFWM1_MASK |
+ CCSR_SSI_SFCSR_RFWM0_MASK | CCSR_SSI_SFCSR_TFWM0_MASK,
+ ssi_private->regcache_sfcsr);
+
return regcache_sync(regs);
}
#endif /* CONFIG_PM_SLEEP */
--
1.9.1
On Jul 6, 2015, at 4:49 AM, Zidan Wang wrote:
> The register SFCSR is volatile, but some bits in it need to be
> recovered after suspend/resume.
>
> Signed-off-by: Zidan Wang <[email protected]>
Shouldn't this be part of patch #1?
On Jul 6, 2015, at 4:49 AM, Zidan Wang wrote:
> +static bool fsl_ssi_readable_reg(struct device *dev, unsigned int reg)
> +{
> + switch (reg) {
> + case CCSR_SSI_STX0:
> + case CCSR_SSI_STX1:
> + case CCSR_SSI_SRX0:
> + case CCSR_SSI_SRX1:
> + case CCSR_SSI_SCR:
> + case CCSR_SSI_SISR:
> + case CCSR_SSI_SIER:
> + case CCSR_SSI_STCR:
> + case CCSR_SSI_SRCR:
> + case CCSR_SSI_STCCR:
> + case CCSR_SSI_SRCCR:
> + case CCSR_SSI_SFCSR:
> + case CCSR_SSI_STR:
> + case CCSR_SSI_SOR:
> + case CCSR_SSI_SACNT:
> + case CCSR_SSI_SACADD:
> + case CCSR_SSI_SACDAT:
> + case CCSR_SSI_SATAG:
> + case CCSR_SSI_STMSK:
> + case CCSR_SSI_SRMSK:
> + case CCSR_SSI_SACCST:
> + case CCSR_SSI_SACCEN:
> + case CCSR_SSI_SACCDIS:
> + return true;
> + default:
> + return false;
> + }
> +}
This should be the other way around: return true by default, and false it is one of the few registers that is not readable.-