This patchset adds initial support for the Nuvoton
Arbel NPCM8XX Board Management controller (BMC) SoC family.
The Nuvoton Arbel NPCM8XX SoC is a fourth-generation BMC.
The NPCM8XX computing subsystem comprises a quadcore ARM
Cortex A35 ARM-V8 architecture.
This patchset adds minimal architecture and drivers such as:
Clocksource, Clock, Reset, and WD.
Some of the Arbel NPCM8XX peripherals are based on Poleg NPCM7XX.
This patchset was tested on the Arbel NPCM8XX evaluation board.
Addressed comments from:
- Arnd Bergmann : https://www.spinics.net/lists/arm-kernel/msg986516.html
https://www.spinics.net/lists/arm-kernel/msg986540.html
- Stephen Boyd: https://www.spinics.net/lists/devicetree/msg507280.html
- Krzysztof Kozlowski: https://www.spinics.net/lists/kernel/msg4389776.html
https://www.spinics.net/lists/arm-kernel/msg986462.html
https://www.spinics.net/lists/linux-clk/msg71589.html
https://www.spinics.net/lists/arm-kernel/msg987286.html
https://www.spinics.net/lists/arm-kernel/msg987099.html
https://www.spinics.net/lists/kernel/msg4389821.html
- Rob Herring : https://www.spinics.net/lists/arm-kernel/msg986655.html
Changes since version 2:
- Remove NPCM8xx WDT compatible patch.
- Remove NPCM8xx UART compatible patch.
- NPCM8XX clock driver
- Add debug new line.
- Add 25M fixed rate clock.
- Remove unused clocks and clock name from dt-binding.
- NPCM reset driver
- Revert to npcm7xx dt-binding.
- Skip dt binding quotes.
- Adding DTS backward compatibility.
- Remove NPCM8xx binding include file.
- Warp commit message.
- NPCM8XX device tree:
- Remove unused clock nodes (used in the clock driver)
- Modify gcr and rst node names.
Changes since version 1:
- NPCM8XX clock driver
- Modify dt-binding.
- Remove unsed definition and include.
- Include alphabetically.
- Use clock devm.
- NPCM reset driver
- Modify dt-binding.
- Modify syscon name.
- Add syscon support to NPCM7XX dts reset node.
- use data structure.
- NPCM8XX device tree:
- Modify evb compatible name.
- Add NPCM7xx compatible.
- Remove disable nodes from the EVB DTS.
Tomer Maimon (18):
dt-bindings: timer: npcm: Add npcm845 compatible string
clocksource: timer-npcm7xx: Add NPCM845 timer support
dt-bindings: serial: 8250: Add npcm845 compatible string
dt-bindings: watchdog: npcm: Add npcm845 compatible string
dt-binding: clk: npcm845: Add binding for Nuvoton NPCM8XX Clock
clk: npcm8xx: add clock controller
dt-bindings: reset: npcm: add GCR syscon property
ARM: dts: nuvoton: add reset syscon property
reset: npcm: using syscon instead of device data
dt-bindings: reset: npcm: Add support for NPCM8XX
reset: npcm: Add NPCM8XX support
dt-bindings: arm: npcm: Add maintainer
dt-bindings: arm: npcm: Add nuvoton,npcm845 compatible string
dt-bindings: arm: npcm: Add nuvoton,npcm845 GCR compatible string
arm64: npcm: Add support for Nuvoton NPCM8XX BMC SoC
arm64: dts: nuvoton: Add initial NPCM8XX device tree
arm64: dts: nuvoton: Add initial NPCM845 EVB device tree
arm64: defconfig: Add Nuvoton NPCM family support
.../devicetree/bindings/arm/npcm/npcm.yaml | 7 +
.../bindings/arm/npcm/nuvoton,gcr.yaml | 2 +
.../bindings/clock/nuvoton,npcm845-clk.yaml | 49 ++
.../bindings/reset/nuvoton,npcm750-reset.yaml | 9 +-
.../devicetree/bindings/serial/8250.yaml | 1 +
.../bindings/timer/nuvoton,npcm7xx-timer.yaml | 2 +
.../bindings/watchdog/nuvoton,npcm-wdt.txt | 3 +-
MAINTAINERS | 2 +
arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi | 1 +
arch/arm64/Kconfig.platforms | 11 +
arch/arm64/boot/dts/Makefile | 1 +
arch/arm64/boot/dts/nuvoton/Makefile | 2 +
.../dts/nuvoton/nuvoton-common-npcm8xx.dtsi | 170 ++++
.../boot/dts/nuvoton/nuvoton-npcm845-evb.dts | 30 +
.../boot/dts/nuvoton/nuvoton-npcm845.dtsi | 76 ++
arch/arm64/configs/defconfig | 3 +
drivers/clk/Kconfig | 6 +
drivers/clk/Makefile | 1 +
drivers/clk/clk-npcm8xx.c | 760 ++++++++++++++++++
drivers/clocksource/timer-npcm7xx.c | 1 +
drivers/reset/reset-npcm.c | 206 ++++-
.../dt-bindings/clock/nuvoton,npcm8xx-clock.h | 49 ++
22 files changed, 1356 insertions(+), 36 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml
create mode 100644 arch/arm64/boot/dts/nuvoton/Makefile
create mode 100644 arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
create mode 100644 arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts
create mode 100644 arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi
create mode 100644 drivers/clk/clk-npcm8xx.c
create mode 100644 include/dt-bindings/clock/nuvoton,npcm8xx-clock.h
--
2.33.0
Add a compatible string for Nuvoton BMC NPCM845 watchdog.
Signed-off-by: Tomer Maimon <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
---
.../devicetree/bindings/watchdog/nuvoton,npcm-wdt.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/watchdog/nuvoton,npcm-wdt.txt b/Documentation/devicetree/bindings/watchdog/nuvoton,npcm-wdt.txt
index 9059f54dc023..866a958b8a2b 100644
--- a/Documentation/devicetree/bindings/watchdog/nuvoton,npcm-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/nuvoton,npcm-wdt.txt
@@ -6,7 +6,8 @@ expiry.
Required properties:
- compatible : "nuvoton,npcm750-wdt" for NPCM750 (Poleg), or
- "nuvoton,wpcm450-wdt" for WPCM450 (Hermon).
+ "nuvoton,wpcm450-wdt" for WPCM450 (Hermon), or
+ "nuvoton,npcm845-wdt" for NPCM845 (Arbel).
- reg : Offset and length of the register set for the device.
- interrupts : Contain the timer interrupt with flags for
falling edge.
--
2.33.0
Add a compatible string for Nuvoton BMC NPCM845 timer.
Signed-off-by: Tomer Maimon <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
---
.../devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml b/Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml
index 0cbc26a72151..737af78ad70c 100644
--- a/Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml
+++ b/Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml
@@ -8,12 +8,14 @@ title: Nuvoton NPCM7xx timer
maintainers:
- Jonathan Neuschäfer <[email protected]>
+ - Tomer Maimon <[email protected]>
properties:
compatible:
enum:
- nuvoton,wpcm450-timer # for Hermon WPCM450
- nuvoton,npcm750-timer # for Poleg NPCM750
+ - nuvoton,npcm845-timer # for Arbel NPCM845
reg:
maxItems: 1
--
2.33.0
Add a compatible string for Nuvoton BMC NPCM845 UART.
Signed-off-by: Tomer Maimon <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
---
Documentation/devicetree/bindings/serial/8250.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/serial/8250.yaml b/Documentation/devicetree/bindings/serial/8250.yaml
index 5f6b113d378f..6258f5f59b19 100644
--- a/Documentation/devicetree/bindings/serial/8250.yaml
+++ b/Documentation/devicetree/bindings/serial/8250.yaml
@@ -62,6 +62,7 @@ properties:
- const: mrvl,pxa-uart
- const: nuvoton,wpcm450-uart
- const: nuvoton,npcm750-uart
+ - const: nuvoton,npcm845-uart
- const: nvidia,tegra20-uart
- const: nxp,lpc3220-uart
- items:
--
2.33.0
Enable basic drivers for NPCM8XX booting up support: Architecture, Clock,
and WD.
Signed-off-by: Tomer Maimon <[email protected]>
---
arch/arm64/configs/defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 7d1105343bc2..c4a237a84efa 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -49,6 +49,7 @@ CONFIG_ARCH_MEDIATEK=y
CONFIG_ARCH_MESON=y
CONFIG_ARCH_MVEBU=y
CONFIG_ARCH_MXC=y
+CONFIG_ARCH_NPCM=y
CONFIG_ARCH_QCOM=y
CONFIG_ARCH_RENESAS=y
CONFIG_ARCH_ROCKCHIP=y
@@ -627,6 +628,7 @@ CONFIG_RENESAS_RZG2LWDT=y
CONFIG_UNIPHIER_WATCHDOG=y
CONFIG_PM8916_WATCHDOG=m
CONFIG_BCM2835_WDT=y
+CONFIG_NPCM7XX_WATCHDOG=y
CONFIG_MFD_ALTERA_SYSMGR=y
CONFIG_MFD_BD9571MWV=y
CONFIG_MFD_AXP20X_I2C=y
@@ -1021,6 +1023,7 @@ CONFIG_COMMON_CLK_FSL_SAI=y
CONFIG_COMMON_CLK_S2MPS11=y
CONFIG_COMMON_CLK_PWM=y
CONFIG_COMMON_CLK_VC5=y
+CONFIG_COMMON_CLK_NPCM8XX=y
CONFIG_COMMON_CLK_BD718XX=m
CONFIG_CLK_RASPBERRYPI=m
CONFIG_CLK_IMX8MM=y
--
2.33.0
Describe syscon property that handles general control registers (GCR) in
Nuvoton BMC NPCM reset driver.
Signed-off-by: Tomer Maimon <[email protected]>
---
.../devicetree/bindings/reset/nuvoton,npcm750-reset.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/reset/nuvoton,npcm750-reset.yaml b/Documentation/devicetree/bindings/reset/nuvoton,npcm750-reset.yaml
index fa5e4ea6400e..7ba3a6ff82ed 100644
--- a/Documentation/devicetree/bindings/reset/nuvoton,npcm750-reset.yaml
+++ b/Documentation/devicetree/bindings/reset/nuvoton,npcm750-reset.yaml
@@ -19,6 +19,9 @@ properties:
'#reset-cells':
const: 2
+ nuvoton,sysgcr:
+ description: a phandle to access GCR registers.
+
nuvoton,sw-reset-number:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 1
@@ -31,6 +34,7 @@ required:
- compatible
- reg
- '#reset-cells'
+ - nuvoton,sysgcr
additionalProperties: false
@@ -41,6 +45,7 @@ examples:
compatible = "nuvoton,npcm750-reset";
reg = <0xf0801000 0x70>;
#reset-cells = <2>;
+ nuvoton,sysgcr = <&gcr>;
nuvoton,sw-reset-number = <2>;
};
--
2.33.0
Add a compatible string for Nuvoton BMC NPCM845 SoC and a board specific
device tree for the NPCM845 (Arbel) evaluation board.
Signed-off-by: Tomer Maimon <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
---
Documentation/devicetree/bindings/arm/npcm/npcm.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/npcm/npcm.yaml b/Documentation/devicetree/bindings/arm/npcm/npcm.yaml
index ea9c3103761d..43409e5721d5 100644
--- a/Documentation/devicetree/bindings/arm/npcm/npcm.yaml
+++ b/Documentation/devicetree/bindings/arm/npcm/npcm.yaml
@@ -27,4 +27,10 @@ properties:
- nuvoton,npcm750-evb # NPCM750 evaluation board
- const: nuvoton,npcm750
+ - description: NPCM845 based boards
+ items:
+ - enum:
+ - nuvoton,npcm845-evb # NPCM845 evaluation board
+ - const: nuvoton,npcm845
+
additionalProperties: true
--
2.33.0
This adds support for the Nuvoton NPCM8XX Board Management
controller (BMC) SoC family.
The NPCM8XX based quad-core Cortex-A35 ARMv8 architecture.
Signed-off-by: Tomer Maimon <[email protected]>
---
MAINTAINERS | 2 ++
arch/arm64/Kconfig.platforms | 11 +++++++++++
2 files changed, 13 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index f52543aedd61..69cb86b913cf 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2448,9 +2448,11 @@ F: Documentation/devicetree/bindings/*/*npcm*
F: Documentation/devicetree/bindings/arm/npcm/*
F: arch/arm/boot/dts/nuvoton-npcm*
F: arch/arm/mach-npcm/
+F: arch/arm64/boot/dts/nuvoton/
F: drivers/*/*npcm*
F: drivers/*/*/*npcm*
F: include/dt-bindings/clock/nuvoton,npcm7xx-clock.h
+F: include/dt-bindings/clock/nuvoton,npcm8xx-clock.h
ARM/NUVOTON WPCM450 ARCHITECTURE
M: Jonathan Neuschäfer <[email protected]>
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 4e6d635a1731..c68d1b4f8975 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -202,6 +202,17 @@ config ARCH_MXC
This enables support for the ARMv8 based SoCs in the
NXP i.MX family.
+config ARCH_NPCM
+ bool "Nuvoton NPCM Architecture"
+ select PINCTRL
+ select GPIOLIB
+ select NPCM7XX_TIMER
+ select RESET_CONTROLLER
+ select MFD_SYSCON
+ help
+ General support for NPCM8xx BMC (Arbel).
+ Nuvoton NPCM8xx BMC based on the Cortex A35.
+
config ARCH_QCOM
bool "Qualcomm Platforms"
select GPIOLIB
--
2.33.0
On 19/06/2022 17:12, Tomer Maimon wrote:
> Describe syscon property that handles general control registers (GCR) in
> Nuvoton BMC NPCM reset driver.
>
> Signed-off-by: Tomer Maimon <[email protected]>
> ---
> .../devicetree/bindings/reset/nuvoton,npcm750-reset.yaml | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/reset/nuvoton,npcm750-reset.yaml b/Documentation/devicetree/bindings/reset/nuvoton,npcm750-reset.yaml
> index fa5e4ea6400e..7ba3a6ff82ed 100644
> --- a/Documentation/devicetree/bindings/reset/nuvoton,npcm750-reset.yaml
> +++ b/Documentation/devicetree/bindings/reset/nuvoton,npcm750-reset.yaml
> @@ -19,6 +19,9 @@ properties:
> '#reset-cells':
> const: 2
>
> + nuvoton,sysgcr:
> + description: a phandle to access GCR registers.
That's not valid. You miss here ref. My comment was to skip quotes and
you removed entire ref.
Best regards,
Krzysztof
On 19/06/2022 17:12, Tomer Maimon wrote:
> Enable basic drivers for NPCM8XX booting up support: Architecture, Clock,
> and WD.
>
> Signed-off-by: Tomer Maimon <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
Hi Krzysztof,
On Mon, 20 Jun 2022 at 11:22, Krzysztof Kozlowski
<[email protected]> wrote:
>
> On 19/06/2022 17:12, Tomer Maimon wrote:
> > Describe syscon property that handles general control registers (GCR) in
> > Nuvoton BMC NPCM reset driver.
> >
> > Signed-off-by: Tomer Maimon <[email protected]>
> > ---
> > .../devicetree/bindings/reset/nuvoton,npcm750-reset.yaml | 5 +++++
> > 1 file changed, 5 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/reset/nuvoton,npcm750-reset.yaml b/Documentation/devicetree/bindings/reset/nuvoton,npcm750-reset.yaml
> > index fa5e4ea6400e..7ba3a6ff82ed 100644
> > --- a/Documentation/devicetree/bindings/reset/nuvoton,npcm750-reset.yaml
> > +++ b/Documentation/devicetree/bindings/reset/nuvoton,npcm750-reset.yaml
> > @@ -19,6 +19,9 @@ properties:
> > '#reset-cells':
> > const: 2
> >
> > + nuvoton,sysgcr:
> > + description: a phandle to access GCR registers.
>
> That's not valid. You miss here ref. My comment was to skip quotes and
> you removed entire ref.
Will add the ref next version.
>
> Best regards,
> Krzysztof
Best regards,
Tomer