STM32MP13 is STM32 SOC with 2 GMACs instances
GMAC IP version is SNPS 4.20.
GMAC IP configure with 1 RX and 1 TX queue.
DMA HW capability register supported
RX Checksum Offload Engine supported
TX Checksum insertion supported
Wake-Up On Lan supported
TSO supported
Rework dwmac glue to simplify management for next stm32 (integrate RFC from Marek)
V2: - Remark from Rob Herring (add Krzysztof's ack in patch 02/11, update in yaml)
Remark from Serge Semin (upate commits msg)
V3: - Remove PHY regulator patch and Ethernet2 DT because need to clarify how to
manage PHY regulator (in glue or PHY side)
- Integrate RFC from Marek
- Remark from Rob Herring in YAML documentation
Christophe Roullier (6):
dt-bindings: net: add STM32MP13 compatible in documentation for stm32
net: ethernet: stmmac: add management of stm32mp13 for stm32
ARM: dts: stm32: add ethernet1 and ethernet2 support on stm32mp13
ARM: dts: stm32: add ethernet1/2 RMII pins for STM32MP13F-DK board
ARM: dts: stm32: add ethernet1 for STM32MP135F-DK board
ARM: multi_v7_defconfig: Add MCP23S08 pinctrl support
Marek Vasut (5):
net: stmmac: dwmac-stm32: Separate out external clock rate validation
net: stmmac: dwmac-stm32: Separate out external clock selector
net: stmmac: dwmac-stm32: Extract PMCR configuration
net: stmmac: dwmac-stm32: Clean up the debug prints
net: stmmac: dwmac-stm32: Fix Mhz to MHz
.../devicetree/bindings/net/stm32-dwmac.yaml | 41 +++-
arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi | 71 +++++++
arch/arm/boot/dts/st/stm32mp131.dtsi | 31 +++
arch/arm/boot/dts/st/stm32mp133.dtsi | 30 +++
arch/arm/boot/dts/st/stm32mp135f-dk.dts | 24 +++
arch/arm/configs/multi_v7_defconfig | 1 +
.../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 176 ++++++++++++++----
7 files changed, 327 insertions(+), 47 deletions(-)
--
2.25.1
Add Ethernet support for STM32MP13.
STM32MP13 is STM32 SOC with 2 GMACs instances.
GMAC IP version is SNPS 4.20.
GMAC IP configure with 1 RX and 1 TX queue.
DMA HW capability register supported
RX Checksum Offload Engine supported
TX Checksum insertion supported
Wake-Up On Lan supported
TSO supported
Signed-off-by: Christophe Roullier <[email protected]>
---
.../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 51 +++++++++++++++----
1 file changed, 41 insertions(+), 10 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
index 260b5eb27b07c..10c199729ec58 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
@@ -84,12 +84,14 @@ struct stm32_dwmac {
struct clk *clk_eth_ck;
struct clk *clk_ethstp;
struct clk *syscfg_clk;
+ bool is_mp13;
int ext_phyclk;
int enable_eth_ck;
int eth_clk_sel_reg;
int eth_ref_clk_sel_reg;
int irq_pwr_wakeup;
u32 mode_reg; /* MAC glue-logic mode register */
+ u32 mode_mask;
struct regmap *regmap;
u32 speed;
const struct stm32_ops *ops;
@@ -102,8 +104,8 @@ struct stm32_ops {
void (*resume)(struct stm32_dwmac *dwmac);
int (*parse_data)(struct stm32_dwmac *dwmac,
struct device *dev);
- u32 syscfg_eth_mask;
bool clk_rx_enable_in_suspend;
+ u32 syscfg_clr_off;
};
static int stm32_dwmac_clk_enable(struct stm32_dwmac *dwmac, bool resume)
@@ -230,7 +232,14 @@ static int stm32mp1_configure_pmcr(struct plat_stmmacenet_data *plat_dat)
switch (plat_dat->mac_interface) {
case PHY_INTERFACE_MODE_MII:
- val = SYSCFG_PMCR_ETH_SEL_MII;
+ /*
+ * STM32MP15xx supports both MII and GMII, STM32MP13xx MII only.
+ * SYSCFG_PMCSETR ETH_SELMII is present only on STM32MP15xx and
+ * acts as a selector between 0:GMII and 1:MII. As STM32MP13xx
+ * supports only MII, ETH_SELMII is not present.
+ */
+ if (!dwmac->is_mp13) /* Select MII mode on STM32MP15xx */
+ val |= SYSCFG_PMCR_ETH_SEL_MII;
break;
case PHY_INTERFACE_MODE_GMII:
val = SYSCFG_PMCR_ETH_SEL_GMII;
@@ -259,13 +268,17 @@ static int stm32mp1_configure_pmcr(struct plat_stmmacenet_data *plat_dat)
dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->mac_interface));
+ /* Shift value at correct ethernet MAC offset in SYSCFG_PMCSETR */
+ val <<= ffs(dwmac->mode_mask) - ffs(SYSCFG_MP1_ETH_MASK);
+
/* Need to update PMCCLRR (clear register) */
- regmap_write(dwmac->regmap, reg + SYSCFG_PMCCLRR_OFFSET,
- dwmac->ops->syscfg_eth_mask);
+ regmap_write(dwmac->regmap, dwmac->ops->syscfg_clr_off,
+ dwmac->mode_mask);
/* Update PMCSETR (set register) */
return regmap_update_bits(dwmac->regmap, reg,
- dwmac->ops->syscfg_eth_mask, val);
+ dwmac->mode_mask, val);
}
static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat)
@@ -306,7 +319,7 @@ static int stm32mcu_set_mode(struct plat_stmmacenet_data *plat_dat)
dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->mac_interface));
return regmap_update_bits(dwmac->regmap, reg,
- dwmac->ops->syscfg_eth_mask, val << 23);
+ SYSCFG_MCU_ETH_MASK, val << 23);
}
static void stm32_dwmac_clk_disable(struct stm32_dwmac *dwmac, bool suspend)
@@ -351,8 +364,15 @@ static int stm32_dwmac_parse_data(struct stm32_dwmac *dwmac,
return PTR_ERR(dwmac->regmap);
err = of_property_read_u32_index(np, "st,syscon", 1, &dwmac->mode_reg);
- if (err)
+ if (err) {
dev_err(dev, "Can't get sysconfig mode offset (%d)\n", err);
+ return err;
+ }
+
+ dwmac->mode_mask = SYSCFG_MP1_ETH_MASK;
+ err = of_property_read_u32_index(np, "st,syscon", 2, &dwmac->mode_mask);
+ if (err)
+ pr_debug("Warning sysconfig register mask not set\n");
return err;
}
@@ -364,6 +384,8 @@ static int stm32mp1_parse_data(struct stm32_dwmac *dwmac,
struct device_node *np = dev->of_node;
int err = 0;
+ dwmac->is_mp13 = of_device_is_compatible(np, "st,stm32mp13-dwmac");
+
/* Ethernet PHY have no crystal */
dwmac->ext_phyclk = of_property_read_bool(np, "st,ext-phyclk");
@@ -543,8 +565,7 @@ static SIMPLE_DEV_PM_OPS(stm32_dwmac_pm_ops,
stm32_dwmac_suspend, stm32_dwmac_resume);
static struct stm32_ops stm32mcu_dwmac_data = {
- .set_mode = stm32mcu_set_mode,
- .syscfg_eth_mask = SYSCFG_MCU_ETH_MASK
+ .set_mode = stm32mcu_set_mode
};
static struct stm32_ops stm32mp1_dwmac_data = {
@@ -552,13 +573,23 @@ static struct stm32_ops stm32mp1_dwmac_data = {
.suspend = stm32mp1_suspend,
.resume = stm32mp1_resume,
.parse_data = stm32mp1_parse_data,
- .syscfg_eth_mask = SYSCFG_MP1_ETH_MASK,
+ .syscfg_clr_off = 0x44,
+ .clk_rx_enable_in_suspend = true
+};
+
+static struct stm32_ops stm32mp13_dwmac_data = {
+ .set_mode = stm32mp1_set_mode,
+ .suspend = stm32mp1_suspend,
+ .resume = stm32mp1_resume,
+ .parse_data = stm32mp1_parse_data,
+ .syscfg_clr_off = 0x08,
.clk_rx_enable_in_suspend = true
};
static const struct of_device_id stm32_dwmac_match[] = {
{ .compatible = "st,stm32-dwmac", .data = &stm32mcu_dwmac_data},
{ .compatible = "st,stm32mp1-dwmac", .data = &stm32mp1_dwmac_data},
+ { .compatible = "st,stm32mp13-dwmac", .data = &stm32mp13_dwmac_data},
{ }
};
MODULE_DEVICE_TABLE(of, stm32_dwmac_match);
--
2.25.1
New STM32 SOC have 2 GMACs instances.
GMAC IP version is SNPS 4.20.
Signed-off-by: Christophe Roullier <[email protected]>
---
.../devicetree/bindings/net/stm32-dwmac.yaml | 41 +++++++++++++++----
1 file changed, 34 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
index 7ccf75676b6d5..ecbed9a7aaf6d 100644
--- a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
+++ b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
@@ -22,18 +22,17 @@ select:
enum:
- st,stm32-dwmac
- st,stm32mp1-dwmac
+ - st,stm32mp13-dwmac
required:
- compatible
-allOf:
- - $ref: snps,dwmac.yaml#
-
properties:
compatible:
oneOf:
- items:
- enum:
- st,stm32mp1-dwmac
+ - st,stm32mp13-dwmac
- const: snps,dwmac-4.20a
- items:
- enum:
@@ -75,12 +74,15 @@ properties:
st,syscon:
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
- - items:
+ - minItems: 2
+ items:
- description: phandle to the syscon node which encompases the glue register
- description: offset of the control register
+ - description: field to set mask in register
description:
Should be phandle/offset pair. The phandle to the syscon node which
- encompases the glue register, and the offset of the control register
+ encompases the glue register, the offset of the control register and
+ the mask to set bitfield in control register
st,ext-phyclk:
description:
@@ -112,12 +114,37 @@ required:
unevaluatedProperties: false
+allOf:
+ - $ref: snps,dwmac.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - st,stm32mp1-dwmac
+ - st,stm32-dwmac
+ then:
+ properties:
+ st,syscon:
+ items:
+ maxItems: 2
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - st,stm32mp13-dwmac
+ then:
+ properties:
+ st,syscon:
+ items:
+ minItems: 3
+
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/stm32mp1-clks.h>
- #include <dt-bindings/reset/stm32mp1-resets.h>
- #include <dt-bindings/mfd/stm32h7-rcc.h>
//Example 1
ethernet0: ethernet@5800a000 {
compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
--
2.25.1
From: Marek Vasut <[email protected]>
Use dev_err()/dev_dbg() and phy_modes() to print PHY mode instead of
pr_debug() and hand-written PHY mode decoding. This way, each debug
print has associated device with it and duplicated mode decoding is
removed.
Signed-off-by: Marek Vasut <[email protected]>
---
.../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 18 ++++++++----------
1 file changed, 8 insertions(+), 10 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
index 3fedb447970a6..91e1a540616d1 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
@@ -231,19 +231,16 @@ static int stm32mp1_configure_pmcr(struct plat_stmmacenet_data *plat_dat)
switch (plat_dat->mac_interface) {
case PHY_INTERFACE_MODE_MII:
val = SYSCFG_PMCR_ETH_SEL_MII;
- pr_debug("SYSCFG init : PHY_INTERFACE_MODE_MII\n");
break;
case PHY_INTERFACE_MODE_GMII:
val = SYSCFG_PMCR_ETH_SEL_GMII;
if (dwmac->enable_eth_ck)
val |= SYSCFG_PMCR_ETH_CLK_SEL;
- pr_debug("SYSCFG init : PHY_INTERFACE_MODE_GMII\n");
break;
case PHY_INTERFACE_MODE_RMII:
val = SYSCFG_PMCR_ETH_SEL_RMII;
if (dwmac->enable_eth_ck)
val |= SYSCFG_PMCR_ETH_REF_CLK_SEL;
- pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RMII\n");
break;
case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_ID:
@@ -252,15 +249,16 @@ static int stm32mp1_configure_pmcr(struct plat_stmmacenet_data *plat_dat)
val = SYSCFG_PMCR_ETH_SEL_RGMII;
if (dwmac->enable_eth_ck)
val |= SYSCFG_PMCR_ETH_CLK_SEL;
- pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RGMII\n");
break;
default:
- pr_debug("SYSCFG init : Do not manage %d interface\n",
- plat_dat->mac_interface);
+ dev_err(dwmac->dev, "Mode %s not supported",
+ phy_modes(plat_dat->mac_interface));
/* Do not manage others interfaces */
return -EINVAL;
}
+ dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->mac_interface));
+
/* Need to update PMCCLRR (clear register) */
regmap_write(dwmac->regmap, reg + SYSCFG_PMCCLRR_OFFSET,
dwmac->ops->syscfg_eth_mask);
@@ -294,19 +292,19 @@ static int stm32mcu_set_mode(struct plat_stmmacenet_data *plat_dat)
switch (plat_dat->mac_interface) {
case PHY_INTERFACE_MODE_MII:
val = SYSCFG_MCU_ETH_SEL_MII;
- pr_debug("SYSCFG init : PHY_INTERFACE_MODE_MII\n");
break;
case PHY_INTERFACE_MODE_RMII:
val = SYSCFG_MCU_ETH_SEL_RMII;
- pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RMII\n");
break;
default:
- pr_debug("SYSCFG init : Do not manage %d interface\n",
- plat_dat->mac_interface);
+ dev_err(dwmac->dev, "Mode %s not supported",
+ phy_modes(plat_dat->mac_interface));
/* Do not manage others interfaces */
return -EINVAL;
}
+ dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->mac_interface));
+
return regmap_update_bits(dwmac->regmap, reg,
dwmac->ops->syscfg_eth_mask, val << 23);
}
--
2.25.1
On 03/06/2024 11.27, Christophe Roullier wrote:
> @@ -259,13 +268,17 @@ static int stm32mp1_configure_pmcr(struct plat_stmmacenet_data *plat_dat)
>
> dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->mac_interface));
>
> + /* Shift value at correct ethernet MAC offset in SYSCFG_PMCSETR */
> + val <<= ffs(dwmac->mode_mask) - ffs(SYSCFG_MP1_ETH_MASK);
> +
> /* Need to update PMCCLRR (clear register) */
> - regmap_write(dwmac->regmap, reg + SYSCFG_PMCCLRR_OFFSET,
> - dwmac->ops->syscfg_eth_mask);
> + regmap_write(dwmac->regmap, dwmac->ops->syscfg_clr_off,
> + dwmac->mode_mask);
>
> /* Update PMCSETR (set register) */
> return regmap_update_bits(dwmac->regmap, reg,
> - dwmac->ops->syscfg_eth_mask, val);
> + dwmac->mode_mask, val);
> }
>
> static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat)
This hunk is broken, and makes the patch not apply:
Applying: net: ethernet: stmmac: add management of stm32mp13 for stm32
error: corrupt patch at line 70
The -259,13 seems correct, and the net lines added by previous hunks is
indeed +9, but this hunk only adds three more lines than it removes, not
four, so the +268,17 should have been +268,16.
Have you manually edited this patch before sending? If so, please don't
do that, it makes people waste a lot of time figuring out what is wrong.
Also, please include a base-id in the cover letter so one knows what it
applies to.
Finally, I think you also need to sign-off on the patches you send
authored by Marek.
Rasmus
On 6/3/24 1:30 PM, Rasmus Villemoes wrote:
> On 03/06/2024 11.27, Christophe Roullier wrote:
>
>> @@ -259,13 +268,17 @@ static int stm32mp1_configure_pmcr(struct plat_stmmacenet_data *plat_dat)
>>
>> dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->mac_interface));
>>
>> + /* Shift value at correct ethernet MAC offset in SYSCFG_PMCSETR */
>> + val <<= ffs(dwmac->mode_mask) - ffs(SYSCFG_MP1_ETH_MASK);
>> +
>> /* Need to update PMCCLRR (clear register) */
>> - regmap_write(dwmac->regmap, reg + SYSCFG_PMCCLRR_OFFSET,
>> - dwmac->ops->syscfg_eth_mask);
>> + regmap_write(dwmac->regmap, dwmac->ops->syscfg_clr_off,
>> + dwmac->mode_mask);
>>
>> /* Update PMCSETR (set register) */
>> return regmap_update_bits(dwmac->regmap, reg,
>> - dwmac->ops->syscfg_eth_mask, val);
>> + dwmac->mode_mask, val);
>> }
>>
>> static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat)
>
> This hunk is broken, and makes the patch not apply:
>
> Applying: net: ethernet: stmmac: add management of stm32mp13 for stm32
> error: corrupt patch at line 70
>
> The -259,13 seems correct, and the net lines added by previous hunks is
> indeed +9, but this hunk only adds three more lines than it removes, not
> four, so the +268,17 should have been +268,16.
>
> Have you manually edited this patch before sending? If so, please don't
> do that, it makes people waste a lot of time figuring out what is wrong.
>
> Also, please include a base-id in the cover letter so one knows what it
> applies to.
Just out of curiosity, I know one can generate cover letter from branch
description with git branch --edit-description and git format-patch
--cover-from-description= , but is there something to automatically fill
in the merge base (I assume that's what you want) ?
Or are you looking for git send-email --subject-prefix="net-next,PATCH"
to fill in the net/net-next subject prefix ?
On 03/06/2024 15.01, Marek Vasut wrote:
> On 6/3/24 1:30 PM, Rasmus Villemoes wrote:
>> Also, please include a base-id in the cover letter so one knows what it
>> applies to.
>
> Just out of curiosity, I know one can generate cover letter from branch
> description with git branch --edit-description and git format-patch
> --cover-from-description= , but is there something to automatically fill
> in the merge base (I assume that's what you want) ?
https://git-scm.com/docs/git-format-patch#_base_tree_information
Seems to have been in git since v2.9 (2016ish).
Rasmus
On 6/3/24 4:38 PM, Rasmus Villemoes wrote:
> On 03/06/2024 15.01, Marek Vasut wrote:
>> On 6/3/24 1:30 PM, Rasmus Villemoes wrote:
>
>>> Also, please include a base-id in the cover letter so one knows what it
>>> applies to.
>>
>> Just out of curiosity, I know one can generate cover letter from branch
>> description with git branch --edit-description and git format-patch
>> --cover-from-description= , but is there something to automatically fill
>> in the merge base (I assume that's what you want) ?
>
> https://git-scm.com/docs/git-format-patch#_base_tree_information
>
> Seems to have been in git since v2.9 (2016ish).
Nice, thanks !
On 6/3/24 13:30, Rasmus Villemoes wrote:
> On 03/06/2024 11.27, Christophe Roullier wrote:
>
>> @@ -259,13 +268,17 @@ static int stm32mp1_configure_pmcr(struct plat_stmmacenet_data *plat_dat)
>>
>> dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->mac_interface));
>>
>> + /* Shift value at correct ethernet MAC offset in SYSCFG_PMCSETR */
>> + val <<= ffs(dwmac->mode_mask) - ffs(SYSCFG_MP1_ETH_MASK);
>> +
>> /* Need to update PMCCLRR (clear register) */
>> - regmap_write(dwmac->regmap, reg + SYSCFG_PMCCLRR_OFFSET,
>> - dwmac->ops->syscfg_eth_mask);
>> + regmap_write(dwmac->regmap, dwmac->ops->syscfg_clr_off,
>> + dwmac->mode_mask);
>>
>> /* Update PMCSETR (set register) */
>> return regmap_update_bits(dwmac->regmap, reg,
>> - dwmac->ops->syscfg_eth_mask, val);
>> + dwmac->mode_mask, val);
>> }
>>
>> static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat)
> This hunk is broken, and makes the patch not apply:
>
> Applying: net: ethernet: stmmac: add management of stm32mp13 for stm32
> error: corrupt patch at line 70
>
> The -259,13 seems correct, and the net lines added by previous hunks is
> indeed +9, but this hunk only adds three more lines than it removes, not
> four, so the +268,17 should have been +268,16.
>
> Have you manually edited this patch before sending? If so, please don't
> do that, it makes people waste a lot of time figuring out what is wrong.
Hi Rasmus,
Yes sorry :-(
>
> Also, please include a base-id in the cover letter so one knows what it
> applies to.
>
> Finally, I think you also need to sign-off on the patches you send
> authored by Marek.
Yes, you are right
>
> Rasmus
>
On Mon, 03 Jun 2024 11:27:46 +0200, Christophe Roullier wrote:
> STM32MP13 is STM32 SOC with 2 GMACs instances
> GMAC IP version is SNPS 4.20.
> GMAC IP configure with 1 RX and 1 TX queue.
> DMA HW capability register supported
> RX Checksum Offload Engine supported
> TX Checksum insertion supported
> Wake-Up On Lan supported
> TSO supported
> Rework dwmac glue to simplify management for next stm32 (integrate RFC from Marek)
>
> V2: - Remark from Rob Herring (add Krzysztof's ack in patch 02/11, update in yaml)
> Remark from Serge Semin (upate commits msg)
> V3: - Remove PHY regulator patch and Ethernet2 DT because need to clarify how to
> manage PHY regulator (in glue or PHY side)
> - Integrate RFC from Marek
> - Remark from Rob Herring in YAML documentation
>
> Christophe Roullier (6):
> dt-bindings: net: add STM32MP13 compatible in documentation for stm32
> net: ethernet: stmmac: add management of stm32mp13 for stm32
> ARM: dts: stm32: add ethernet1 and ethernet2 support on stm32mp13
> ARM: dts: stm32: add ethernet1/2 RMII pins for STM32MP13F-DK board
> ARM: dts: stm32: add ethernet1 for STM32MP135F-DK board
> ARM: multi_v7_defconfig: Add MCP23S08 pinctrl support
>
> Marek Vasut (5):
> net: stmmac: dwmac-stm32: Separate out external clock rate validation
> net: stmmac: dwmac-stm32: Separate out external clock selector
> net: stmmac: dwmac-stm32: Extract PMCR configuration
> net: stmmac: dwmac-stm32: Clean up the debug prints
> net: stmmac: dwmac-stm32: Fix Mhz to MHz
>
> .../devicetree/bindings/net/stm32-dwmac.yaml | 41 +++-
> arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi | 71 +++++++
> arch/arm/boot/dts/st/stm32mp131.dtsi | 31 +++
> arch/arm/boot/dts/st/stm32mp133.dtsi | 30 +++
> arch/arm/boot/dts/st/stm32mp135f-dk.dts | 24 +++
> arch/arm/configs/multi_v7_defconfig | 1 +
> .../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 176 ++++++++++++++----
> 7 files changed, 327 insertions(+), 47 deletions(-)
>
> --
> 2.25.1
>
>
>
My bot found new DTB warnings on the .dts files added or changed in this
series.
Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.
If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:
pip3 install dtschema --upgrade
New warnings running 'make CHECK_DTBS=y st/stm32mp135f-dk.dtb' for [email protected]:
arch/arm/boot/dts/st/stm32mp135f-dk.dtb: adc@48003000: 'ethernet@5800e000' does not match any of the regexes: '^adc@[0-9]+$', 'pinctrl-[0-9]+'
from schema $id: http://devicetree.org/schemas/iio/adc/st,stm32-adc.yaml#