Drop the enable and frame_count parameters from dpu_hw_setup_misr() as they
are always set to the same values.
In addition, replace MISR_FRAME_COUNT_MASK with MISR_FRAME_COUNT as
frame_count is always set to the same value.
Fixes: 7b37523fb1d1 ("drm/msm/dpu: Move MISR methods to dpu_hw_util")
Reviewed-by: Dmitry Baryshkov <[email protected]>
Signed-off-by: Jessica Zhang <[email protected]>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 4 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 4 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 6 +++---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 4 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 6 +++---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h | 3 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 26 ++++++++------------------
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 9 +++------
8 files changed, 25 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 8ebed048a193..555182201b8e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2014-2021 The Linux Foundation. All rights reserved.
* Copyright (C) 2013 Red Hat
* Author: Rob Clark <[email protected]>
@@ -114,7 +114,7 @@ static void dpu_crtc_setup_lm_misr(struct dpu_crtc_state *crtc_state)
continue;
/* Calculate MISR over 1 frame */
- m->hw_lm->ops.setup_misr(m->hw_lm, true, 1);
+ m->hw_lm->ops.setup_misr(m->hw_lm);
}
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index aa1a1646b322..1d8eb3b509b4 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -2,7 +2,7 @@
/*
* Copyright (C) 2013 Red Hat
* Copyright (c) 2014-2018, 2020-2021 The Linux Foundation. All rights reserved.
- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Author: Rob Clark <[email protected]>
*/
@@ -258,7 +258,7 @@ void dpu_encoder_setup_misr(const struct drm_encoder *drm_enc)
if (!phys->hw_intf || !phys->hw_intf->ops.setup_misr)
continue;
- phys->hw_intf->ops.setup_misr(phys->hw_intf, true, 1);
+ phys->hw_intf->ops.setup_misr(phys->hw_intf);
}
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index 226133af7840..6bba531d6dc4 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
*/
@@ -320,9 +320,9 @@ static u32 dpu_hw_intf_get_line_count(struct dpu_hw_intf *intf)
return DPU_REG_READ(c, INTF_LINE_COUNT);
}
-static void dpu_hw_intf_setup_misr(struct dpu_hw_intf *intf, bool enable, u32 frame_count)
+static void dpu_hw_intf_setup_misr(struct dpu_hw_intf *intf)
{
- dpu_hw_setup_misr(&intf->hw, INTF_MISR_CTRL, enable, frame_count, 0x1);
+ dpu_hw_setup_misr(&intf->hw, INTF_MISR_CTRL, 0x1);
}
static int dpu_hw_intf_collect_misr(struct dpu_hw_intf *intf, u32 *misr_value)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
index 215401bb042e..0bd57a32144a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
*/
@@ -95,7 +95,7 @@ struct dpu_hw_intf_ops {
void (*bind_pingpong_blk)(struct dpu_hw_intf *intf,
const enum dpu_pingpong pp);
- void (*setup_misr)(struct dpu_hw_intf *intf, bool enable, u32 frame_count);
+ void (*setup_misr)(struct dpu_hw_intf *intf);
int (*collect_misr)(struct dpu_hw_intf *intf, u32 *misr_value);
// Tearcheck on INTF since DPU 5.0.0
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
index bbc9756ecde9..1d3ccf3228c6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
*/
@@ -83,9 +83,9 @@ static void dpu_hw_lm_setup_border_color(struct dpu_hw_mixer *ctx,
}
}
-static void dpu_hw_lm_setup_misr(struct dpu_hw_mixer *ctx, bool enable, u32 frame_count)
+static void dpu_hw_lm_setup_misr(struct dpu_hw_mixer *ctx)
{
- dpu_hw_setup_misr(&ctx->hw, LM_MISR_CTRL, enable, frame_count, 0x0);
+ dpu_hw_setup_misr(&ctx->hw, LM_MISR_CTRL, 0x0);
}
static int dpu_hw_lm_collect_misr(struct dpu_hw_mixer *ctx, u32 *misr_value)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h
index 8835fd106413..0a3381755249 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
*/
@@ -57,7 +58,7 @@ struct dpu_hw_lm_ops {
/**
* setup_misr: Enable/disable MISR
*/
- void (*setup_misr)(struct dpu_hw_mixer *ctx, bool enable, u32 frame_count);
+ void (*setup_misr)(struct dpu_hw_mixer *ctx);
/**
* collect_misr: Read MISR signature
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
index 87716a60332e..3b33a60c5c6b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
*/
#define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
@@ -476,9 +476,7 @@ void _dpu_hw_setup_qos_lut(struct dpu_hw_blk_reg_map *c, u32 offset,
}
void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c,
- u32 misr_ctrl_offset,
- bool enable, u32 frame_count,
- u32 input_sel)
+ u32 misr_ctrl_offset, u32 input_sel)
{
u32 config = 0;
@@ -487,20 +485,12 @@ void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c,
/* Clear old MISR value (in case it's read before a new value is calculated)*/
wmb();
- if (enable) {
- /*
- * note: Aside from encoders, input_sel should be
- * set to 0x0 by default
- */
- config = (frame_count & MISR_FRAME_COUNT_MASK) |
- MISR_CTRL_ENABLE | MISR_CTRL_FREE_RUN_MASK |
- ((input_sel & 0xF) << 24);
-
- DPU_REG_WRITE(c, misr_ctrl_offset, config);
- } else {
- DPU_REG_WRITE(c, misr_ctrl_offset, 0);
- }
-
+ /*
+ * note: Aside from encoders, input_sel should be set to 0x0 by default
+ */
+ config = MISR_FRAME_COUNT | MISR_CTRL_ENABLE | MISR_CTRL_FREE_RUN_MASK |
+ ((input_sel & 0xF) << 24);
+ DPU_REG_WRITE(c, misr_ctrl_offset, config);
}
int dpu_hw_collect_misr(struct dpu_hw_blk_reg_map *c,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
index 761056be272b..a561720f827d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
*/
@@ -13,7 +13,7 @@
#include "dpu_hw_catalog.h"
#define REG_MASK(n) ((BIT(n)) - 1)
-#define MISR_FRAME_COUNT_MASK 0xFF
+#define MISR_FRAME_COUNT 0x1
#define MISR_CTRL_ENABLE BIT(8)
#define MISR_CTRL_STATUS BIT(9)
#define MISR_CTRL_STATUS_CLEAR BIT(10)
@@ -355,10 +355,7 @@ void _dpu_hw_setup_qos_lut(struct dpu_hw_blk_reg_map *c, u32 offset,
const struct dpu_hw_qos_cfg *cfg);
void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c,
- u32 misr_ctrl_offset,
- bool enable,
- u32 frame_count,
- u32 input_sel);
+ u32 misr_ctrl_offset, u32 input_sel);
int dpu_hw_collect_misr(struct dpu_hw_blk_reg_map *c,
u32 misr_ctrl_offset,
--
2.43.0
On 12/13/2023 12:51 PM, Jessica Zhang wrote:
> Drop the enable and frame_count parameters from dpu_hw_setup_misr() as they
> are always set to the same values.
>
> In addition, replace MISR_FRAME_COUNT_MASK with MISR_FRAME_COUNT as
> frame_count is always set to the same value.
>
> Fixes: 7b37523fb1d1 ("drm/msm/dpu: Move MISR methods to dpu_hw_util")
> Reviewed-by: Dmitry Baryshkov <[email protected]>
> Signed-off-by: Jessica Zhang <[email protected]>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 4 ++--
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 4 ++--
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 6 +++---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 4 ++--
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 6 +++---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h | 3 ++-
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 26 ++++++++------------------
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 9 +++------
> 8 files changed, 25 insertions(+), 37 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> index 8ebed048a193..555182201b8e 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> @@ -1,6 +1,6 @@
> // SPDX-License-Identifier: GPL-2.0-only
> /*
> - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
> + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
> * Copyright (c) 2014-2021 The Linux Foundation. All rights reserved.
> * Copyright (C) 2013 Red Hat
> * Author: Rob Clark <[email protected]>
> @@ -114,7 +114,7 @@ static void dpu_crtc_setup_lm_misr(struct dpu_crtc_state *crtc_state)
> continue;
>
> /* Calculate MISR over 1 frame */
> - m->hw_lm->ops.setup_misr(m->hw_lm, true, 1);
> + m->hw_lm->ops.setup_misr(m->hw_lm);
> }
> }
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index aa1a1646b322..1d8eb3b509b4 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -2,7 +2,7 @@
> /*
> * Copyright (C) 2013 Red Hat
> * Copyright (c) 2014-2018, 2020-2021 The Linux Foundation. All rights reserved.
> - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
> + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
> *
> * Author: Rob Clark <[email protected]>
> */
> @@ -258,7 +258,7 @@ void dpu_encoder_setup_misr(const struct drm_encoder *drm_enc)
> if (!phys->hw_intf || !phys->hw_intf->ops.setup_misr)
> continue;
>
> - phys->hw_intf->ops.setup_misr(phys->hw_intf, true, 1);
> + phys->hw_intf->ops.setup_misr(phys->hw_intf);
> }
> }
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> index 226133af7840..6bba531d6dc4 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> @@ -1,6 +1,6 @@
> // SPDX-License-Identifier: GPL-2.0-only
> /*
> - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
> + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
> * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
> */
>
> @@ -320,9 +320,9 @@ static u32 dpu_hw_intf_get_line_count(struct dpu_hw_intf *intf)
> return DPU_REG_READ(c, INTF_LINE_COUNT);
> }
>
> -static void dpu_hw_intf_setup_misr(struct dpu_hw_intf *intf, bool enable, u32 frame_count)
> +static void dpu_hw_intf_setup_misr(struct dpu_hw_intf *intf)
> {
> - dpu_hw_setup_misr(&intf->hw, INTF_MISR_CTRL, enable, frame_count, 0x1);
> + dpu_hw_setup_misr(&intf->hw, INTF_MISR_CTRL, 0x1);
> }
>
> static int dpu_hw_intf_collect_misr(struct dpu_hw_intf *intf, u32 *misr_value)
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
> index 215401bb042e..0bd57a32144a 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
> @@ -1,6 +1,6 @@
> /* SPDX-License-Identifier: GPL-2.0-only */
> /*
> - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
> + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
> * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
> */
>
> @@ -95,7 +95,7 @@ struct dpu_hw_intf_ops {
>
> void (*bind_pingpong_blk)(struct dpu_hw_intf *intf,
> const enum dpu_pingpong pp);
> - void (*setup_misr)(struct dpu_hw_intf *intf, bool enable, u32 frame_count);
> + void (*setup_misr)(struct dpu_hw_intf *intf);
> int (*collect_misr)(struct dpu_hw_intf *intf, u32 *misr_value);
>
> // Tearcheck on INTF since DPU 5.0.0
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
> index bbc9756ecde9..1d3ccf3228c6 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
> @@ -1,6 +1,6 @@
> // SPDX-License-Identifier: GPL-2.0-only
> /*
> - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
> + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
> * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
> */
>
> @@ -83,9 +83,9 @@ static void dpu_hw_lm_setup_border_color(struct dpu_hw_mixer *ctx,
> }
> }
>
> -static void dpu_hw_lm_setup_misr(struct dpu_hw_mixer *ctx, bool enable, u32 frame_count)
> +static void dpu_hw_lm_setup_misr(struct dpu_hw_mixer *ctx)
> {
> - dpu_hw_setup_misr(&ctx->hw, LM_MISR_CTRL, enable, frame_count, 0x0);
> + dpu_hw_setup_misr(&ctx->hw, LM_MISR_CTRL, 0x0);
> }
>
> static int dpu_hw_lm_collect_misr(struct dpu_hw_mixer *ctx, u32 *misr_value)
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h
> index 8835fd106413..0a3381755249 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h
> @@ -1,5 +1,6 @@
> /* SPDX-License-Identifier: GPL-2.0-only */
> /*
> + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
> * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
> */
>
> @@ -57,7 +58,7 @@ struct dpu_hw_lm_ops {
> /**
> * setup_misr: Enable/disable MISR
> */
> - void (*setup_misr)(struct dpu_hw_mixer *ctx, bool enable, u32 frame_count);
> + void (*setup_misr)(struct dpu_hw_mixer *ctx);
>
> /**
> * collect_misr: Read MISR signature
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
> index 87716a60332e..3b33a60c5c6b 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
> @@ -1,6 +1,6 @@
> // SPDX-License-Identifier: GPL-2.0-only
> /*
> - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
> + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
> * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
> */
> #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
> @@ -476,9 +476,7 @@ void _dpu_hw_setup_qos_lut(struct dpu_hw_blk_reg_map *c, u32 offset,
> }
>
> void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c,
> - u32 misr_ctrl_offset,
> - bool enable, u32 frame_count,
> - u32 input_sel)
> + u32 misr_ctrl_offset, u32 input_sel)
I thought input_sel is going to be u8 now?
> {
> u32 config = 0;
>
> @@ -487,20 +485,12 @@ void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c,
> /* Clear old MISR value (in case it's read before a new value is calculated)*/
> wmb();
>
> - if (enable) {
> - /*
> - * note: Aside from encoders, input_sel should be
> - * set to 0x0 by default
> - */
> - config = (frame_count & MISR_FRAME_COUNT_MASK) |
> - MISR_CTRL_ENABLE | MISR_CTRL_FREE_RUN_MASK |
> - ((input_sel & 0xF) << 24);
> -
> - DPU_REG_WRITE(c, misr_ctrl_offset, config);
> - } else {
> - DPU_REG_WRITE(c, misr_ctrl_offset, 0);
> - }
> -
> + /*
> + * note: Aside from encoders, input_sel should be set to 0x0 by default
> + */
> + config = MISR_FRAME_COUNT | MISR_CTRL_ENABLE | MISR_CTRL_FREE_RUN_MASK |
> + ((input_sel & 0xF) << 24);
> + DPU_REG_WRITE(c, misr_ctrl_offset, config);
> }
>
> int dpu_hw_collect_misr(struct dpu_hw_blk_reg_map *c,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
> index 761056be272b..a561720f827d 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
> @@ -1,6 +1,6 @@
> /* SPDX-License-Identifier: GPL-2.0-only */
> /*
> - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
> + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
> * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
> */
>
> @@ -13,7 +13,7 @@
> #include "dpu_hw_catalog.h"
>
> #define REG_MASK(n) ((BIT(n)) - 1)
> -#define MISR_FRAME_COUNT_MASK 0xFF
> +#define MISR_FRAME_COUNT 0x1
> #define MISR_CTRL_ENABLE BIT(8)
> #define MISR_CTRL_STATUS BIT(9)
> #define MISR_CTRL_STATUS_CLEAR BIT(10)
> @@ -355,10 +355,7 @@ void _dpu_hw_setup_qos_lut(struct dpu_hw_blk_reg_map *c, u32 offset,
> const struct dpu_hw_qos_cfg *cfg);
>
> void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c,
> - u32 misr_ctrl_offset,
> - bool enable,
> - u32 frame_count,
> - u32 input_sel);
> + u32 misr_ctrl_offset, u32 input_sel);
>
> int dpu_hw_collect_misr(struct dpu_hw_blk_reg_map *c,
> u32 misr_ctrl_offset,
>
On 12/13/2023 1:00 PM, Abhinav Kumar wrote:
>
>
> On 12/13/2023 12:51 PM, Jessica Zhang wrote:
>> Drop the enable and frame_count parameters from dpu_hw_setup_misr() as
>> they
>> are always set to the same values.
>>
>> In addition, replace MISR_FRAME_COUNT_MASK with MISR_FRAME_COUNT as
>> frame_count is always set to the same value.
>>
>> Fixes: 7b37523fb1d1 ("drm/msm/dpu: Move MISR methods to dpu_hw_util")
>> Reviewed-by: Dmitry Baryshkov <[email protected]>
>> Signed-off-by: Jessica Zhang <[email protected]>
>> ---
>> drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 4 ++--
>> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 4 ++--
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 6 +++---
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 4 ++--
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 6 +++---
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h | 3 ++-
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 26
>> ++++++++------------------
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 9 +++------
>> 8 files changed, 25 insertions(+), 37 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>> index 8ebed048a193..555182201b8e 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>> @@ -1,6 +1,6 @@
>> // SPDX-License-Identifier: GPL-2.0-only
>> /*
>> - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights
>> reserved.
>> + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All
>> rights reserved.
>> * Copyright (c) 2014-2021 The Linux Foundation. All rights reserved.
>> * Copyright (C) 2013 Red Hat
>> * Author: Rob Clark <[email protected]>
>> @@ -114,7 +114,7 @@ static void dpu_crtc_setup_lm_misr(struct
>> dpu_crtc_state *crtc_state)
>> continue;
>> /* Calculate MISR over 1 frame */
>> - m->hw_lm->ops.setup_misr(m->hw_lm, true, 1);
>> + m->hw_lm->ops.setup_misr(m->hw_lm);
>> }
>> }
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>> index aa1a1646b322..1d8eb3b509b4 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>> @@ -2,7 +2,7 @@
>> /*
>> * Copyright (C) 2013 Red Hat
>> * Copyright (c) 2014-2018, 2020-2021 The Linux Foundation. All
>> rights reserved.
>> - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights
>> reserved.
>> + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All
>> rights reserved.
>> *
>> * Author: Rob Clark <[email protected]>
>> */
>> @@ -258,7 +258,7 @@ void dpu_encoder_setup_misr(const struct
>> drm_encoder *drm_enc)
>> if (!phys->hw_intf || !phys->hw_intf->ops.setup_misr)
>> continue;
>> - phys->hw_intf->ops.setup_misr(phys->hw_intf, true, 1);
>> + phys->hw_intf->ops.setup_misr(phys->hw_intf);
>> }
>> }
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
>> index 226133af7840..6bba531d6dc4 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
>> @@ -1,6 +1,6 @@
>> // SPDX-License-Identifier: GPL-2.0-only
>> /*
>> - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights
>> reserved.
>> + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All
>> rights reserved.
>> * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
>> */
>> @@ -320,9 +320,9 @@ static u32 dpu_hw_intf_get_line_count(struct
>> dpu_hw_intf *intf)
>> return DPU_REG_READ(c, INTF_LINE_COUNT);
>> }
>> -static void dpu_hw_intf_setup_misr(struct dpu_hw_intf *intf, bool
>> enable, u32 frame_count)
>> +static void dpu_hw_intf_setup_misr(struct dpu_hw_intf *intf)
>> {
>> - dpu_hw_setup_misr(&intf->hw, INTF_MISR_CTRL, enable, frame_count,
>> 0x1);
>> + dpu_hw_setup_misr(&intf->hw, INTF_MISR_CTRL, 0x1);
>> }
>> static int dpu_hw_intf_collect_misr(struct dpu_hw_intf *intf, u32
>> *misr_value)
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
>> index 215401bb042e..0bd57a32144a 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
>> @@ -1,6 +1,6 @@
>> /* SPDX-License-Identifier: GPL-2.0-only */
>> /*
>> - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights
>> reserved.
>> + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All
>> rights reserved.
>> * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
>> */
>> @@ -95,7 +95,7 @@ struct dpu_hw_intf_ops {
>> void (*bind_pingpong_blk)(struct dpu_hw_intf *intf,
>> const enum dpu_pingpong pp);
>> - void (*setup_misr)(struct dpu_hw_intf *intf, bool enable, u32
>> frame_count);
>> + void (*setup_misr)(struct dpu_hw_intf *intf);
>> int (*collect_misr)(struct dpu_hw_intf *intf, u32 *misr_value);
>> // Tearcheck on INTF since DPU 5.0.0
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
>> index bbc9756ecde9..1d3ccf3228c6 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
>> @@ -1,6 +1,6 @@
>> // SPDX-License-Identifier: GPL-2.0-only
>> /*
>> - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights
>> reserved.
>> + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All
>> rights reserved.
>> * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
>> */
>> @@ -83,9 +83,9 @@ static void dpu_hw_lm_setup_border_color(struct
>> dpu_hw_mixer *ctx,
>> }
>> }
>> -static void dpu_hw_lm_setup_misr(struct dpu_hw_mixer *ctx, bool
>> enable, u32 frame_count)
>> +static void dpu_hw_lm_setup_misr(struct dpu_hw_mixer *ctx)
>> {
>> - dpu_hw_setup_misr(&ctx->hw, LM_MISR_CTRL, enable, frame_count, 0x0);
>> + dpu_hw_setup_misr(&ctx->hw, LM_MISR_CTRL, 0x0);
>> }
>> static int dpu_hw_lm_collect_misr(struct dpu_hw_mixer *ctx, u32
>> *misr_value)
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h
>> index 8835fd106413..0a3381755249 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h
>> @@ -1,5 +1,6 @@
>> /* SPDX-License-Identifier: GPL-2.0-only */
>> /*
>> + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All
>> rights reserved.
>> * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
>> */
>> @@ -57,7 +58,7 @@ struct dpu_hw_lm_ops {
>> /**
>> * setup_misr: Enable/disable MISR
>> */
>> - void (*setup_misr)(struct dpu_hw_mixer *ctx, bool enable, u32
>> frame_count);
>> + void (*setup_misr)(struct dpu_hw_mixer *ctx);
>> /**
>> * collect_misr: Read MISR signature
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
>> index 87716a60332e..3b33a60c5c6b 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
>> @@ -1,6 +1,6 @@
>> // SPDX-License-Identifier: GPL-2.0-only
>> /*
>> - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights
>> reserved.
>> + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All
>> rights reserved.
>> * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
>> */
>> #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
>> @@ -476,9 +476,7 @@ void _dpu_hw_setup_qos_lut(struct
>> dpu_hw_blk_reg_map *c, u32 offset,
>> }
>> void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c,
>> - u32 misr_ctrl_offset,
>> - bool enable, u32 frame_count,
>> - u32 input_sel)
>> + u32 misr_ctrl_offset, u32 input_sel)
>
> I thought input_sel is going to be u8 now?
Ah, thanks for catching this -- had it as u32 in an older version and
forgot to change to u8. Will push a v3.
Thanks,
Jessica Zhang
>
>> {
>> u32 config = 0;
>> @@ -487,20 +485,12 @@ void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map
>> *c,
>> /* Clear old MISR value (in case it's read before a new value is
>> calculated)*/
>> wmb();
>> - if (enable) {
>> - /*
>> - * note: Aside from encoders, input_sel should be
>> - * set to 0x0 by default
>> - */
>> - config = (frame_count & MISR_FRAME_COUNT_MASK) |
>> - MISR_CTRL_ENABLE | MISR_CTRL_FREE_RUN_MASK |
>> - ((input_sel & 0xF) << 24);
>> -
>> - DPU_REG_WRITE(c, misr_ctrl_offset, config);
>> - } else {
>> - DPU_REG_WRITE(c, misr_ctrl_offset, 0);
>> - }
>> -
>> + /*
>> + * note: Aside from encoders, input_sel should be set to 0x0 by
>> default
>> + */
>> + config = MISR_FRAME_COUNT | MISR_CTRL_ENABLE |
>> MISR_CTRL_FREE_RUN_MASK |
>> + ((input_sel & 0xF) << 24);
>> + DPU_REG_WRITE(c, misr_ctrl_offset, config);
>> }
>> int dpu_hw_collect_misr(struct dpu_hw_blk_reg_map *c,
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
>> index 761056be272b..a561720f827d 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
>> @@ -1,6 +1,6 @@
>> /* SPDX-License-Identifier: GPL-2.0-only */
>> /*
>> - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights
>> reserved.
>> + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All
>> rights reserved.
>> * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
>> */
>> @@ -13,7 +13,7 @@
>> #include "dpu_hw_catalog.h"
>> #define REG_MASK(n) ((BIT(n)) - 1)
>> -#define MISR_FRAME_COUNT_MASK 0xFF
>> +#define MISR_FRAME_COUNT 0x1
>> #define MISR_CTRL_ENABLE BIT(8)
>> #define MISR_CTRL_STATUS BIT(9)
>> #define MISR_CTRL_STATUS_CLEAR BIT(10)
>> @@ -355,10 +355,7 @@ void _dpu_hw_setup_qos_lut(struct
>> dpu_hw_blk_reg_map *c, u32 offset,
>> const struct dpu_hw_qos_cfg *cfg);
>> void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c,
>> - u32 misr_ctrl_offset,
>> - bool enable,
>> - u32 frame_count,
>> - u32 input_sel);
>> + u32 misr_ctrl_offset, u32 input_sel);
>> int dpu_hw_collect_misr(struct dpu_hw_blk_reg_map *c,
>> u32 misr_ctrl_offset,
>>