On 04/11/2022 10:20, Johan Hovold wrote:
> There are three UFS reference clocks on SC8280XP which are used as
> follows:
>
> - The GCC_UFS_REF_CLKREF_CLK clock is fed to any UFS device connected
> to either controller.
>
> - The GCC_UFS_1_CARD_CLKREF_CLK and GCC_UFS_CARD_CLKREF_CLK clocks
> provide reference clocks to the two PHYs.
>
> Note that this depends on first updating the clock driver to reflect
> that all three clocks are sourced from CXO. Specifically, the UFS
> controller driver expects the device reference clock to have a valid
> frequency:
>
> ufshcd-qcom 1d84000.ufs: invalid ref_clk setting = 0
>
> Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform")
> Fixes: 8d6b458ce6e9 ("arm64: dts: qcom: sc8280xp: fix ufs_card_phy ref clock")
> Fixes: f3aa975e230e ("arm64: dts: qcom: sc8280xp: correct ref clock for ufs_mem_phy")
> Link: https://lore.kernel.org/lkml/[email protected]/
> Cc: [email protected] # 5.20
> Signed-off-by: Johan Hovold <[email protected]>
> ---
Reviewed-by: Konrad Dybcio <[email protected]>
Konrad
> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> index 21ac119e0382..e0d0fb6994b5 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> @@ -912,7 +912,7 @@ ufs_mem_hc: ufs@1d84000 {
> <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
> <&gcc GCC_UFS_PHY_AHB_CLK>,
> <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
> - <&rpmhcc RPMH_CXO_CLK>,
> + <&gcc GCC_UFS_REF_CLKREF_CLK>,
> <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
> <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
> <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
> @@ -943,7 +943,7 @@ ufs_mem_phy: phy@1d87000 {
> ranges;
> clock-names = "ref",
> "ref_aux";
> - clocks = <&gcc GCC_UFS_REF_CLKREF_CLK>,
> + clocks = <&gcc GCC_UFS_CARD_CLKREF_CLK>,
> <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
>
> resets = <&ufs_mem_hc 0>;
> @@ -980,7 +980,7 @@ ufs_card_hc: ufs@1da4000 {
> <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>,
> <&gcc GCC_UFS_CARD_AHB_CLK>,
> <&gcc GCC_UFS_CARD_UNIPRO_CORE_CLK>,
> - <&rpmhcc RPMH_CXO_CLK>,
> + <&gcc GCC_UFS_REF_CLKREF_CLK>,
> <&gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>,
> <&gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>,
> <&gcc GCC_UFS_CARD_RX_SYMBOL_1_CLK>;
> @@ -1011,7 +1011,7 @@ ufs_card_phy: phy@1da7000 {
> ranges;
> clock-names = "ref",
> "ref_aux";
> - clocks = <&gcc GCC_UFS_REF_CLKREF_CLK>,
> + clocks = <&gcc GCC_UFS_1_CARD_CLKREF_CLK>,
> <&gcc GCC_UFS_CARD_PHY_AUX_CLK>;
>
> resets = <&ufs_card_hc 0>;