Until recently Intel CPUs didn't support using non-contiguous 1s
in Cache Allocation Technology (CAT). Writing a bitmask with
non-contiguous 1s to the resctrl schemata file would fail.
Intel CPUs that support non-contiguous 1s can be identified through a
CPUID leaf mentioned in the "Intel® 64 and IA-32 Architectures
Software Developer’s Manual" document available at:
https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html
Add kernel support for detecting if non-contiguous 1s in Cache
Allocation Technology (CAT) are supported by the hardware. Also add a
new resctrl FS file to output this information to the userspace.
Keep the hardcoded value for Haswell CPUs only since they do not have
CPUID enumeration support for Cache allocation.
Unify variable names to match the "bitmask" convention rather than the
"bitmap" one to ensure consistency.
Since the selftests/resctrl files are going through many rewrites and
cleanups the appropriate selftest is still a work in progress. For
basic selftesting capabilities use the bash script attached below this
paragraph. It checks whether various bitmasks written into resctrl FS
generate output consistent with reported feature support.
#!/bin/bash
# must be run as root, depends on a recent cpuid tool (20230406 or later)
# variables
RESCTRL_INFO="/sys/fs/resctrl/info"
L3_NON_CONT_VAL="${RESCTRL_INFO}/L3/sparse_masks"
L2_NON_CONT_VAL="${RESCTRL_INFO}/L2/sparse_masks"
L3_NON_CONT_CBM="${RESCTRL_INFO}/L3/cbm_mask"
L2_NON_CONT_CBM="${RESCTRL_INFO}/L2/cbm_mask"
L3_CPUID_CMD="cpuid -1 -l 0x10 -s 0x01"
L2_CPUID_CMD="cpuid -1 -l 0x10 -s 0x02"
PASSED_TESTS=0
L3_SUPPORT=0
L2_SUPPORT=0
TESTS=0
run_test() {
# L2 or L3
CACHE_LEVEL=$1
CACHE_LEVEL_SUPPORT="${CACHE_LEVEL}_SUPPORT"
echo "Checking ${RESCTRL_INFO}/${CACHE_LEVEL}..."
if [[ -d "${RESCTRL_INFO}/${CACHE_LEVEL}" ]]; then
eval "${CACHE_LEVEL_SUPPORT}=1"
echo "${CACHE_LEVEL} CAT Feature is supported"
else
echo "${CACHE_LEVEL} CAT Feature is not supported"
fi
if [[ ${!CACHE_LEVEL_SUPPORT} -eq 1 ]]; then
echo " --- Running tests for ${CACHE_LEVEL} CAT ---"
# read sysfs entries
# are non-contiguous cbm supported? (driver sysfs)
eval "NON_CONT_VAL=${CACHE_LEVEL}_NON_CONT_VAL"
eval "NON_CONT_FEAT=$( cat ${!NON_CONT_VAL} )"
# are non-contiguous cbm supported? (cpuid)
CACHE_CPUID_CMD="${CACHE_LEVEL}_CPUID_CMD"
NONCONT_CPUID=$(${!CACHE_CPUID_CMD} | grep non-contiguous | grep true)
NONCONT_CPUID_RET=$(( !$? ))
# what is the mask size?
eval "NON_CONT_CBM=${CACHE_LEVEL}_NON_CONT_CBM"
MAX_MASK=$(( 16#$( cat ${!NON_CONT_CBM} ) ))
# prepare contiguous and non-contiguous masks for tests
BC_STRING="l(${MAX_MASK})/l(2)"
MAX_MASK_BIT_COUNT=$(echo ${BC_STRING} | bc -l)
MAX_MASK_BIT_COUNT=$(printf "%.0f" "$MAX_MASK_BIT_COUNT")
BITSHIFT=$(( $MAX_MASK_BIT_COUNT/2 - ($MAX_MASK_BIT_COUNT/2 % 4) ))
CONT_MASK=$(( $MAX_MASK >> $BITSHIFT ))
NONCONT_MASK=$(( ~( $MAX_MASK & ( 15<<$BITSHIFT) ) ))
NONCONT_MASK=$(( $NONCONT_MASK & $MAX_MASK ))
# test if cpuid reported support matches the sysfs one
echo " * Testing if CPUID matches ${CACHE_LEVEL}/sparse_masks..."
TESTS=$((TESTS + 1))
if [[ $NONCONT_CPUID_RET -eq $NON_CONT_FEAT ]]; then
PASSED_TESTS=$((PASSED_TESTS + 1))
echo "There is a match!"
else
echo "Error - no match!"
fi
# test by writing CBMs to the schemata
printf " * Writing 0x%x mask to the schemata...\n" ${CONT_MASK}
TESTS=$((TESTS + 1))
SCHEMATA=$(printf "${CACHE_LEVEL}:0=%x" $CONT_MASK)
echo "$SCHEMATA" > /sys/fs/resctrl/schemata
if [[ $? -eq 0 ]]; then
PASSED_TESTS=$((PASSED_TESTS + 1))
echo "Contiguous ${CACHE_LEVEL} write correct!"
else
echo "Contiguous ${CACHE_LEVEL} write ERROR!"
fi
printf " * Writing 0x%x mask to the schemata...\n" ${NONCONT_MASK}
TESTS=$((TESTS + 1))
SCHEMATA=$(printf "${CACHE_LEVEL}:0=%x" $NONCONT_MASK)
echo "$SCHEMATA" > /sys/fs/resctrl/schemata
if [[ (($? -eq 0) && ($NON_CONT_FEAT -eq 1)) || \
(($? -ne 0) && ($NON_CONT_FEAT -eq 0)) ]]; then
PASSED_TESTS=$((PASSED_TESTS + 1))
echo "Non-contiguous ${CACHE_LEVEL} write correct!"
else
echo "Non-contiguous ${CACHE_LEVEL} write ERROR!"
fi
fi
}
# mount resctrl
mount -t resctrl resctrl /sys/fs/resctrl
run_test L3
run_test L2
echo "TESTS PASSED / ALL TESTS : ${PASSED_TESTS} / ${TESTS}"
# unmount resctrl
umount /sys/fs/resctrl
The series is based on tip/master branch.
Changelog v5:
- Rephrase patch messages (patches 1/4 and 2/4) according to Borislav's
comments on Babu's [1] series.
- Remove redundant message paragraph from patch 4/4.
- Rebase onto tip/master.
- Add Babu's reviewed-by tags.
Changelog v4:
- Add Ilpo's reviewed-by tags.
- Add Reinette's reviewed-by tags.
- Reorder tags in alignment with maintainer-tip.rst.
Changelog v3:
- Add Peter's tested-by and reviewed-by tags.
- Change patch order to make 4th one the 1st.
- Add error checking to schema_len variable.
- Update cover letter since now the feature has moved from the SDM.
Changelog v2:
- Change git signature from Wieczor-Retman Maciej to Maciej
Wieczor-Retman.
- Change bitmap naming convention to bit mask.
- Add patch to change arch_has_sparce_bitmaps name to match bitmask
naming convention.
[1] https://lore.kernel.org/all/[email protected]/
Fenghua Yu (2):
x86/resctrl: Add sparse_masks file in info
Documentation/x86: Document resctrl's new sparse_masks
Maciej Wieczor-Retman (2):
x86/resctrl: Rename arch_has_sparse_bitmaps
x86/resctrl: Enable non-contiguous CBMs in Intel CAT
Documentation/arch/x86/resctrl.rst | 16 ++++++++++++----
arch/x86/kernel/cpu/resctrl/core.c | 11 +++++++----
arch/x86/kernel/cpu/resctrl/ctrlmondata.c | 14 ++++++++------
arch/x86/kernel/cpu/resctrl/internal.h | 9 +++++++++
arch/x86/kernel/cpu/resctrl/rdtgroup.c | 18 ++++++++++++++++++
include/linux/resctrl.h | 4 ++--
6 files changed, 56 insertions(+), 16 deletions(-)
base-commit: ef19bc9dddc3727dec1efa08683f658b1f4b7b78
--
2.42.0
Rename arch_has_sparse_bitmaps to arch_has_sparse_bitmasks to ensure
consistent terminology throughout resctrl.
Suggested-by: Reinette Chatre <[email protected]>
Signed-off-by: Maciej Wieczor-Retman <[email protected]>
Tested-by: Peter Newman <[email protected]>
Reviewed-by: Ilpo Järvinen <[email protected]>
Reviewed-by: Peter Newman <[email protected]>
Reviewed-by: Reinette Chatre <[email protected]>
Reviewed-by: Babu Moger <[email protected]>
---
Changelog v5:
- Add Babu's reviewed-by tag.
- Remove part of the patch message that refrences a later patch.
Changelog v4:
- Add Ilpo's reviewed-by tag.
- Add Reinette's reviewed-by tag.
Changelog v3:
- Add Peter's tested-by and reviewed-by tags.
- Make this patch first in the series. (Reinette)
- Change the patch message. (Reinette)
- Drop rmid_busy_llc comment name change. (Reinette)
Changelog v2:
- Create this patch.
arch/x86/kernel/cpu/resctrl/core.c | 4 ++--
arch/x86/kernel/cpu/resctrl/ctrlmondata.c | 4 ++--
include/linux/resctrl.h | 4 ++--
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c
index 030d3b409768..c09e4fdded3c 100644
--- a/arch/x86/kernel/cpu/resctrl/core.c
+++ b/arch/x86/kernel/cpu/resctrl/core.c
@@ -872,7 +872,7 @@ static __init void rdt_init_res_defs_intel(void)
if (r->rid == RDT_RESOURCE_L3 ||
r->rid == RDT_RESOURCE_L2) {
- r->cache.arch_has_sparse_bitmaps = false;
+ r->cache.arch_has_sparse_bitmasks = false;
r->cache.arch_has_per_cpu_cfg = false;
r->cache.min_cbm_bits = 1;
} else if (r->rid == RDT_RESOURCE_MBA) {
@@ -892,7 +892,7 @@ static __init void rdt_init_res_defs_amd(void)
if (r->rid == RDT_RESOURCE_L3 ||
r->rid == RDT_RESOURCE_L2) {
- r->cache.arch_has_sparse_bitmaps = true;
+ r->cache.arch_has_sparse_bitmasks = true;
r->cache.arch_has_per_cpu_cfg = true;
r->cache.min_cbm_bits = 0;
} else if (r->rid == RDT_RESOURCE_MBA) {
diff --git a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c
index b44c487727d4..ab45012288bb 100644
--- a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c
+++ b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c
@@ -113,8 +113,8 @@ static bool cbm_validate(char *buf, u32 *data, struct rdt_resource *r)
first_bit = find_first_bit(&val, cbm_len);
zero_bit = find_next_zero_bit(&val, cbm_len, first_bit);
- /* Are non-contiguous bitmaps allowed? */
- if (!r->cache.arch_has_sparse_bitmaps &&
+ /* Are non-contiguous bitmasks allowed? */
+ if (!r->cache.arch_has_sparse_bitmasks &&
(find_next_bit(&val, cbm_len, zero_bit) < cbm_len)) {
rdt_last_cmd_printf("The mask %lx has non-consecutive 1-bits\n", val);
return false;
diff --git a/include/linux/resctrl.h b/include/linux/resctrl.h
index 8334eeacfec5..66942d7fba7f 100644
--- a/include/linux/resctrl.h
+++ b/include/linux/resctrl.h
@@ -94,7 +94,7 @@ struct rdt_domain {
* zero CBM.
* @shareable_bits: Bitmask of shareable resource with other
* executing entities
- * @arch_has_sparse_bitmaps: True if a bitmap like f00f is valid.
+ * @arch_has_sparse_bitmasks: True if a bitmask like f00f is valid.
* @arch_has_per_cpu_cfg: True if QOS_CFG register for this cache
* level has CPU scope.
*/
@@ -102,7 +102,7 @@ struct resctrl_cache {
unsigned int cbm_len;
unsigned int min_cbm_bits;
unsigned int shareable_bits;
- bool arch_has_sparse_bitmaps;
+ bool arch_has_sparse_bitmasks;
bool arch_has_per_cpu_cfg;
};
--
2.42.0
The setting for non-contiguous 1s support in Intel CAT is
hardcoded to false. On these systems, writing non-contiguous
1s into the schemata file will fail before resctrl passes
the value to the hardware.
In Intel CAT CPUID.0x10.1:ECX[3] and CPUID.0x10.2:ECX[3] stopped
being reserved and now carry information about non-contiguous 1s
value support for L3 and L2 cache respectively. The CAT
capacity bitmask (CBM) supports a non-contiguous 1s value if
the bit is set.
The exception are Haswell systems where non-contiguous 1s value
support needs to stay disabled since they can't make use of CPUID
for Cache allocation.
Originally-by: Fenghua Yu <[email protected]>
Signed-off-by: Maciej Wieczor-Retman <[email protected]>
Tested-by: Peter Newman <[email protected]>
Reviewed-by: Ilpo Järvinen <[email protected]>
Reviewed-by: Peter Newman <[email protected]>
Reviewed-by: Reinette Chatre <[email protected]>
Reviewed-by: Babu Moger <[email protected]>
---
Changelog v5:
- Add Babu's reviewed-by tag.
- Rephrase the patch message to avoid redundancy with the patch content.
Changelog v4:
- Add Ilpo's reviewed-by tag.
- Add Reinette's reviewed-by tag.
Changelog v3:
- Add Peter's tested-by and reviewed-by tags.
- Change patch subject to mention CBMs. (Babu)
Changelog v2:
- Rewrite part of a comment concerning Haswell. (Reinette)
arch/x86/kernel/cpu/resctrl/core.c | 9 ++++++---
arch/x86/kernel/cpu/resctrl/ctrlmondata.c | 10 ++++++----
arch/x86/kernel/cpu/resctrl/internal.h | 9 +++++++++
3 files changed, 21 insertions(+), 7 deletions(-)
diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c
index c09e4fdded3c..19e0681f0435 100644
--- a/arch/x86/kernel/cpu/resctrl/core.c
+++ b/arch/x86/kernel/cpu/resctrl/core.c
@@ -152,6 +152,7 @@ static inline void cache_alloc_hsw_probe(void)
r->cache.cbm_len = 20;
r->cache.shareable_bits = 0xc0000;
r->cache.min_cbm_bits = 2;
+ r->cache.arch_has_sparse_bitmasks = false;
r->alloc_capable = true;
rdt_alloc_capable = true;
@@ -267,15 +268,18 @@ static void rdt_get_cache_alloc_cfg(int idx, struct rdt_resource *r)
{
struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r);
union cpuid_0x10_1_eax eax;
+ union cpuid_0x10_x_ecx ecx;
union cpuid_0x10_x_edx edx;
- u32 ebx, ecx;
+ u32 ebx;
- cpuid_count(0x00000010, idx, &eax.full, &ebx, &ecx, &edx.full);
+ cpuid_count(0x00000010, idx, &eax.full, &ebx, &ecx.full, &edx.full);
hw_res->num_closid = edx.split.cos_max + 1;
r->cache.cbm_len = eax.split.cbm_len + 1;
r->default_ctrl = BIT_MASK(eax.split.cbm_len + 1) - 1;
r->cache.shareable_bits = ebx & r->default_ctrl;
r->data_width = (r->cache.cbm_len + 3) / 4;
+ if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
+ r->cache.arch_has_sparse_bitmasks = ecx.split.noncont;
r->alloc_capable = true;
}
@@ -872,7 +876,6 @@ static __init void rdt_init_res_defs_intel(void)
if (r->rid == RDT_RESOURCE_L3 ||
r->rid == RDT_RESOURCE_L2) {
- r->cache.arch_has_sparse_bitmasks = false;
r->cache.arch_has_per_cpu_cfg = false;
r->cache.min_cbm_bits = 1;
} else if (r->rid == RDT_RESOURCE_MBA) {
diff --git a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c
index ab45012288bb..beccb0e87ba7 100644
--- a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c
+++ b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c
@@ -87,10 +87,12 @@ int parse_bw(struct rdt_parse_data *data, struct resctrl_schema *s,
/*
* Check whether a cache bit mask is valid.
- * For Intel the SDM says:
- * Please note that all (and only) contiguous '1' combinations
- * are allowed (e.g. FFFFH, 0FF0H, 003CH, etc.).
- * Additionally Haswell requires at least two bits set.
+ * On Intel CPUs, non-contiguous 1s value support is indicated by CPUID:
+ * - CPUID.0x10.1:ECX[3]: L3 non-contiguous 1s value supported if 1
+ * - CPUID.0x10.2:ECX[3]: L2 non-contiguous 1s value supported if 1
+ *
+ * Haswell does not support a non-contiguous 1s value and additionally
+ * requires at least two bits set.
* AMD allows non-contiguous bitmasks.
*/
static bool cbm_validate(char *buf, u32 *data, struct rdt_resource *r)
diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/resctrl/internal.h
index 85ceaf9a31ac..c47ef2f13e8e 100644
--- a/arch/x86/kernel/cpu/resctrl/internal.h
+++ b/arch/x86/kernel/cpu/resctrl/internal.h
@@ -492,6 +492,15 @@ union cpuid_0x10_3_eax {
unsigned int full;
};
+/* CPUID.(EAX=10H, ECX=ResID).ECX */
+union cpuid_0x10_x_ecx {
+ struct {
+ unsigned int reserved:3;
+ unsigned int noncont:1;
+ } split;
+ unsigned int full;
+};
+
/* CPUID.(EAX=10H, ECX=ResID).EDX */
union cpuid_0x10_x_edx {
struct {
--
2.42.0
From: Fenghua Yu <[email protected]>
Add the interface in resctrl FS to show if sparse cache allocation
bit masks are supported on the platform. Reading the file returns
either a "1" if non-contiguous 1s are supported and "0" otherwise.
The file path is /sys/fs/resctrl/info/{resource}/sparse_masks, where
{resource} can be either "L2" or "L3".
Signed-off-by: Fenghua Yu <[email protected]>
Signed-off-by: Maciej Wieczor-Retman <[email protected]>
Tested-by: Peter Newman <[email protected]>
Reviewed-by: Ilpo Järvinen <[email protected]>
Reviewed-by: Peter Newman <[email protected]>
Reviewed-by: Reinette Chatre <[email protected]>
Reviewed-by: Babu Moger <[email protected]>
---
Changelog v5:
- Add Babu's reviewed-by tag.
Changelog v4:
- Add Ilpo's reviewed-by tag.
- Add Reinette's reviewed-by tag.
Changelog v3:
- Add Peter's tested-by and reviewed-by tags.
- Reword patch message slightly. (Reinette)
Changelog v2:
- Change bitmap naming convention to bit mask. (Reinette)
- Change file name to "sparse_masks". (Reinette)
arch/x86/kernel/cpu/resctrl/rdtgroup.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/resctrl/rdtgroup.c
index 725344048f85..945801898a4d 100644
--- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c
+++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c
@@ -895,6 +895,17 @@ static int rdt_shareable_bits_show(struct kernfs_open_file *of,
return 0;
}
+static int rdt_has_sparse_bitmasks_show(struct kernfs_open_file *of,
+ struct seq_file *seq, void *v)
+{
+ struct resctrl_schema *s = of->kn->parent->priv;
+ struct rdt_resource *r = s->res;
+
+ seq_printf(seq, "%u\n", r->cache.arch_has_sparse_bitmasks);
+
+ return 0;
+}
+
/**
* rdt_bit_usage_show - Display current usage of resources
*
@@ -1839,6 +1850,13 @@ static struct rftype res_common_files[] = {
.seq_show = rdtgroup_size_show,
.fflags = RF_CTRL_BASE,
},
+ {
+ .name = "sparse_masks",
+ .mode = 0444,
+ .kf_ops = &rdtgroup_kf_single_ops,
+ .seq_show = rdt_has_sparse_bitmasks_show,
+ .fflags = RF_CTRL_INFO | RFTYPE_RES_CACHE,
+ },
};
--
2.42.0
From: Fenghua Yu <[email protected]>
The documentation mentions that non-contiguous bit masks are not
supported in Intel Cache Allocation Technology (CAT).
Update the documentation on how to determine if sparse bit masks are
allowed in L2 and L3 CAT.
Signed-off-by: Fenghua Yu <[email protected]>
Signed-off-by: Maciej Wieczor-Retman <[email protected]>
Tested-by: Peter Newman <[email protected]>
Reviewed-by: Ilpo Järvinen <[email protected]>
Reviewed-by: Peter Newman <[email protected]>
Reviewed-by: Reinette Chatre <[email protected]>
Reviewed-by: Babu Moger <[email protected]>
---
Changelog v5:
- Remove last patch message paragraph. (Babu)
- Add Babu's reviewed-by tag.
Changelog v4:
- Add Ilpo's reviewed-by tag.
- Add Reinette's reviewed-by tag.
Changelog v3:
- Add Peter's tested-by and reviewed-by tags.
Changelog v2:
- Change bitmap naming convention to bit mask. (Reinette)
Documentation/arch/x86/resctrl.rst | 16 ++++++++++++----
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/Documentation/arch/x86/resctrl.rst b/Documentation/arch/x86/resctrl.rst
index cb05d90111b4..4c6421e2aa31 100644
--- a/Documentation/arch/x86/resctrl.rst
+++ b/Documentation/arch/x86/resctrl.rst
@@ -124,6 +124,13 @@ related to allocation:
"P":
Corresponding region is pseudo-locked. No
sharing allowed.
+"sparse_masks":
+ Indicates if non-contiguous 1s value in CBM is supported.
+
+ "0":
+ Only contiguous 1s value in CBM is supported.
+ "1":
+ Non-contiguous 1s value in CBM is supported.
Memory bandwidth(MB) subdirectory contains the following files
with respect to allocation:
@@ -445,12 +452,13 @@ For cache resources we describe the portion of the cache that is available
for allocation using a bitmask. The maximum value of the mask is defined
by each cpu model (and may be different for different cache levels). It
is found using CPUID, but is also provided in the "info" directory of
-the resctrl file system in "info/{resource}/cbm_mask". Intel hardware
+the resctrl file system in "info/{resource}/cbm_mask". Some Intel hardware
requires that these masks have all the '1' bits in a contiguous block. So
0x3, 0x6 and 0xC are legal 4-bit masks with two bits set, but 0x5, 0x9
-and 0xA are not. On a system with a 20-bit mask each bit represents 5%
-of the capacity of the cache. You could partition the cache into four
-equal parts with masks: 0x1f, 0x3e0, 0x7c00, 0xf8000.
+and 0xA are not. Check /sys/fs/resctrl/info/{resource}/sparse_masks
+if non-contiguous 1s value is supported. On a system with a 20-bit mask
+each bit represents 5% of the capacity of the cache. You could partition
+the cache into four equal parts with masks: 0x1f, 0x3e0, 0x7c00, 0xf8000.
Memory bandwidth Allocation and monitoring
==========================================
--
2.42.0
Hi x86 maintainers,
Could you please consider this series for inclusion?
This is the second resctrl series that is now ready for your
consideration. The other series is Babu's work [1] that has already
been reviewed by Boris and we await a new version.
There is a merge conflict between the two series. I assume from
conversation with Boris [2] that you will decide which series to merge
first and then the other can be rebased on top. Please let us know how
you prefer to manage this.
Thank you very much.
Reinette
[1] https://lore.kernel.org/lkml/[email protected]/
[2] https://lore.kernel.org/lkml/20231009165403.GCZSQwKwjGifBIQTpq@fat_crate.local/
On 10/10/2023 3:42 AM, Maciej Wieczor-Retman wrote:
> Until recently Intel CPUs didn't support using non-contiguous 1s
> in Cache Allocation Technology (CAT). Writing a bitmask with
> non-contiguous 1s to the resctrl schemata file would fail.
>
> Intel CPUs that support non-contiguous 1s can be identified through a
> CPUID leaf mentioned in the "Intel® 64 and IA-32 Architectures
> Software Developer’s Manual" document available at:
> https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html
>
> Add kernel support for detecting if non-contiguous 1s in Cache
> Allocation Technology (CAT) are supported by the hardware. Also add a
> new resctrl FS file to output this information to the userspace.
> Keep the hardcoded value for Haswell CPUs only since they do not have
> CPUID enumeration support for Cache allocation.
>
> Unify variable names to match the "bitmask" convention rather than the
> "bitmap" one to ensure consistency.
>
> Since the selftests/resctrl files are going through many rewrites and
> cleanups the appropriate selftest is still a work in progress. For
> basic selftesting capabilities use the bash script attached below this
> paragraph. It checks whether various bitmasks written into resctrl FS
> generate output consistent with reported feature support.
>
> #!/bin/bash
> # must be run as root, depends on a recent cpuid tool (20230406 or later)
> # variables
> RESCTRL_INFO="/sys/fs/resctrl/info"
> L3_NON_CONT_VAL="${RESCTRL_INFO}/L3/sparse_masks"
> L2_NON_CONT_VAL="${RESCTRL_INFO}/L2/sparse_masks"
> L3_NON_CONT_CBM="${RESCTRL_INFO}/L3/cbm_mask"
> L2_NON_CONT_CBM="${RESCTRL_INFO}/L2/cbm_mask"
> L3_CPUID_CMD="cpuid -1 -l 0x10 -s 0x01"
> L2_CPUID_CMD="cpuid -1 -l 0x10 -s 0x02"
> PASSED_TESTS=0
> L3_SUPPORT=0
> L2_SUPPORT=0
> TESTS=0
>
> run_test() {
> # L2 or L3
> CACHE_LEVEL=$1
> CACHE_LEVEL_SUPPORT="${CACHE_LEVEL}_SUPPORT"
> echo "Checking ${RESCTRL_INFO}/${CACHE_LEVEL}..."
> if [[ -d "${RESCTRL_INFO}/${CACHE_LEVEL}" ]]; then
> eval "${CACHE_LEVEL_SUPPORT}=1"
> echo "${CACHE_LEVEL} CAT Feature is supported"
> else
> echo "${CACHE_LEVEL} CAT Feature is not supported"
> fi
>
> if [[ ${!CACHE_LEVEL_SUPPORT} -eq 1 ]]; then
> echo " --- Running tests for ${CACHE_LEVEL} CAT ---"
>
> # read sysfs entries
> # are non-contiguous cbm supported? (driver sysfs)
> eval "NON_CONT_VAL=${CACHE_LEVEL}_NON_CONT_VAL"
> eval "NON_CONT_FEAT=$( cat ${!NON_CONT_VAL} )"
>
> # are non-contiguous cbm supported? (cpuid)
> CACHE_CPUID_CMD="${CACHE_LEVEL}_CPUID_CMD"
> NONCONT_CPUID=$(${!CACHE_CPUID_CMD} | grep non-contiguous | grep true)
> NONCONT_CPUID_RET=$(( !$? ))
>
> # what is the mask size?
> eval "NON_CONT_CBM=${CACHE_LEVEL}_NON_CONT_CBM"
> MAX_MASK=$(( 16#$( cat ${!NON_CONT_CBM} ) ))
>
> # prepare contiguous and non-contiguous masks for tests
> BC_STRING="l(${MAX_MASK})/l(2)"
> MAX_MASK_BIT_COUNT=$(echo ${BC_STRING} | bc -l)
> MAX_MASK_BIT_COUNT=$(printf "%.0f" "$MAX_MASK_BIT_COUNT")
> BITSHIFT=$(( $MAX_MASK_BIT_COUNT/2 - ($MAX_MASK_BIT_COUNT/2 % 4) ))
> CONT_MASK=$(( $MAX_MASK >> $BITSHIFT ))
> NONCONT_MASK=$(( ~( $MAX_MASK & ( 15<<$BITSHIFT) ) ))
> NONCONT_MASK=$(( $NONCONT_MASK & $MAX_MASK ))
>
> # test if cpuid reported support matches the sysfs one
> echo " * Testing if CPUID matches ${CACHE_LEVEL}/sparse_masks..."
> TESTS=$((TESTS + 1))
> if [[ $NONCONT_CPUID_RET -eq $NON_CONT_FEAT ]]; then
> PASSED_TESTS=$((PASSED_TESTS + 1))
> echo "There is a match!"
> else
> echo "Error - no match!"
> fi
>
> # test by writing CBMs to the schemata
> printf " * Writing 0x%x mask to the schemata...\n" ${CONT_MASK}
> TESTS=$((TESTS + 1))
> SCHEMATA=$(printf "${CACHE_LEVEL}:0=%x" $CONT_MASK)
> echo "$SCHEMATA" > /sys/fs/resctrl/schemata
> if [[ $? -eq 0 ]]; then
> PASSED_TESTS=$((PASSED_TESTS + 1))
> echo "Contiguous ${CACHE_LEVEL} write correct!"
> else
> echo "Contiguous ${CACHE_LEVEL} write ERROR!"
> fi
>
> printf " * Writing 0x%x mask to the schemata...\n" ${NONCONT_MASK}
> TESTS=$((TESTS + 1))
> SCHEMATA=$(printf "${CACHE_LEVEL}:0=%x" $NONCONT_MASK)
> echo "$SCHEMATA" > /sys/fs/resctrl/schemata
> if [[ (($? -eq 0) && ($NON_CONT_FEAT -eq 1)) || \
> (($? -ne 0) && ($NON_CONT_FEAT -eq 0)) ]]; then
> PASSED_TESTS=$((PASSED_TESTS + 1))
> echo "Non-contiguous ${CACHE_LEVEL} write correct!"
> else
> echo "Non-contiguous ${CACHE_LEVEL} write ERROR!"
> fi
> fi
> }
>
> # mount resctrl
> mount -t resctrl resctrl /sys/fs/resctrl
>
> run_test L3
> run_test L2
>
> echo "TESTS PASSED / ALL TESTS : ${PASSED_TESTS} / ${TESTS}"
>
> # unmount resctrl
> umount /sys/fs/resctrl
>
> The series is based on tip/master branch.
>
> Changelog v5:
> - Rephrase patch messages (patches 1/4 and 2/4) according to Borislav's
> comments on Babu's [1] series.
> - Remove redundant message paragraph from patch 4/4.
> - Rebase onto tip/master.
> - Add Babu's reviewed-by tags.
>
> Changelog v4:
> - Add Ilpo's reviewed-by tags.
> - Add Reinette's reviewed-by tags.
> - Reorder tags in alignment with maintainer-tip.rst.
>
> Changelog v3:
> - Add Peter's tested-by and reviewed-by tags.
> - Change patch order to make 4th one the 1st.
> - Add error checking to schema_len variable.
> - Update cover letter since now the feature has moved from the SDM.
>
> Changelog v2:
> - Change git signature from Wieczor-Retman Maciej to Maciej
> Wieczor-Retman.
> - Change bitmap naming convention to bit mask.
> - Add patch to change arch_has_sparce_bitmaps name to match bitmask
> naming convention.
>
> [1] https://lore.kernel.org/all/[email protected]/
>
> Fenghua Yu (2):
> x86/resctrl: Add sparse_masks file in info
> Documentation/x86: Document resctrl's new sparse_masks
>
> Maciej Wieczor-Retman (2):
> x86/resctrl: Rename arch_has_sparse_bitmaps
> x86/resctrl: Enable non-contiguous CBMs in Intel CAT
>
> Documentation/arch/x86/resctrl.rst | 16 ++++++++++++----
> arch/x86/kernel/cpu/resctrl/core.c | 11 +++++++----
> arch/x86/kernel/cpu/resctrl/ctrlmondata.c | 14 ++++++++------
> arch/x86/kernel/cpu/resctrl/internal.h | 9 +++++++++
> arch/x86/kernel/cpu/resctrl/rdtgroup.c | 18 ++++++++++++++++++
> include/linux/resctrl.h | 4 ++--
> 6 files changed, 56 insertions(+), 16 deletions(-)
>
>
> base-commit: ef19bc9dddc3727dec1efa08683f658b1f4b7b78