2024-05-21 20:31:04

by Dmitry Baryshkov

Subject: [PATCH 1/2] phy: qcom: qmp-pcie: restore compatibility with existing DTs

Existing device trees specify only a single clock-output-name for the
PCIe PHYs. The function phy_aux_clk_register() expects a second entry in
that property. When it doesn't find it, it returns an error, thus
failing the probe of the PHY and thus breaking support for the
corresponding PCIe host.

Follow the approach of the combo USB+DT PHY and generate the name for
the AUX clocks instead of requiring it in DT.

Fixes: 583ca9ccfa80 ("phy: qcom: qmp-pcie: register second optional PHY AUX clock")
Signed-off-by: Dmitry Baryshkov <[email protected]>
---
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 9 +++------
1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index 6c796723c8f5..b4767b8cc014 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -3730,14 +3730,11 @@ static int phy_aux_clk_register(struct qmp_pcie *qmp, struct device_node *np)
{
struct clk_fixed_rate *fixed = &qmp->aux_clk_fixed;
struct clk_init_data init = { };
- int ret;
+ char name[64];

- ret = of_property_read_string_index(np, "clock-output-names", 1, &init.name);
- if (ret) {
- dev_err(qmp->dev, "%pOFn: No clock-output-names index 1\n", np);
- return ret;
- }
+ snprintf(name, sizeof(name), "%s::pipe_aux_clk", dev_name(qmp->dev));

+ init.name = name;
init.ops = &clk_fixed_rate_ops;

fixed->fixed_rate = qmp->cfg->aux_clock_rate;

--
2.39.2

2024-05-22 07:46:21

by Neil Armstrong

Subject: Re: [PATCH 1/2] phy: qcom: qmp-pcie: restore compatibility with existing DTs

On 21/05/2024 22:30, Dmitry Baryshkov wrote:
> Existing device trees specify only a single clock-output-name for the
> PCIe PHYs. The function phy_aux_clk_register() expects a second entry in
> that property. When it doesn't find it, it returns an error, thus
> failing the probe of the PHY and thus breaking support for the
> corresponding PCIe host.
>
> Follow the approach of the combo USB+DT PHY and generate the name for
> the AUX clocks instead of requiring it in DT.
>
> Fixes: 583ca9ccfa80 ("phy: qcom: qmp-pcie: register second optional PHY AUX clock")
> Signed-off-by: Dmitry Baryshkov <[email protected]>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 9 +++------
> 1 file changed, 3 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> index 6c796723c8f5..b4767b8cc014 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> @@ -3730,14 +3730,11 @@ static int phy_aux_clk_register(struct qmp_pcie *qmp, struct device_node *np)
> {
> struct clk_fixed_rate *fixed = &qmp->aux_clk_fixed;
> struct clk_init_data init = { };
> - int ret;
> + char name[64];
>
> - ret = of_property_read_string_index(np, "clock-output-names", 1, &init.name);
> - if (ret) {
> - dev_err(qmp->dev, "%pOFn: No clock-output-names index 1\n", np);
> - return ret;
> - }
> + snprintf(name, sizeof(name), "%s::pipe_aux_clk", dev_name(qmp->dev));

Should be "::phy_aux_clk"

>
> + init.name = name;
> init.ops = &clk_fixed_rate_ops;
>
> fixed->fixed_rate = qmp->cfg->aux_clock_rate;
>

With that:
Reviewed-by: Neil Armstrong <[email protected]>

Thanks,
Neil