2019-07-18 11:16:50

by Jan Kotas

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Subject: [PATCH 2/3] media: Add lane checks for Cadence CSI2TX

This patch adds line checks for CSI2TX, to prevent
clock lane being used as a data lane.

Signed-off-by: Jan Kotas <[email protected]>
---
drivers/media/platform/cadence/cdns-csi2tx.c | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/media/platform/cadence/cdns-csi2tx.c b/drivers/media/platform/cadence/cdns-csi2tx.c
index 5042d053b..232259c71 100644
--- a/drivers/media/platform/cadence/cdns-csi2tx.c
+++ b/drivers/media/platform/cadence/cdns-csi2tx.c
@@ -2,7 +2,7 @@
/*
* Driver for Cadence MIPI-CSI2 TX Controller
*
- * Copyright (C) 2017-2018 Cadence Design Systems Inc.
+ * Copyright (C) 2017-2019 Cadence Design Systems Inc.
*/

#include <linux/clk.h>
@@ -434,7 +434,7 @@ static int csi2tx_check_lanes(struct csi2tx_priv *csi2tx)
{
struct v4l2_fwnode_endpoint v4l2_ep = { .bus_type = 0 };
struct device_node *ep;
- int ret;
+ int ret, i;

ep = of_graph_get_endpoint_by_regs(csi2tx->dev->of_node, 0, 0);
if (!ep)
@@ -461,6 +461,15 @@ static int csi2tx_check_lanes(struct csi2tx_priv *csi2tx)
goto out;
}

+ for (i = 0; i < csi2tx->num_lanes; i++) {
+ if (v4l2_ep.bus.mipi_csi2.data_lanes[i] < 1) {
+ dev_err(csi2tx->dev, "Invalid lane[%d] number: %u\n",
+ i, v4l2_ep.bus.mipi_csi2.data_lanes[i]);
+ ret = -EINVAL;
+ goto out;
+ }
+ }
+
memcpy(csi2tx->lanes, v4l2_ep.bus.mipi_csi2.data_lanes,
sizeof(csi2tx->lanes));

--
2.15.0


2019-07-18 12:03:03

by Marc Gonzalez

[permalink] [raw]
Subject: Re: [PATCH 2/3] media: Add lane checks for Cadence CSI2TX

On 18/07/2019 13:15, Jan Kotas wrote:

> This patch adds line checks for CSI2TX, to prevent
> clock lane being used as a data lane.

"line checks" or "lane checks? ^_^

NB: commit messages may be up to 72-character-wide ;-)
(No need to line-wrap at 50)

Regards.

2019-07-18 12:09:26

by Jan Kotas

[permalink] [raw]
Subject: Re: [PATCH 2/3] media: Add lane checks for Cadence CSI2TX


> On 18 Jul 2019, at 13:52, Marc Gonzalez <[email protected]> wrote:
>
> EXTERNAL MAIL
>
>
> On 18/07/2019 13:15, Jan Kotas wrote:
>
>> This patch adds line checks for CSI2TX, to prevent
>> clock lane being used as a data lane.
>
> "line checks" or "lane checks? ^_^

Yes, you’re right, should be lane checks :)

Regards,
Jan

>
> NB: commit messages may be up to 72-character-wide ;-)
> (No need to line-wrap at 50)
>
> Regards.

2019-07-20 18:41:01

by Maxime Ripard

[permalink] [raw]
Subject: Re: [PATCH 2/3] media: Add lane checks for Cadence CSI2TX

65;5603;1c
On Thu, Jul 18, 2019 at 12:15:08PM +0100, Jan Kotas wrote:
> This patch adds line checks for CSI2TX, to prevent
> clock lane being used as a data lane.
>
> Signed-off-by: Jan Kotas <[email protected]>

Acked-by: Maxime Ripard <[email protected]>

Maxime

--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com


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