This series integrates the recent review feedback from Chanwoo Choi to
v7.
Chanwoo, I am sending the full patchset again for people to try this
series. You said that you applied 1-5 already, so please start picking
from 6/26.
Sascha
Sascha Hauer (26):
PM / devfreq: rockchip-dfi: Make pmu regmap mandatory
PM / devfreq: rockchip-dfi: Embed desc into private data struct
PM / devfreq: rockchip-dfi: use consistent name for private data
struct
PM / devfreq: rockchip-dfi: Add SoC specific init function
PM / devfreq: rockchip-dfi: dfi store raw values in counter struct
PM / devfreq: rockchip-dfi: Use free running counter
PM / devfreq: rockchip-dfi: introduce channel mask
PM / devfreq: rk3399_dmc,dfi: generalize DDRTYPE defines
PM / devfreq: rockchip-dfi: Clean up DDR type register defines
PM / devfreq: rockchip-dfi: Add RK3568 support
PM / devfreq: rockchip-dfi: Handle LPDDR2 correctly
PM / devfreq: rockchip-dfi: Handle LPDDR4X
PM / devfreq: rockchip-dfi: Pass private data struct to internal
functions
PM / devfreq: rockchip-dfi: Prepare for multiple users
PM / devfreq: rockchip-dfi: give variable a better name
PM / devfreq: rockchip-dfi: Add perf support
PM / devfreq: rockchip-dfi: make register stride SoC specific
PM / devfreq: rockchip-dfi: account for multiple DDRMON_CTRL registers
PM / devfreq: rockchip-dfi: add support for RK3588
dt-bindings: devfreq: event: convert Rockchip DFI binding to yaml
dt-bindings: devfreq: event: rockchip,dfi: Add rk3568 support
dt-bindings: devfreq: event: rockchip,dfi: Add rk3588 support
dt-bindings: soc: rockchip: grf: add rockchip,rk3588-pmugrf
arm64: dts: rockchip: rk3399: Enable DFI
arm64: dts: rockchip: rk356x: Add DFI
arm64: dts: rockchip: rk3588s: Add DFI
.../bindings/devfreq/event/rockchip,dfi.yaml | 74 ++
.../bindings/devfreq/event/rockchip-dfi.txt | 18 -
.../rockchip,rk3399-dmc.yaml | 2 +-
.../devicetree/bindings/soc/rockchip/grf.yaml | 1 +
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 1 -
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 7 +
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 16 +
drivers/devfreq/event/rockchip-dfi.c | 814 +++++++++++++++---
drivers/devfreq/rk3399_dmc.c | 10 +-
include/soc/rockchip/rk3399_grf.h | 9 +-
include/soc/rockchip/rk3568_grf.h | 13 +
include/soc/rockchip/rk3588_grf.h | 18 +
include/soc/rockchip/rockchip_grf.h | 18 +
13 files changed, 863 insertions(+), 138 deletions(-)
create mode 100644 Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml
delete mode 100644 Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt
create mode 100644 include/soc/rockchip/rk3568_grf.h
create mode 100644 include/soc/rockchip/rk3588_grf.h
create mode 100644 include/soc/rockchip/rockchip_grf.h
--
2.39.2
Add support for the RK3588 to the driver. The RK3588 has four DDR
channels with a register stride of 0x4000 between the channel
registers, also it has a DDRMON_CTRL register per channel.
Reviewed-by: Jonathan Cameron <[email protected]>
Reviewed-by: Sebastian Reichel <[email protected]>
Signed-off-by: Sascha Hauer <[email protected]>
---
drivers/devfreq/event/rockchip-dfi.c | 36 +++++++++++++++++++++++++++-
include/soc/rockchip/rk3588_grf.h | 18 ++++++++++++++
2 files changed, 53 insertions(+), 1 deletion(-)
create mode 100644 include/soc/rockchip/rk3588_grf.h
diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c
index bf38829a2a4af..794f36e7eebd1 100644
--- a/drivers/devfreq/event/rockchip-dfi.c
+++ b/drivers/devfreq/event/rockchip-dfi.c
@@ -26,8 +26,9 @@
#include <soc/rockchip/rockchip_grf.h>
#include <soc/rockchip/rk3399_grf.h>
#include <soc/rockchip/rk3568_grf.h>
+#include <soc/rockchip/rk3588_grf.h>
-#define DMC_MAX_CHANNELS 2
+#define DMC_MAX_CHANNELS 4
#define HIWORD_UPDATE(val, mask) ((val) | (mask) << 16)
@@ -723,9 +724,42 @@ static int rk3568_dfi_init(struct rockchip_dfi *dfi)
return 0;
};
+static int rk3588_dfi_init(struct rockchip_dfi *dfi)
+{
+ struct regmap *regmap_pmu = dfi->regmap_pmu;
+ u32 reg2, reg3, reg4;
+
+ regmap_read(regmap_pmu, RK3588_PMUGRF_OS_REG2, ®2);
+ regmap_read(regmap_pmu, RK3588_PMUGRF_OS_REG3, ®3);
+ regmap_read(regmap_pmu, RK3588_PMUGRF_OS_REG4, ®4);
+
+ /* lower 3 bits of the DDR type */
+ dfi->ddr_type = FIELD_GET(RK3588_PMUGRF_OS_REG2_DRAMTYPE_INFO, reg2);
+
+ /*
+ * For version three and higher the upper two bits of the DDR type are
+ * in RK3588_PMUGRF_OS_REG3
+ */
+ if (FIELD_GET(RK3588_PMUGRF_OS_REG3_SYSREG_VERSION, reg3) >= 0x3)
+ dfi->ddr_type |= FIELD_GET(RK3588_PMUGRF_OS_REG3_DRAMTYPE_INFO_V3, reg3) << 3;
+
+ dfi->buswidth[0] = FIELD_GET(RK3588_PMUGRF_OS_REG2_BW_CH0, reg2) == 0 ? 4 : 2;
+ dfi->buswidth[1] = FIELD_GET(RK3588_PMUGRF_OS_REG2_BW_CH1, reg2) == 0 ? 4 : 2;
+ dfi->buswidth[2] = FIELD_GET(RK3568_PMUGRF_OS_REG2_BW_CH0, reg4) == 0 ? 4 : 2;
+ dfi->buswidth[3] = FIELD_GET(RK3588_PMUGRF_OS_REG2_BW_CH1, reg4) == 0 ? 4 : 2;
+ dfi->channel_mask = FIELD_GET(RK3588_PMUGRF_OS_REG2_CH_INFO, reg2) |
+ FIELD_GET(RK3588_PMUGRF_OS_REG2_CH_INFO, reg4) << 2;
+ dfi->max_channels = 4;
+
+ dfi->ddrmon_stride = 0x4000;
+
+ return 0;
+};
+
static const struct of_device_id rockchip_dfi_id_match[] = {
{ .compatible = "rockchip,rk3399-dfi", .data = rk3399_dfi_init },
{ .compatible = "rockchip,rk3568-dfi", .data = rk3568_dfi_init },
+ { .compatible = "rockchip,rk3588-dfi", .data = rk3588_dfi_init },
{ },
};
diff --git a/include/soc/rockchip/rk3588_grf.h b/include/soc/rockchip/rk3588_grf.h
new file mode 100644
index 0000000000000..630b35a550640
--- /dev/null
+++ b/include/soc/rockchip/rk3588_grf.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+#ifndef __SOC_RK3588_GRF_H
+#define __SOC_RK3588_GRF_H
+
+#define RK3588_PMUGRF_OS_REG2 0x208
+#define RK3588_PMUGRF_OS_REG2_DRAMTYPE_INFO GENMASK(15, 13)
+#define RK3588_PMUGRF_OS_REG2_BW_CH0 GENMASK(3, 2)
+#define RK3588_PMUGRF_OS_REG2_BW_CH1 GENMASK(19, 18)
+#define RK3588_PMUGRF_OS_REG2_CH_INFO GENMASK(29, 28)
+
+#define RK3588_PMUGRF_OS_REG3 0x20c
+#define RK3588_PMUGRF_OS_REG3_DRAMTYPE_INFO_V3 GENMASK(13, 12)
+#define RK3588_PMUGRF_OS_REG3_SYSREG_VERSION GENMASK(31, 28)
+
+#define RK3588_PMUGRF_OS_REG4 0x210
+#define RK3588_PMUGRF_OS_REG5 0x214
+
+#endif /* __SOC_RK3588_GRF_H */
--
2.39.2
This adds RK3568 support to the DFI driver. Only iniitialization
differs from the currently supported RK3399.
Signed-off-by: Sascha Hauer <[email protected]>
---
Notes:
Changes since v7:
- Add comment to explain << 3
drivers/devfreq/event/rockchip-dfi.c | 27 +++++++++++++++++++++++++++
include/soc/rockchip/rk3568_grf.h | 12 ++++++++++++
2 files changed, 39 insertions(+)
create mode 100644 include/soc/rockchip/rk3568_grf.h
diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c
index 12f9096879235..571d72d1abd1c 100644
--- a/drivers/devfreq/event/rockchip-dfi.c
+++ b/drivers/devfreq/event/rockchip-dfi.c
@@ -23,6 +23,7 @@
#include <soc/rockchip/rockchip_grf.h>
#include <soc/rockchip/rk3399_grf.h>
+#include <soc/rockchip/rk3568_grf.h>
#define DMC_MAX_CHANNELS 2
@@ -211,10 +212,36 @@ static int rk3399_dfi_init(struct rockchip_dfi *dfi)
return 0;
};
+static int rk3568_dfi_init(struct rockchip_dfi *dfi)
+{
+ struct regmap *regmap_pmu = dfi->regmap_pmu;
+ u32 reg2, reg3;
+
+ regmap_read(regmap_pmu, RK3568_PMUGRF_OS_REG2, ®2);
+ regmap_read(regmap_pmu, RK3568_PMUGRF_OS_REG3, ®3);
+
+ /* lower 3 bits of the DDR type */
+ dfi->ddr_type = FIELD_GET(RK3568_PMUGRF_OS_REG2_DRAMTYPE_INFO, reg2);
+
+ /*
+ * For version three and higher the upper two bits of the DDR type are
+ * in RK3568_PMUGRF_OS_REG3
+ */
+ if (FIELD_GET(RK3568_PMUGRF_OS_REG3_SYSREG_VERSION, reg3) >= 0x3)
+ dfi->ddr_type |= FIELD_GET(RK3568_PMUGRF_OS_REG3_DRAMTYPE_INFO_V3, reg3) << 3;
+
+ dfi->channel_mask = BIT(0);
+ dfi->max_channels = 1;
+
+ return 0;
+};
+
static const struct of_device_id rockchip_dfi_id_match[] = {
{ .compatible = "rockchip,rk3399-dfi", .data = rk3399_dfi_init },
+ { .compatible = "rockchip,rk3568-dfi", .data = rk3568_dfi_init },
{ },
};
+
MODULE_DEVICE_TABLE(of, rockchip_dfi_id_match);
static int rockchip_dfi_probe(struct platform_device *pdev)
diff --git a/include/soc/rockchip/rk3568_grf.h b/include/soc/rockchip/rk3568_grf.h
new file mode 100644
index 0000000000000..575584e9d8834
--- /dev/null
+++ b/include/soc/rockchip/rk3568_grf.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+#ifndef __SOC_RK3568_GRF_H
+#define __SOC_RK3568_GRF_H
+
+#define RK3568_PMUGRF_OS_REG2 0x208
+#define RK3568_PMUGRF_OS_REG2_DRAMTYPE_INFO GENMASK(15, 13)
+
+#define RK3568_PMUGRF_OS_REG3 0x20c
+#define RK3568_PMUGRF_OS_REG3_DRAMTYPE_INFO_V3 GENMASK(13, 12)
+#define RK3568_PMUGRF_OS_REG3_SYSREG_VERSION GENMASK(31, 28)
+
+#endif /* __SOC_RK3568_GRF_H */
--
2.39.2
Different Rockchip SoC variants have a different number of channels.
Introduce a channel mask to make the number of channels configurable
from SoC initialization code.
Reviewed-by: Sebastian Reichel <[email protected]>
Signed-off-by: Sascha Hauer <[email protected]>
---
Notes:
Changes since v7:
- Loop only over channels present on a SoC
drivers/devfreq/event/rockchip-dfi.c | 25 +++++++++++++++++++------
1 file changed, 19 insertions(+), 6 deletions(-)
diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c
index 126bb744645b6..28c18bbf6baa5 100644
--- a/drivers/devfreq/event/rockchip-dfi.c
+++ b/drivers/devfreq/event/rockchip-dfi.c
@@ -18,10 +18,11 @@
#include <linux/list.h>
#include <linux/of.h>
#include <linux/of_device.h>
+#include <linux/bits.h>
#include <soc/rockchip/rk3399_grf.h>
-#define RK3399_DMC_NUM_CH 2
+#define DMC_MAX_CHANNELS 2
/* DDRMON_CTRL */
#define DDRMON_CTRL 0x04
@@ -44,7 +45,7 @@ struct dmc_count_channel {
};
struct dmc_count {
- struct dmc_count_channel c[RK3399_DMC_NUM_CH];
+ struct dmc_count_channel c[DMC_MAX_CHANNELS];
};
/*
@@ -61,6 +62,8 @@ struct rockchip_dfi {
struct regmap *regmap_pmu;
struct clk *clk;
u32 ddr_type;
+ unsigned int channel_mask;
+ unsigned int max_channels;
};
static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
@@ -95,7 +98,9 @@ static void rockchip_dfi_read_counters(struct devfreq_event_dev *edev, struct dm
u32 i;
void __iomem *dfi_regs = dfi->regs;
- for (i = 0; i < RK3399_DMC_NUM_CH; i++) {
+ for (i = 0; i < dfi->max_channels; i++) {
+ if (!(dfi->channel_mask & BIT(i)))
+ continue;
count->c[i].access = readl_relaxed(dfi_regs +
DDRMON_CH0_DFI_ACCESS_NUM + i * 20);
count->c[i].total = readl_relaxed(dfi_regs +
@@ -145,9 +150,14 @@ static int rockchip_dfi_get_event(struct devfreq_event_dev *edev,
rockchip_dfi_read_counters(edev, &count);
/* We can only report one channel, so find the busiest one */
- for (i = 0; i < RK3399_DMC_NUM_CH; i++) {
- u32 a = count.c[i].access - last->c[i].access;
- u32 t = count.c[i].total - last->c[i].total;
+ for (i = 0; i < dfi->max_channels; i++) {
+ u32 a, t;
+
+ if (!(dfi->channel_mask & BIT(i)))
+ continue;
+
+ a = count.c[i].access - last->c[i].access;
+ t = count.c[i].total - last->c[i].total;
if (a > access) {
access = a;
@@ -185,6 +195,9 @@ static int rk3399_dfi_init(struct rockchip_dfi *dfi)
dfi->ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) &
RK3399_PMUGRF_DDRTYPE_MASK;
+ dfi->channel_mask = GENMASK(1, 0);
+ dfi->max_channels = 2;
+
return 0;
};
--
2.39.2
The DFI unit can be used to measure DRAM utilization using perf. Add the
node to the device tree.
Signed-off-by: Sascha Hauer <[email protected]>
---
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index abee88911982d..0964761e3ce9e 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -959,6 +959,13 @@ qos_vop_m1: qos@fe1a8100 {
reg = <0x0 0xfe1a8100 0x0 0x20>;
};
+ dfi: dfi@fe230000 {
+ compatible = "rockchip,rk3568-dfi";
+ reg = <0x00 0xfe230000 0x00 0x400>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ rockchip,pmu = <&pmugrf>;
+ };
+
pcie2x1: pcie@fe260000 {
compatible = "rockchip,rk3568-pcie";
reg = <0x3 0xc0000000 0x0 0x00400000>,
--
2.39.2
The variable name for the private data struct is 'info' in some
functions and 'data' in others. Both names do not give a clue what
type the variable has, so consistently use 'dfi'.
Reviewed-by: Heiko Stuebner <[email protected]>
Reviewed-by: Jonathan Cameron <[email protected]>
Reviewed-by: Sebastian Reichel <[email protected]>
Signed-off-by: Sascha Hauer <[email protected]>
---
drivers/devfreq/event/rockchip-dfi.c | 72 ++++++++++++++--------------
1 file changed, 36 insertions(+), 36 deletions(-)
diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c
index 467f9f42d38f7..e19e5acaa362c 100644
--- a/drivers/devfreq/event/rockchip-dfi.c
+++ b/drivers/devfreq/event/rockchip-dfi.c
@@ -59,13 +59,13 @@ struct rockchip_dfi {
static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
{
- struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
- void __iomem *dfi_regs = info->regs;
+ struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);
+ void __iomem *dfi_regs = dfi->regs;
u32 val;
u32 ddr_type;
/* get ddr type */
- regmap_read(info->regmap_pmu, RK3399_PMUGRF_OS_REG2, &val);
+ regmap_read(dfi->regmap_pmu, RK3399_PMUGRF_OS_REG2, &val);
ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) &
RK3399_PMUGRF_DDRTYPE_MASK;
@@ -84,28 +84,28 @@ static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
static void rockchip_dfi_stop_hardware_counter(struct devfreq_event_dev *edev)
{
- struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
- void __iomem *dfi_regs = info->regs;
+ struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);
+ void __iomem *dfi_regs = dfi->regs;
writel_relaxed(SOFTWARE_DIS, dfi_regs + DDRMON_CTRL);
}
static int rockchip_dfi_get_busier_ch(struct devfreq_event_dev *edev)
{
- struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
+ struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);
u32 tmp, max = 0;
u32 i, busier_ch = 0;
- void __iomem *dfi_regs = info->regs;
+ void __iomem *dfi_regs = dfi->regs;
rockchip_dfi_stop_hardware_counter(edev);
/* Find out which channel is busier */
for (i = 0; i < RK3399_DMC_NUM_CH; i++) {
- info->ch_usage[i].access = readl_relaxed(dfi_regs +
+ dfi->ch_usage[i].access = readl_relaxed(dfi_regs +
DDRMON_CH0_DFI_ACCESS_NUM + i * 20) * 4;
- info->ch_usage[i].total = readl_relaxed(dfi_regs +
+ dfi->ch_usage[i].total = readl_relaxed(dfi_regs +
DDRMON_CH0_COUNT_NUM + i * 20);
- tmp = info->ch_usage[i].access;
+ tmp = dfi->ch_usage[i].access;
if (tmp > max) {
busier_ch = i;
max = tmp;
@@ -118,20 +118,20 @@ static int rockchip_dfi_get_busier_ch(struct devfreq_event_dev *edev)
static int rockchip_dfi_disable(struct devfreq_event_dev *edev)
{
- struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
+ struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);
rockchip_dfi_stop_hardware_counter(edev);
- clk_disable_unprepare(info->clk);
+ clk_disable_unprepare(dfi->clk);
return 0;
}
static int rockchip_dfi_enable(struct devfreq_event_dev *edev)
{
- struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
+ struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);
int ret;
- ret = clk_prepare_enable(info->clk);
+ ret = clk_prepare_enable(dfi->clk);
if (ret) {
dev_err(&edev->dev, "failed to enable dfi clk: %d\n", ret);
return ret;
@@ -149,13 +149,13 @@ static int rockchip_dfi_set_event(struct devfreq_event_dev *edev)
static int rockchip_dfi_get_event(struct devfreq_event_dev *edev,
struct devfreq_event_data *edata)
{
- struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
+ struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);
int busier_ch;
busier_ch = rockchip_dfi_get_busier_ch(edev);
- edata->load_count = info->ch_usage[busier_ch].access;
- edata->total_count = info->ch_usage[busier_ch].total;
+ edata->load_count = dfi->ch_usage[busier_ch].access;
+ edata->total_count = dfi->ch_usage[busier_ch].total;
return 0;
}
@@ -176,47 +176,47 @@ MODULE_DEVICE_TABLE(of, rockchip_dfi_id_match);
static int rockchip_dfi_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
- struct rockchip_dfi *data;
+ struct rockchip_dfi *dfi;
struct devfreq_event_desc *desc;
struct device_node *np = pdev->dev.of_node, *node;
- data = devm_kzalloc(dev, sizeof(struct rockchip_dfi), GFP_KERNEL);
- if (!data)
+ dfi = devm_kzalloc(dev, sizeof(*dfi), GFP_KERNEL);
+ if (!dfi)
return -ENOMEM;
- data->regs = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(data->regs))
- return PTR_ERR(data->regs);
+ dfi->regs = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(dfi->regs))
+ return PTR_ERR(dfi->regs);
- data->clk = devm_clk_get(dev, "pclk_ddr_mon");
- if (IS_ERR(data->clk))
- return dev_err_probe(dev, PTR_ERR(data->clk),
+ dfi->clk = devm_clk_get(dev, "pclk_ddr_mon");
+ if (IS_ERR(dfi->clk))
+ return dev_err_probe(dev, PTR_ERR(dfi->clk),
"Cannot get the clk pclk_ddr_mon\n");
node = of_parse_phandle(np, "rockchip,pmu", 0);
if (!node)
return dev_err_probe(&pdev->dev, -ENODEV, "Can't find pmu_grf registers\n");
- data->regmap_pmu = syscon_node_to_regmap(node);
+ dfi->regmap_pmu = syscon_node_to_regmap(node);
of_node_put(node);
- if (IS_ERR(data->regmap_pmu))
- return PTR_ERR(data->regmap_pmu);
+ if (IS_ERR(dfi->regmap_pmu))
+ return PTR_ERR(dfi->regmap_pmu);
- data->dev = dev;
+ dfi->dev = dev;
- desc = &data->desc;
+ desc = &dfi->desc;
desc->ops = &rockchip_dfi_ops;
- desc->driver_data = data;
+ desc->driver_data = dfi;
desc->name = np->name;
- data->edev = devm_devfreq_event_add_edev(&pdev->dev, desc);
- if (IS_ERR(data->edev)) {
+ dfi->edev = devm_devfreq_event_add_edev(&pdev->dev, desc);
+ if (IS_ERR(dfi->edev)) {
dev_err(&pdev->dev,
"failed to add devfreq-event device\n");
- return PTR_ERR(data->edev);
+ return PTR_ERR(dfi->edev);
}
- platform_set_drvdata(pdev, data);
+ platform_set_drvdata(pdev, dfi);
return 0;
}
--
2.39.2
As a matter of fact the regmap_pmu already is mandatory because
it is used unconditionally in the driver. Bail out gracefully in
probe() rather than crashing later.
Fixes: b9d1262bca0af ("PM / devfreq: event: support rockchip dfi controller")
Reviewed-by: Sebastian Reichel <[email protected]>
Signed-off-by: Sascha Hauer <[email protected]>
---
Notes:
Changes since v4:
- move to beginning of the series to make it easier to backport to stable
- Add a Fixes: tag
- add missing of_node_put()
drivers/devfreq/event/rockchip-dfi.c | 15 ++++++++-------
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c
index 39ac069cabc75..74893c06aa087 100644
--- a/drivers/devfreq/event/rockchip-dfi.c
+++ b/drivers/devfreq/event/rockchip-dfi.c
@@ -193,14 +193,15 @@ static int rockchip_dfi_probe(struct platform_device *pdev)
return dev_err_probe(dev, PTR_ERR(data->clk),
"Cannot get the clk pclk_ddr_mon\n");
- /* try to find the optional reference to the pmu syscon */
node = of_parse_phandle(np, "rockchip,pmu", 0);
- if (node) {
- data->regmap_pmu = syscon_node_to_regmap(node);
- of_node_put(node);
- if (IS_ERR(data->regmap_pmu))
- return PTR_ERR(data->regmap_pmu);
- }
+ if (!node)
+ return dev_err_probe(&pdev->dev, -ENODEV, "Can't find pmu_grf registers\n");
+
+ data->regmap_pmu = syscon_node_to_regmap(node);
+ of_node_put(node);
+ if (IS_ERR(data->regmap_pmu))
+ return PTR_ERR(data->regmap_pmu);
+
data->dev = dev;
desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
--
2.39.2
The internal functions do not need the struct devfreq_event_dev *,
so pass them the struct rockchip_dfi *. This is a preparation for
adding perf support later which doesn't have a struct devfreq_event_dev *.
Reviewed-by: Jonathan Cameron <[email protected]>
Reviewed-by: Sebastian Reichel <[email protected]>
Acked-by: Chanwoo Choi <[email protected]>
Signed-off-by: Sascha Hauer <[email protected]>
---
drivers/devfreq/event/rockchip-dfi.c | 15 ++++++---------
1 file changed, 6 insertions(+), 9 deletions(-)
diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c
index bdf421b248df9..d56a33d03db4c 100644
--- a/drivers/devfreq/event/rockchip-dfi.c
+++ b/drivers/devfreq/event/rockchip-dfi.c
@@ -73,9 +73,8 @@ struct rockchip_dfi {
unsigned int max_channels;
};
-static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
+static void rockchip_dfi_start_hardware_counter(struct rockchip_dfi *dfi)
{
- struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);
void __iomem *dfi_regs = dfi->regs;
/* clear DDRMON_CTRL setting */
@@ -103,18 +102,16 @@ static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
dfi_regs + DDRMON_CTRL);
}
-static void rockchip_dfi_stop_hardware_counter(struct devfreq_event_dev *edev)
+static void rockchip_dfi_stop_hardware_counter(struct rockchip_dfi *dfi)
{
- struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);
void __iomem *dfi_regs = dfi->regs;
writel_relaxed(HIWORD_UPDATE(0, DDRMON_CTRL_SOFTWARE_EN),
dfi_regs + DDRMON_CTRL);
}
-static void rockchip_dfi_read_counters(struct devfreq_event_dev *edev, struct dmc_count *count)
+static void rockchip_dfi_read_counters(struct rockchip_dfi *dfi, struct dmc_count *count)
{
- struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);
u32 i;
void __iomem *dfi_regs = dfi->regs;
@@ -132,7 +129,7 @@ static int rockchip_dfi_disable(struct devfreq_event_dev *edev)
{
struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);
- rockchip_dfi_stop_hardware_counter(edev);
+ rockchip_dfi_stop_hardware_counter(dfi);
clk_disable_unprepare(dfi->clk);
return 0;
@@ -149,7 +146,7 @@ static int rockchip_dfi_enable(struct devfreq_event_dev *edev)
return ret;
}
- rockchip_dfi_start_hardware_counter(edev);
+ rockchip_dfi_start_hardware_counter(dfi);
return 0;
}
@@ -167,7 +164,7 @@ static int rockchip_dfi_get_event(struct devfreq_event_dev *edev,
u32 access = 0, total = 0;
int i;
- rockchip_dfi_read_counters(edev, &count);
+ rockchip_dfi_read_counters(dfi, &count);
/* We can only report one channel, so find the busiest one */
for (i = 0; i < dfi->max_channels; i++) {
--
2.39.2
The DDRTYPE defines are named to be RK3399 specific, but they can be
used for other Rockchip SoCs as well, so replace the RK3399_PMUGRF_
prefix with ROCKCHIP_. They are defined in a SoC specific header
file, so when generalizing the prefix also move the new defines to
a SoC agnostic header file. While at it use GENMASK to define the
DDRTYPE bitfield and give it a name including the full register name.
Reviewed-by: Sebastian Reichel <[email protected]>
Acked-by: Chanwoo Choi <[email protected]>
Signed-off-by: Sascha Hauer <[email protected]>
---
drivers/devfreq/event/rockchip-dfi.c | 9 +++++----
drivers/devfreq/rk3399_dmc.c | 10 +++++-----
include/soc/rockchip/rk3399_grf.h | 7 +------
include/soc/rockchip/rockchip_grf.h | 17 +++++++++++++++++
4 files changed, 28 insertions(+), 15 deletions(-)
create mode 100644 include/soc/rockchip/rockchip_grf.h
diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c
index 28c18bbf6baa5..82d18c60538a5 100644
--- a/drivers/devfreq/event/rockchip-dfi.c
+++ b/drivers/devfreq/event/rockchip-dfi.c
@@ -18,8 +18,10 @@
#include <linux/list.h>
#include <linux/of.h>
#include <linux/of_device.h>
+#include <linux/bitfield.h>
#include <linux/bits.h>
+#include <soc/rockchip/rockchip_grf.h>
#include <soc/rockchip/rk3399_grf.h>
#define DMC_MAX_CHANNELS 2
@@ -75,9 +77,9 @@ static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
writel_relaxed(CLR_DDRMON_CTRL, dfi_regs + DDRMON_CTRL);
/* set ddr type to dfi */
- if (dfi->ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR3)
+ if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR3)
writel_relaxed(LPDDR3_EN, dfi_regs + DDRMON_CTRL);
- else if (dfi->ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR4)
+ else if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR4)
writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL);
/* enable count, use software mode */
@@ -192,8 +194,7 @@ static int rk3399_dfi_init(struct rockchip_dfi *dfi)
/* get ddr type */
regmap_read(regmap_pmu, RK3399_PMUGRF_OS_REG2, &val);
- dfi->ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) &
- RK3399_PMUGRF_DDRTYPE_MASK;
+ dfi->ddr_type = FIELD_GET(RK3399_PMUGRF_OS_REG2_DDRTYPE, val);
dfi->channel_mask = GENMASK(1, 0);
dfi->max_channels = 2;
diff --git a/drivers/devfreq/rk3399_dmc.c b/drivers/devfreq/rk3399_dmc.c
index daff407026157..fd2c5ffedf41e 100644
--- a/drivers/devfreq/rk3399_dmc.c
+++ b/drivers/devfreq/rk3399_dmc.c
@@ -22,6 +22,7 @@
#include <linux/suspend.h>
#include <soc/rockchip/pm_domains.h>
+#include <soc/rockchip/rockchip_grf.h>
#include <soc/rockchip/rk3399_grf.h>
#include <soc/rockchip/rockchip_sip.h>
@@ -381,17 +382,16 @@ static int rk3399_dmcfreq_probe(struct platform_device *pdev)
}
regmap_read(data->regmap_pmu, RK3399_PMUGRF_OS_REG2, &val);
- ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) &
- RK3399_PMUGRF_DDRTYPE_MASK;
+ ddr_type = FIELD_GET(RK3399_PMUGRF_OS_REG2_DDRTYPE, val);
switch (ddr_type) {
- case RK3399_PMUGRF_DDRTYPE_DDR3:
+ case ROCKCHIP_DDRTYPE_DDR3:
data->odt_dis_freq = data->ddr3_odt_dis_freq;
break;
- case RK3399_PMUGRF_DDRTYPE_LPDDR3:
+ case ROCKCHIP_DDRTYPE_LPDDR3:
data->odt_dis_freq = data->lpddr3_odt_dis_freq;
break;
- case RK3399_PMUGRF_DDRTYPE_LPDDR4:
+ case ROCKCHIP_DDRTYPE_LPDDR4:
data->odt_dis_freq = data->lpddr4_odt_dis_freq;
break;
default:
diff --git a/include/soc/rockchip/rk3399_grf.h b/include/soc/rockchip/rk3399_grf.h
index 3eebabcb28123..775f8444bea8d 100644
--- a/include/soc/rockchip/rk3399_grf.h
+++ b/include/soc/rockchip/rk3399_grf.h
@@ -11,11 +11,6 @@
/* PMU GRF Registers */
#define RK3399_PMUGRF_OS_REG2 0x308
-#define RK3399_PMUGRF_DDRTYPE_SHIFT 13
-#define RK3399_PMUGRF_DDRTYPE_MASK 7
-#define RK3399_PMUGRF_DDRTYPE_DDR3 3
-#define RK3399_PMUGRF_DDRTYPE_LPDDR2 5
-#define RK3399_PMUGRF_DDRTYPE_LPDDR3 6
-#define RK3399_PMUGRF_DDRTYPE_LPDDR4 7
+#define RK3399_PMUGRF_OS_REG2_DDRTYPE GENMASK(15, 13)
#endif
diff --git a/include/soc/rockchip/rockchip_grf.h b/include/soc/rockchip/rockchip_grf.h
new file mode 100644
index 0000000000000..dde1a9796ccb5
--- /dev/null
+++ b/include/soc/rockchip/rockchip_grf.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Rockchip General Register Files definitions
+ */
+
+#ifndef __SOC_ROCKCHIP_GRF_H
+#define __SOC_ROCKCHIP_GRF_H
+
+/* Rockchip DDRTYPE defines */
+enum {
+ ROCKCHIP_DDRTYPE_DDR3 = 3,
+ ROCKCHIP_DDRTYPE_LPDDR2 = 5,
+ ROCKCHIP_DDRTYPE_LPDDR3 = 6,
+ ROCKCHIP_DDRTYPE_LPDDR4 = 7,
+};
+
+#endif /* __SOC_ROCKCHIP_GRF_H */
--
2.39.2
Convert the Rockchip DFI binding to yaml.
Reviewed-by: Rob Herring <[email protected]>
Reviewed-by: Sebastian Reichel <[email protected]>
Acked-by: Chanwoo Choi <[email protected]>
Signed-off-by: Sascha Hauer <[email protected]>
---
Notes:
Changes since v4:
- Revert to state of v3 (changes were lost in v4)
.../bindings/devfreq/event/rockchip,dfi.yaml | 61 +++++++++++++++++++
.../bindings/devfreq/event/rockchip-dfi.txt | 18 ------
.../rockchip,rk3399-dmc.yaml | 2 +-
3 files changed, 62 insertions(+), 19 deletions(-)
create mode 100644 Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml
delete mode 100644 Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt
diff --git a/Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml b/Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml
new file mode 100644
index 0000000000000..7a82f6ae0701e
--- /dev/null
+++ b/Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/devfreq/event/rockchip,dfi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip DFI
+
+maintainers:
+ - Sascha Hauer <[email protected]>
+
+properties:
+ compatible:
+ enum:
+ - rockchip,rk3399-dfi
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: pclk_ddr_mon
+
+ interrupts:
+ maxItems: 1
+
+ reg:
+ maxItems: 1
+
+ rockchip,pmu:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to the syscon managing the "PMU general register files".
+
+required:
+ - compatible
+ - clocks
+ - clock-names
+ - interrupts
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/rk3308-cru.h>
+
+ bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ dfi: dfi@ff630000 {
+ compatible = "rockchip,rk3399-dfi";
+ reg = <0x00 0xff630000 0x00 0x4000>;
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>;
+ rockchip,pmu = <&pmugrf>;
+ clocks = <&cru PCLK_DDR_MON>;
+ clock-names = "pclk_ddr_mon";
+ };
+ };
diff --git a/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt b/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt
deleted file mode 100644
index 148191b0fc158..0000000000000
--- a/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-
-* Rockchip rk3399 DFI device
-
-Required properties:
-- compatible: Must be "rockchip,rk3399-dfi".
-- reg: physical base address of each DFI and length of memory mapped region
-- rockchip,pmu: phandle to the syscon managing the "pmu general register files"
-- clocks: phandles for clock specified in "clock-names" property
-- clock-names : the name of clock used by the DFI, must be "pclk_ddr_mon";
-
-Example:
- dfi: dfi@ff630000 {
- compatible = "rockchip,rk3399-dfi";
- reg = <0x00 0xff630000 0x00 0x4000>;
- rockchip,pmu = <&pmugrf>;
- clocks = <&cru PCLK_DDR_MON>;
- clock-names = "pclk_ddr_mon";
- };
diff --git a/Documentation/devicetree/bindings/memory-controllers/rockchip,rk3399-dmc.yaml b/Documentation/devicetree/bindings/memory-controllers/rockchip,rk3399-dmc.yaml
index 4e4af3cfc0fe4..1f58ee99be280 100644
--- a/Documentation/devicetree/bindings/memory-controllers/rockchip,rk3399-dmc.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/rockchip,rk3399-dmc.yaml
@@ -18,7 +18,7 @@ properties:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Node to get DDR loading. Refer to
- Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt.
+ Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml.
clocks:
maxItems: 1
--
2.39.2
Use the HIWORD_UPDATE() define known from other rockchip drivers to
make the defines look less odd to the readers who've seen other
rockchip drivers.
The HIWORD registers have their functional bits in the lower 16 bits
whereas the upper 16 bits contain a mask. Only the functional bits that
have the corresponding mask bit set are modified during a write. Although
the register writes look different, the end result should be the same,
at least there's no functional change intended with this patch.
Signed-off-by: Sascha Hauer <[email protected]>
Reviewed-by: Sebastian Reichel <[email protected]>
Acked-by: Chanwoo Choi <[email protected]>
---
drivers/devfreq/event/rockchip-dfi.c | 33 ++++++++++++++++++----------
1 file changed, 21 insertions(+), 12 deletions(-)
diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c
index 82d18c60538a5..12f9096879235 100644
--- a/drivers/devfreq/event/rockchip-dfi.c
+++ b/drivers/devfreq/event/rockchip-dfi.c
@@ -26,15 +26,19 @@
#define DMC_MAX_CHANNELS 2
+#define HIWORD_UPDATE(val, mask) ((val) | (mask) << 16)
+
/* DDRMON_CTRL */
#define DDRMON_CTRL 0x04
-#define CLR_DDRMON_CTRL (0x1f0000 << 0)
-#define LPDDR4_EN (0x10001 << 4)
-#define HARDWARE_EN (0x10001 << 3)
-#define LPDDR3_EN (0x10001 << 2)
-#define SOFTWARE_EN (0x10001 << 1)
-#define SOFTWARE_DIS (0x10000 << 1)
-#define TIME_CNT_EN (0x10001 << 0)
+#define DDRMON_CTRL_DDR4 BIT(5)
+#define DDRMON_CTRL_LPDDR4 BIT(4)
+#define DDRMON_CTRL_HARDWARE_EN BIT(3)
+#define DDRMON_CTRL_LPDDR23 BIT(2)
+#define DDRMON_CTRL_SOFTWARE_EN BIT(1)
+#define DDRMON_CTRL_TIMER_CNT_EN BIT(0)
+#define DDRMON_CTRL_DDR_TYPE_MASK (DDRMON_CTRL_DDR4 | \
+ DDRMON_CTRL_LPDDR4 | \
+ DDRMON_CTRL_LPDDR23)
#define DDRMON_CH0_COUNT_NUM 0x28
#define DDRMON_CH0_DFI_ACCESS_NUM 0x2c
@@ -74,16 +78,20 @@ static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
void __iomem *dfi_regs = dfi->regs;
/* clear DDRMON_CTRL setting */
- writel_relaxed(CLR_DDRMON_CTRL, dfi_regs + DDRMON_CTRL);
+ writel_relaxed(HIWORD_UPDATE(0, DDRMON_CTRL_TIMER_CNT_EN | DDRMON_CTRL_SOFTWARE_EN |
+ DDRMON_CTRL_HARDWARE_EN), dfi_regs + DDRMON_CTRL);
/* set ddr type to dfi */
if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR3)
- writel_relaxed(LPDDR3_EN, dfi_regs + DDRMON_CTRL);
+ writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR23, DDRMON_CTRL_DDR_TYPE_MASK),
+ dfi_regs + DDRMON_CTRL);
else if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR4)
- writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL);
+ writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR4, DDRMON_CTRL_DDR_TYPE_MASK),
+ dfi_regs + DDRMON_CTRL);
/* enable count, use software mode */
- writel_relaxed(SOFTWARE_EN, dfi_regs + DDRMON_CTRL);
+ writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_SOFTWARE_EN, DDRMON_CTRL_SOFTWARE_EN),
+ dfi_regs + DDRMON_CTRL);
}
static void rockchip_dfi_stop_hardware_counter(struct devfreq_event_dev *edev)
@@ -91,7 +99,8 @@ static void rockchip_dfi_stop_hardware_counter(struct devfreq_event_dev *edev)
struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);
void __iomem *dfi_regs = dfi->regs;
- writel_relaxed(SOFTWARE_DIS, dfi_regs + DDRMON_CTRL);
+ writel_relaxed(HIWORD_UPDATE(0, DDRMON_CTRL_SOFTWARE_EN),
+ dfi_regs + DDRMON_CTRL);
}
static void rockchip_dfi_read_counters(struct devfreq_event_dev *edev, struct dmc_count *count)
--
2.39.2
According to the downstream driver the DDRMON_CTRL_LPDDR23 bit must be
set for both LPDDR2 and LPDDR3. Add the missing LPDDR2 case and while
at it turn the if/else if/else into switch/case which makes it easier
to read.
Reviewed-by: Jonathan Cameron <[email protected]>
Reviewed-by: Sebastian Reichel <[email protected]>
Acked-by: Chanwoo Choi <[email protected]>
Signed-off-by: Sascha Hauer <[email protected]>
---
drivers/devfreq/event/rockchip-dfi.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c
index 571d72d1abd1c..8ce0191552ef1 100644
--- a/drivers/devfreq/event/rockchip-dfi.c
+++ b/drivers/devfreq/event/rockchip-dfi.c
@@ -83,12 +83,19 @@ static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
DDRMON_CTRL_HARDWARE_EN), dfi_regs + DDRMON_CTRL);
/* set ddr type to dfi */
- if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR3)
+ switch (dfi->ddr_type) {
+ case ROCKCHIP_DDRTYPE_LPDDR2:
+ case ROCKCHIP_DDRTYPE_LPDDR3:
writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR23, DDRMON_CTRL_DDR_TYPE_MASK),
dfi_regs + DDRMON_CTRL);
- else if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR4)
+ break;
+ case ROCKCHIP_DDRTYPE_LPDDR4:
writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR4, DDRMON_CTRL_DDR_TYPE_MASK),
dfi_regs + DDRMON_CTRL);
+ break;
+ default:
+ break;
+ }
/* enable count, use software mode */
writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_SOFTWARE_EN, DDRMON_CTRL_SOFTWARE_EN),
--
2.39.2
The DFI is a unit which is suitable for measuring DDR utilization, but
so far it could only be used as an event driver for the DDR frequency
scaling driver. This adds perf support to the DFI driver.
Usage with the 'perf' tool can look like:
perf stat -a -e rockchip_ddr/cycles/,\
rockchip_ddr/read-bytes/,\
rockchip_ddr/write-bytes/,\
rockchip_ddr/bytes/ sleep 1
Performance counter stats for 'system wide':
1582524826 rockchip_ddr/cycles/
1802.25 MB rockchip_ddr/read-bytes/
1793.72 MB rockchip_ddr/write-bytes/
3595.90 MB rockchip_ddr/bytes/
1.014369709 seconds time elapsed
perf support has been tested on a RK3568 and a RK3399, the latter with
dual channel DDR.
Reviewed-by: Sebastian Reichel <[email protected]>
Acked-by: Chanwoo Choi <[email protected]>
Signed-off-by: Sascha Hauer <[email protected]>
---
Notes:
Changes since v7:
- rename variable 'c' to 'count'
Changes since v5:
- Add missing initialization of &dfi->last_perf_count
Changes since v4:
- use __stringify to ensure event type definitions and event numbers in sysfs are consistent
- only use 64bit values in structs holding counters
- support monitoring individual DDR channels
- fix return value in rockchip_ddr_perf_event_init(): -EOPNOTSUPP -> -EINVAL
- check for invalid event->attr.config values
- start hrtimer to trigger in one second, not immediately
- use devm_add_action_or_reset()
- add suppress_bind_attrs
- enable DDRMON during probe when perf is enabled
- use a seqlock to protect perf reading the counters from the hrtimer callback modifying them
drivers/devfreq/event/rockchip-dfi.c | 440 ++++++++++++++++++++++++++-
include/soc/rockchip/rk3399_grf.h | 2 +
include/soc/rockchip/rk3568_grf.h | 1 +
3 files changed, 438 insertions(+), 5 deletions(-)
diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c
index 3d5c6d737ccd9..63977f9fc2693 100644
--- a/drivers/devfreq/event/rockchip-dfi.c
+++ b/drivers/devfreq/event/rockchip-dfi.c
@@ -16,10 +16,12 @@
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/list.h>
+#include <linux/seqlock.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/bitfield.h>
#include <linux/bits.h>
+#include <linux/perf_event.h>
#include <soc/rockchip/rockchip_grf.h>
#include <soc/rockchip/rk3399_grf.h>
@@ -41,19 +43,39 @@
DDRMON_CTRL_LPDDR4 | \
DDRMON_CTRL_LPDDR23)
+#define DDRMON_CH0_WR_NUM 0x20
+#define DDRMON_CH0_RD_NUM 0x24
#define DDRMON_CH0_COUNT_NUM 0x28
#define DDRMON_CH0_DFI_ACCESS_NUM 0x2c
#define DDRMON_CH1_COUNT_NUM 0x3c
#define DDRMON_CH1_DFI_ACCESS_NUM 0x40
+#define PERF_EVENT_CYCLES 0x0
+#define PERF_EVENT_READ_BYTES 0x1
+#define PERF_EVENT_WRITE_BYTES 0x2
+#define PERF_EVENT_READ_BYTES0 0x3
+#define PERF_EVENT_WRITE_BYTES0 0x4
+#define PERF_EVENT_READ_BYTES1 0x5
+#define PERF_EVENT_WRITE_BYTES1 0x6
+#define PERF_EVENT_READ_BYTES2 0x7
+#define PERF_EVENT_WRITE_BYTES2 0x8
+#define PERF_EVENT_READ_BYTES3 0x9
+#define PERF_EVENT_WRITE_BYTES3 0xa
+#define PERF_EVENT_BYTES 0xb
+#define PERF_ACCESS_TYPE_MAX 0xc
+
/**
* struct dmc_count_channel - structure to hold counter values from the DDR controller
* @access: Number of read and write accesses
* @clock_cycles: DDR clock cycles
+ * @read_access: number of read accesses
+ * @write_acccess: number of write accesses
*/
struct dmc_count_channel {
- u32 access;
- u32 clock_cycles;
+ u64 access;
+ u64 clock_cycles;
+ u64 read_access;
+ u64 write_access;
};
struct dmc_count {
@@ -69,6 +91,11 @@ struct rockchip_dfi {
struct devfreq_event_dev *edev;
struct devfreq_event_desc desc;
struct dmc_count last_event_count;
+
+ struct dmc_count last_perf_count;
+ struct dmc_count total_count;
+ seqlock_t count_seqlock; /* protects last_perf_count and total_count */
+
struct device *dev;
void __iomem *regs;
struct regmap *regmap_pmu;
@@ -78,6 +105,14 @@ struct rockchip_dfi {
u32 ddr_type;
unsigned int channel_mask;
unsigned int max_channels;
+ enum cpuhp_state cpuhp_state;
+ struct hlist_node node;
+ struct pmu pmu;
+ struct hrtimer timer;
+ unsigned int cpu;
+ int active_events;
+ int burst_len;
+ int buswidth[DMC_MAX_CHANNELS];
};
static int rockchip_dfi_enable(struct rockchip_dfi *dfi)
@@ -146,7 +181,7 @@ static void rockchip_dfi_disable(struct rockchip_dfi *dfi)
mutex_unlock(&dfi->mutex);
}
-static void rockchip_dfi_read_counters(struct rockchip_dfi *dfi, struct dmc_count *count)
+static void rockchip_dfi_read_counters(struct rockchip_dfi *dfi, struct dmc_count *res)
{
u32 i;
void __iomem *dfi_regs = dfi->regs;
@@ -154,13 +189,36 @@ static void rockchip_dfi_read_counters(struct rockchip_dfi *dfi, struct dmc_coun
for (i = 0; i < dfi->max_channels; i++) {
if (!(dfi->channel_mask & BIT(i)))
continue;
- count->c[i].access = readl_relaxed(dfi_regs +
+ res->c[i].read_access = readl_relaxed(dfi_regs +
+ DDRMON_CH0_RD_NUM + i * 20);
+ res->c[i].write_access = readl_relaxed(dfi_regs +
+ DDRMON_CH0_WR_NUM + i * 20);
+ res->c[i].access = readl_relaxed(dfi_regs +
DDRMON_CH0_DFI_ACCESS_NUM + i * 20);
- count->c[i].clock_cycles = readl_relaxed(dfi_regs +
+ res->c[i].clock_cycles = readl_relaxed(dfi_regs +
DDRMON_CH0_COUNT_NUM + i * 20);
}
}
+static void rockchip_ddr_perf_counters_add(struct rockchip_dfi *dfi,
+ const struct dmc_count *now,
+ struct dmc_count *res)
+{
+ const struct dmc_count *last = &dfi->last_perf_count;
+ int i;
+
+ for (i = 0; i < dfi->max_channels; i++) {
+ res->c[i].read_access = dfi->total_count.c[i].read_access +
+ (u32)(now->c[i].read_access - last->c[i].read_access);
+ res->c[i].write_access = dfi->total_count.c[i].write_access +
+ (u32)(now->c[i].write_access - last->c[i].write_access);
+ res->c[i].access = dfi->total_count.c[i].access +
+ (u32)(now->c[i].access - last->c[i].access);
+ res->c[i].clock_cycles = dfi->total_count.c[i].clock_cycles +
+ (u32)(now->c[i].clock_cycles - last->c[i].clock_cycles);
+ }
+}
+
static int rockchip_dfi_event_disable(struct devfreq_event_dev *edev)
{
struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);
@@ -224,6 +282,368 @@ static const struct devfreq_event_ops rockchip_dfi_ops = {
.set_event = rockchip_dfi_set_event,
};
+#ifdef CONFIG_PERF_EVENTS
+
+static ssize_t ddr_perf_cpumask_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct pmu *pmu = dev_get_drvdata(dev);
+ struct rockchip_dfi *dfi = container_of(pmu, struct rockchip_dfi, pmu);
+
+ return cpumap_print_to_pagebuf(true, buf, cpumask_of(dfi->cpu));
+}
+
+static struct device_attribute ddr_perf_cpumask_attr =
+ __ATTR(cpumask, 0444, ddr_perf_cpumask_show, NULL);
+
+static struct attribute *ddr_perf_cpumask_attrs[] = {
+ &ddr_perf_cpumask_attr.attr,
+ NULL,
+};
+
+static const struct attribute_group ddr_perf_cpumask_attr_group = {
+ .attrs = ddr_perf_cpumask_attrs,
+};
+
+PMU_EVENT_ATTR_STRING(cycles, ddr_pmu_cycles, "event="__stringify(PERF_EVENT_CYCLES))
+
+#define DFI_PMU_EVENT_ATTR(_name, _var, _str) \
+ PMU_EVENT_ATTR_STRING(_name, _var, _str); \
+ PMU_EVENT_ATTR_STRING(_name.unit, _var##_unit, "MB"); \
+ PMU_EVENT_ATTR_STRING(_name.scale, _var##_scale, "9.536743164e-07")
+
+DFI_PMU_EVENT_ATTR(read-bytes0, ddr_pmu_read_bytes0, "event="__stringify(PERF_EVENT_READ_BYTES0));
+DFI_PMU_EVENT_ATTR(write-bytes0, ddr_pmu_write_bytes0, "event="__stringify(PERF_EVENT_WRITE_BYTES0));
+
+DFI_PMU_EVENT_ATTR(read-bytes1, ddr_pmu_read_bytes1, "event="__stringify(PERF_EVENT_READ_BYTES1));
+DFI_PMU_EVENT_ATTR(write-bytes1, ddr_pmu_write_bytes1, "event="__stringify(PERF_EVENT_WRITE_BYTES1));
+
+DFI_PMU_EVENT_ATTR(read-bytes2, ddr_pmu_read_bytes2, "event="__stringify(PERF_EVENT_READ_BYTES2));
+DFI_PMU_EVENT_ATTR(write-bytes2, ddr_pmu_write_bytes2, "event="__stringify(PERF_EVENT_WRITE_BYTES2));
+
+DFI_PMU_EVENT_ATTR(read-bytes3, ddr_pmu_read_bytes3, "event="__stringify(PERF_EVENT_READ_BYTES3));
+DFI_PMU_EVENT_ATTR(write-bytes3, ddr_pmu_write_bytes3, "event="__stringify(PERF_EVENT_WRITE_BYTES3));
+
+DFI_PMU_EVENT_ATTR(read-bytes, ddr_pmu_read_bytes, "event="__stringify(PERF_EVENT_READ_BYTES));
+DFI_PMU_EVENT_ATTR(write-bytes, ddr_pmu_write_bytes, "event="__stringify(PERF_EVENT_WRITE_BYTES));
+
+DFI_PMU_EVENT_ATTR(bytes, ddr_pmu_bytes, "event="__stringify(PERF_EVENT_BYTES));
+
+#define DFI_ATTR_MB(_name) \
+ &_name.attr.attr, \
+ &_name##_unit.attr.attr, \
+ &_name##_scale.attr.attr
+
+static struct attribute *ddr_perf_events_attrs[] = {
+ &ddr_pmu_cycles.attr.attr,
+ DFI_ATTR_MB(ddr_pmu_read_bytes),
+ DFI_ATTR_MB(ddr_pmu_write_bytes),
+ DFI_ATTR_MB(ddr_pmu_read_bytes0),
+ DFI_ATTR_MB(ddr_pmu_write_bytes0),
+ DFI_ATTR_MB(ddr_pmu_read_bytes1),
+ DFI_ATTR_MB(ddr_pmu_write_bytes1),
+ DFI_ATTR_MB(ddr_pmu_read_bytes2),
+ DFI_ATTR_MB(ddr_pmu_write_bytes2),
+ DFI_ATTR_MB(ddr_pmu_read_bytes3),
+ DFI_ATTR_MB(ddr_pmu_write_bytes3),
+ DFI_ATTR_MB(ddr_pmu_bytes),
+ NULL,
+};
+
+static const struct attribute_group ddr_perf_events_attr_group = {
+ .name = "events",
+ .attrs = ddr_perf_events_attrs,
+};
+
+PMU_FORMAT_ATTR(event, "config:0-7");
+
+static struct attribute *ddr_perf_format_attrs[] = {
+ &format_attr_event.attr,
+ NULL,
+};
+
+static const struct attribute_group ddr_perf_format_attr_group = {
+ .name = "format",
+ .attrs = ddr_perf_format_attrs,
+};
+
+static const struct attribute_group *attr_groups[] = {
+ &ddr_perf_events_attr_group,
+ &ddr_perf_cpumask_attr_group,
+ &ddr_perf_format_attr_group,
+ NULL,
+};
+
+static int rockchip_ddr_perf_event_init(struct perf_event *event)
+{
+ struct rockchip_dfi *dfi = container_of(event->pmu, struct rockchip_dfi, pmu);
+
+ if (event->attr.type != event->pmu->type)
+ return -ENOENT;
+
+ if (event->attach_state & PERF_ATTACH_TASK)
+ return -EINVAL;
+
+ if (event->cpu < 0) {
+ dev_warn(dfi->dev, "Can't provide per-task data!\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static u64 rockchip_ddr_perf_event_get_count(struct perf_event *event)
+{
+ struct rockchip_dfi *dfi = container_of(event->pmu, struct rockchip_dfi, pmu);
+ int blen = dfi->burst_len;
+ struct dmc_count total, now;
+ unsigned int seq;
+ u64 count = 0;
+ int i;
+
+ rockchip_dfi_read_counters(dfi, &now);
+
+ do {
+ seq = read_seqbegin(&dfi->count_seqlock);
+ rockchip_ddr_perf_counters_add(dfi, &now, &total);
+ } while (read_seqretry(&dfi->count_seqlock, seq));
+
+ switch (event->attr.config) {
+ case PERF_EVENT_CYCLES:
+ count = total.c[0].clock_cycles;
+ break;
+ case PERF_EVENT_READ_BYTES:
+ for (i = 0; i < dfi->max_channels; i++)
+ count += total.c[i].read_access * blen * dfi->buswidth[i];
+ break;
+ case PERF_EVENT_WRITE_BYTES:
+ for (i = 0; i < dfi->max_channels; i++)
+ count += total.c[i].write_access * blen * dfi->buswidth[i];
+ break;
+ case PERF_EVENT_READ_BYTES0:
+ count = total.c[0].read_access * blen * dfi->buswidth[0];
+ break;
+ case PERF_EVENT_WRITE_BYTES0:
+ count = total.c[0].write_access * blen * dfi->buswidth[0];
+ break;
+ case PERF_EVENT_READ_BYTES1:
+ count = total.c[1].read_access * blen * dfi->buswidth[1];
+ break;
+ case PERF_EVENT_WRITE_BYTES1:
+ count = total.c[1].write_access * blen * dfi->buswidth[1];
+ break;
+ case PERF_EVENT_READ_BYTES2:
+ count = total.c[2].read_access * blen * dfi->buswidth[2];
+ break;
+ case PERF_EVENT_WRITE_BYTES2:
+ count = total.c[2].write_access * blen * dfi->buswidth[2];
+ break;
+ case PERF_EVENT_READ_BYTES3:
+ count = total.c[3].read_access * blen * dfi->buswidth[3];
+ break;
+ case PERF_EVENT_WRITE_BYTES3:
+ count = total.c[3].write_access * blen * dfi->buswidth[3];
+ break;
+ case PERF_EVENT_BYTES:
+ for (i = 0; i < dfi->max_channels; i++)
+ count += total.c[i].access * blen * dfi->buswidth[i];
+ break;
+ }
+
+ return count;
+}
+
+static void rockchip_ddr_perf_event_update(struct perf_event *event)
+{
+ u64 now;
+ s64 prev;
+
+ if (event->attr.config >= PERF_ACCESS_TYPE_MAX)
+ return;
+
+ now = rockchip_ddr_perf_event_get_count(event);
+ prev = local64_xchg(&event->hw.prev_count, now);
+ local64_add(now - prev, &event->count);
+}
+
+static void rockchip_ddr_perf_event_start(struct perf_event *event, int flags)
+{
+ u64 now = rockchip_ddr_perf_event_get_count(event);
+
+ local64_set(&event->hw.prev_count, now);
+}
+
+static int rockchip_ddr_perf_event_add(struct perf_event *event, int flags)
+{
+ struct rockchip_dfi *dfi = container_of(event->pmu, struct rockchip_dfi, pmu);
+
+ dfi->active_events++;
+
+ if (dfi->active_events == 1) {
+ dfi->total_count = (struct dmc_count){};
+ rockchip_dfi_read_counters(dfi, &dfi->last_perf_count);
+ hrtimer_start(&dfi->timer, ns_to_ktime(NSEC_PER_SEC), HRTIMER_MODE_REL);
+ }
+
+ if (flags & PERF_EF_START)
+ rockchip_ddr_perf_event_start(event, flags);
+
+ return 0;
+}
+
+static void rockchip_ddr_perf_event_stop(struct perf_event *event, int flags)
+{
+ rockchip_ddr_perf_event_update(event);
+}
+
+static void rockchip_ddr_perf_event_del(struct perf_event *event, int flags)
+{
+ struct rockchip_dfi *dfi = container_of(event->pmu, struct rockchip_dfi, pmu);
+
+ rockchip_ddr_perf_event_stop(event, PERF_EF_UPDATE);
+
+ dfi->active_events--;
+
+ if (dfi->active_events == 0)
+ hrtimer_cancel(&dfi->timer);
+}
+
+static enum hrtimer_restart rockchip_dfi_timer(struct hrtimer *timer)
+{
+ struct rockchip_dfi *dfi = container_of(timer, struct rockchip_dfi, timer);
+ struct dmc_count now, total;
+
+ rockchip_dfi_read_counters(dfi, &now);
+
+ write_seqlock(&dfi->count_seqlock);
+
+ rockchip_ddr_perf_counters_add(dfi, &now, &total);
+ dfi->total_count = total;
+ dfi->last_perf_count = now;
+
+ write_sequnlock(&dfi->count_seqlock);
+
+ hrtimer_forward_now(&dfi->timer, ns_to_ktime(NSEC_PER_SEC));
+
+ return HRTIMER_RESTART;
+};
+
+static int ddr_perf_offline_cpu(unsigned int cpu, struct hlist_node *node)
+{
+ struct rockchip_dfi *dfi = hlist_entry_safe(node, struct rockchip_dfi, node);
+ int target;
+
+ if (cpu != dfi->cpu)
+ return 0;
+
+ target = cpumask_any_but(cpu_online_mask, cpu);
+ if (target >= nr_cpu_ids)
+ return 0;
+
+ perf_pmu_migrate_context(&dfi->pmu, cpu, target);
+ dfi->cpu = target;
+
+ return 0;
+}
+
+static void rockchip_ddr_cpuhp_remove_state(void *data)
+{
+ struct rockchip_dfi *dfi = data;
+
+ cpuhp_remove_multi_state(dfi->cpuhp_state);
+
+ rockchip_dfi_disable(dfi);
+}
+
+static void rockchip_ddr_cpuhp_remove_instance(void *data)
+{
+ struct rockchip_dfi *dfi = data;
+
+ cpuhp_state_remove_instance_nocalls(dfi->cpuhp_state, &dfi->node);
+}
+
+static void rockchip_ddr_perf_remove(void *data)
+{
+ struct rockchip_dfi *dfi = data;
+
+ perf_pmu_unregister(&dfi->pmu);
+}
+
+static int rockchip_ddr_perf_init(struct rockchip_dfi *dfi)
+{
+ struct pmu *pmu = &dfi->pmu;
+ int ret;
+
+ seqlock_init(&dfi->count_seqlock);
+
+ pmu->module = THIS_MODULE;
+ pmu->capabilities = PERF_PMU_CAP_NO_EXCLUDE;
+ pmu->task_ctx_nr = perf_invalid_context;
+ pmu->attr_groups = attr_groups;
+ pmu->event_init = rockchip_ddr_perf_event_init;
+ pmu->add = rockchip_ddr_perf_event_add;
+ pmu->del = rockchip_ddr_perf_event_del;
+ pmu->start = rockchip_ddr_perf_event_start;
+ pmu->stop = rockchip_ddr_perf_event_stop;
+ pmu->read = rockchip_ddr_perf_event_update;
+
+ dfi->cpu = raw_smp_processor_id();
+
+ ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
+ "rockchip_ddr_perf_pmu",
+ NULL,
+ ddr_perf_offline_cpu);
+
+ if (ret < 0) {
+ dev_err(dfi->dev, "cpuhp_setup_state_multi failed: %d\n", ret);
+ return ret;
+ }
+
+ dfi->cpuhp_state = ret;
+
+ rockchip_dfi_enable(dfi);
+
+ ret = devm_add_action_or_reset(dfi->dev, rockchip_ddr_cpuhp_remove_state, dfi);
+ if (ret)
+ return ret;
+
+ ret = cpuhp_state_add_instance_nocalls(dfi->cpuhp_state, &dfi->node);
+ if (ret) {
+ dev_err(dfi->dev, "Error %d registering hotplug\n", ret);
+ return ret;
+ }
+
+ ret = devm_add_action_or_reset(dfi->dev, rockchip_ddr_cpuhp_remove_instance, dfi);
+ if (ret)
+ return ret;
+
+ hrtimer_init(&dfi->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
+ dfi->timer.function = rockchip_dfi_timer;
+
+ switch (dfi->ddr_type) {
+ case ROCKCHIP_DDRTYPE_LPDDR2:
+ case ROCKCHIP_DDRTYPE_LPDDR3:
+ dfi->burst_len = 8;
+ break;
+ case ROCKCHIP_DDRTYPE_LPDDR4:
+ case ROCKCHIP_DDRTYPE_LPDDR4X:
+ dfi->burst_len = 16;
+ break;
+ }
+
+ ret = perf_pmu_register(pmu, "rockchip_ddr", -1);
+ if (ret)
+ return ret;
+
+ return devm_add_action_or_reset(dfi->dev, rockchip_ddr_perf_remove, dfi);
+}
+#else
+static int rockchip_ddr_perf_init(struct rockchip_dfi *dfi)
+{
+ return 0;
+}
+#endif
+
static int rk3399_dfi_init(struct rockchip_dfi *dfi)
{
struct regmap *regmap_pmu = dfi->regmap_pmu;
@@ -241,6 +661,9 @@ static int rk3399_dfi_init(struct rockchip_dfi *dfi)
dfi->channel_mask = GENMASK(1, 0);
dfi->max_channels = 2;
+ dfi->buswidth[0] = FIELD_GET(RK3399_PMUGRF_OS_REG2_BW_CH0, val) == 0 ? 4 : 2;
+ dfi->buswidth[1] = FIELD_GET(RK3399_PMUGRF_OS_REG2_BW_CH1, val) == 0 ? 4 : 2;
+
return 0;
};
@@ -265,6 +688,8 @@ static int rk3568_dfi_init(struct rockchip_dfi *dfi)
dfi->channel_mask = BIT(0);
dfi->max_channels = 1;
+ dfi->buswidth[0] = FIELD_GET(RK3568_PMUGRF_OS_REG2_BW_CH0, reg2) == 0 ? 4 : 2;
+
return 0;
};
@@ -325,6 +750,10 @@ static int rockchip_dfi_probe(struct platform_device *pdev)
return PTR_ERR(dfi->edev);
}
+ ret = rockchip_ddr_perf_init(dfi);
+ if (ret)
+ return ret;
+
platform_set_drvdata(pdev, dfi);
return 0;
@@ -335,6 +764,7 @@ static struct platform_driver rockchip_dfi_driver = {
.driver = {
.name = "rockchip-dfi",
.of_match_table = rockchip_dfi_id_match,
+ .suppress_bind_attrs = true,
},
};
module_platform_driver(rockchip_dfi_driver);
diff --git a/include/soc/rockchip/rk3399_grf.h b/include/soc/rockchip/rk3399_grf.h
index 775f8444bea8d..39cd44cec982f 100644
--- a/include/soc/rockchip/rk3399_grf.h
+++ b/include/soc/rockchip/rk3399_grf.h
@@ -12,5 +12,7 @@
/* PMU GRF Registers */
#define RK3399_PMUGRF_OS_REG2 0x308
#define RK3399_PMUGRF_OS_REG2_DDRTYPE GENMASK(15, 13)
+#define RK3399_PMUGRF_OS_REG2_BW_CH0 GENMASK(3, 2)
+#define RK3399_PMUGRF_OS_REG2_BW_CH1 GENMASK(19, 18)
#endif
diff --git a/include/soc/rockchip/rk3568_grf.h b/include/soc/rockchip/rk3568_grf.h
index 575584e9d8834..52853efd6720e 100644
--- a/include/soc/rockchip/rk3568_grf.h
+++ b/include/soc/rockchip/rk3568_grf.h
@@ -4,6 +4,7 @@
#define RK3568_PMUGRF_OS_REG2 0x208
#define RK3568_PMUGRF_OS_REG2_DRAMTYPE_INFO GENMASK(15, 13)
+#define RK3568_PMUGRF_OS_REG2_BW_CH0 GENMASK(3, 2)
#define RK3568_PMUGRF_OS_REG3 0x20c
#define RK3568_PMUGRF_OS_REG3_DRAMTYPE_INFO_V3 GENMASK(13, 12)
--
2.39.2
No need for an extra allocation, just embed the struct
devfreq_event_desc into the private data struct.
Reviewed-by: Heiko Stuebner <[email protected]>
Reviewed-by: Jonathan Cameron <[email protected]>
Reviewed-by: Sebastian Reichel <[email protected]>
Signed-off-by: Sascha Hauer <[email protected]>
---
drivers/devfreq/event/rockchip-dfi.c | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c
index 74893c06aa087..467f9f42d38f7 100644
--- a/drivers/devfreq/event/rockchip-dfi.c
+++ b/drivers/devfreq/event/rockchip-dfi.c
@@ -49,7 +49,7 @@ struct dmc_usage {
*/
struct rockchip_dfi {
struct devfreq_event_dev *edev;
- struct devfreq_event_desc *desc;
+ struct devfreq_event_desc desc;
struct dmc_usage ch_usage[RK3399_DMC_NUM_CH];
struct device *dev;
void __iomem *regs;
@@ -204,14 +204,10 @@ static int rockchip_dfi_probe(struct platform_device *pdev)
data->dev = dev;
- desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
- if (!desc)
- return -ENOMEM;
-
+ desc = &data->desc;
desc->ops = &rockchip_dfi_ops;
desc->driver_data = data;
desc->name = np->name;
- data->desc = desc;
data->edev = devm_devfreq_event_add_edev(&pdev->dev, desc);
if (IS_ERR(data->edev)) {
--
2.39.2
Heiko,
Could you provide your Ack for this patch?
Thanks
Sascha
On Wed, Oct 18, 2023 at 08:16:56AM +0200, Sascha Hauer wrote:
> The DDRTYPE defines are named to be RK3399 specific, but they can be
> used for other Rockchip SoCs as well, so replace the RK3399_PMUGRF_
> prefix with ROCKCHIP_. They are defined in a SoC specific header
> file, so when generalizing the prefix also move the new defines to
> a SoC agnostic header file. While at it use GENMASK to define the
> DDRTYPE bitfield and give it a name including the full register name.
>
> Reviewed-by: Sebastian Reichel <[email protected]>
> Acked-by: Chanwoo Choi <[email protected]>
> Signed-off-by: Sascha Hauer <[email protected]>
> ---
> drivers/devfreq/event/rockchip-dfi.c | 9 +++++----
> drivers/devfreq/rk3399_dmc.c | 10 +++++-----
> include/soc/rockchip/rk3399_grf.h | 7 +------
> include/soc/rockchip/rockchip_grf.h | 17 +++++++++++++++++
> 4 files changed, 28 insertions(+), 15 deletions(-)
> create mode 100644 include/soc/rockchip/rockchip_grf.h
>
> diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c
> index 28c18bbf6baa5..82d18c60538a5 100644
> --- a/drivers/devfreq/event/rockchip-dfi.c
> +++ b/drivers/devfreq/event/rockchip-dfi.c
> @@ -18,8 +18,10 @@
> #include <linux/list.h>
> #include <linux/of.h>
> #include <linux/of_device.h>
> +#include <linux/bitfield.h>
> #include <linux/bits.h>
>
> +#include <soc/rockchip/rockchip_grf.h>
> #include <soc/rockchip/rk3399_grf.h>
>
> #define DMC_MAX_CHANNELS 2
> @@ -75,9 +77,9 @@ static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
> writel_relaxed(CLR_DDRMON_CTRL, dfi_regs + DDRMON_CTRL);
>
> /* set ddr type to dfi */
> - if (dfi->ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR3)
> + if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR3)
> writel_relaxed(LPDDR3_EN, dfi_regs + DDRMON_CTRL);
> - else if (dfi->ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR4)
> + else if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR4)
> writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL);
>
> /* enable count, use software mode */
> @@ -192,8 +194,7 @@ static int rk3399_dfi_init(struct rockchip_dfi *dfi)
>
> /* get ddr type */
> regmap_read(regmap_pmu, RK3399_PMUGRF_OS_REG2, &val);
> - dfi->ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) &
> - RK3399_PMUGRF_DDRTYPE_MASK;
> + dfi->ddr_type = FIELD_GET(RK3399_PMUGRF_OS_REG2_DDRTYPE, val);
>
> dfi->channel_mask = GENMASK(1, 0);
> dfi->max_channels = 2;
> diff --git a/drivers/devfreq/rk3399_dmc.c b/drivers/devfreq/rk3399_dmc.c
> index daff407026157..fd2c5ffedf41e 100644
> --- a/drivers/devfreq/rk3399_dmc.c
> +++ b/drivers/devfreq/rk3399_dmc.c
> @@ -22,6 +22,7 @@
> #include <linux/suspend.h>
>
> #include <soc/rockchip/pm_domains.h>
> +#include <soc/rockchip/rockchip_grf.h>
> #include <soc/rockchip/rk3399_grf.h>
> #include <soc/rockchip/rockchip_sip.h>
>
> @@ -381,17 +382,16 @@ static int rk3399_dmcfreq_probe(struct platform_device *pdev)
> }
>
> regmap_read(data->regmap_pmu, RK3399_PMUGRF_OS_REG2, &val);
> - ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) &
> - RK3399_PMUGRF_DDRTYPE_MASK;
> + ddr_type = FIELD_GET(RK3399_PMUGRF_OS_REG2_DDRTYPE, val);
>
> switch (ddr_type) {
> - case RK3399_PMUGRF_DDRTYPE_DDR3:
> + case ROCKCHIP_DDRTYPE_DDR3:
> data->odt_dis_freq = data->ddr3_odt_dis_freq;
> break;
> - case RK3399_PMUGRF_DDRTYPE_LPDDR3:
> + case ROCKCHIP_DDRTYPE_LPDDR3:
> data->odt_dis_freq = data->lpddr3_odt_dis_freq;
> break;
> - case RK3399_PMUGRF_DDRTYPE_LPDDR4:
> + case ROCKCHIP_DDRTYPE_LPDDR4:
> data->odt_dis_freq = data->lpddr4_odt_dis_freq;
> break;
> default:
> diff --git a/include/soc/rockchip/rk3399_grf.h b/include/soc/rockchip/rk3399_grf.h
> index 3eebabcb28123..775f8444bea8d 100644
> --- a/include/soc/rockchip/rk3399_grf.h
> +++ b/include/soc/rockchip/rk3399_grf.h
> @@ -11,11 +11,6 @@
>
> /* PMU GRF Registers */
> #define RK3399_PMUGRF_OS_REG2 0x308
> -#define RK3399_PMUGRF_DDRTYPE_SHIFT 13
> -#define RK3399_PMUGRF_DDRTYPE_MASK 7
> -#define RK3399_PMUGRF_DDRTYPE_DDR3 3
> -#define RK3399_PMUGRF_DDRTYPE_LPDDR2 5
> -#define RK3399_PMUGRF_DDRTYPE_LPDDR3 6
> -#define RK3399_PMUGRF_DDRTYPE_LPDDR4 7
> +#define RK3399_PMUGRF_OS_REG2_DDRTYPE GENMASK(15, 13)
>
> #endif
> diff --git a/include/soc/rockchip/rockchip_grf.h b/include/soc/rockchip/rockchip_grf.h
> new file mode 100644
> index 0000000000000..dde1a9796ccb5
> --- /dev/null
> +++ b/include/soc/rockchip/rockchip_grf.h
> @@ -0,0 +1,17 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Rockchip General Register Files definitions
> + */
> +
> +#ifndef __SOC_ROCKCHIP_GRF_H
> +#define __SOC_ROCKCHIP_GRF_H
> +
> +/* Rockchip DDRTYPE defines */
> +enum {
> + ROCKCHIP_DDRTYPE_DDR3 = 3,
> + ROCKCHIP_DDRTYPE_LPDDR2 = 5,
> + ROCKCHIP_DDRTYPE_LPDDR3 = 6,
> + ROCKCHIP_DDRTYPE_LPDDR4 = 7,
> +};
> +
> +#endif /* __SOC_ROCKCHIP_GRF_H */
> --
> 2.39.2
>
>
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
Hi Sascha,
kernel test robot noticed the following build warnings:
[auto build test WARNING on linus/master]
[also build test WARNING on v6.6-rc6]
[cannot apply to next-20231018]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Sascha-Hauer/PM-devfreq-rockchip-dfi-Make-pmu-regmap-mandatory/20231018-142228
base: linus/master
patch link: https://lore.kernel.org/r/20231018061714.3553817-17-s.hauer%40pengutronix.de
patch subject: [PATCH v8 16/26] PM / devfreq: rockchip-dfi: Add perf support
config: m68k-allyesconfig (https://download.01.org/0day-ci/archive/20231018/[email protected]/config)
compiler: m68k-linux-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20231018/[email protected]/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <[email protected]>
| Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/
All warnings (new ones prefixed by >>):
>> drivers/devfreq/event/rockchip-dfi.c:203:13: warning: 'rockchip_ddr_perf_counters_add' defined but not used [-Wunused-function]
203 | static void rockchip_ddr_perf_counters_add(struct rockchip_dfi *dfi,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
--
>> drivers/devfreq/event/rockchip-dfi.c:79: warning: Function parameter or member 'write_access' not described in 'dmc_count_channel'
vim +/rockchip_ddr_perf_counters_add +203 drivers/devfreq/event/rockchip-dfi.c
66
67 /**
68 * struct dmc_count_channel - structure to hold counter values from the DDR controller
69 * @access: Number of read and write accesses
70 * @clock_cycles: DDR clock cycles
71 * @read_access: number of read accesses
72 * @write_acccess: number of write accesses
73 */
74 struct dmc_count_channel {
75 u64 access;
76 u64 clock_cycles;
77 u64 read_access;
78 u64 write_access;
> 79 };
80
81 struct dmc_count {
82 struct dmc_count_channel c[DMC_MAX_CHANNELS];
83 };
84
85 /*
86 * The dfi controller can monitor DDR load. It has an upper and lower threshold
87 * for the operating points. Whenever the usage leaves these bounds an event is
88 * generated to indicate the DDR frequency should be changed.
89 */
90 struct rockchip_dfi {
91 struct devfreq_event_dev *edev;
92 struct devfreq_event_desc desc;
93 struct dmc_count last_event_count;
94
95 struct dmc_count last_perf_count;
96 struct dmc_count total_count;
97 seqlock_t count_seqlock; /* protects last_perf_count and total_count */
98
99 struct device *dev;
100 void __iomem *regs;
101 struct regmap *regmap_pmu;
102 struct clk *clk;
103 int usecount;
104 struct mutex mutex;
105 u32 ddr_type;
106 unsigned int channel_mask;
107 unsigned int max_channels;
108 enum cpuhp_state cpuhp_state;
109 struct hlist_node node;
110 struct pmu pmu;
111 struct hrtimer timer;
112 unsigned int cpu;
113 int active_events;
114 int burst_len;
115 int buswidth[DMC_MAX_CHANNELS];
116 };
117
118 static int rockchip_dfi_enable(struct rockchip_dfi *dfi)
119 {
120 void __iomem *dfi_regs = dfi->regs;
121 int ret = 0;
122
123 mutex_lock(&dfi->mutex);
124
125 dfi->usecount++;
126 if (dfi->usecount > 1)
127 goto out;
128
129 ret = clk_prepare_enable(dfi->clk);
130 if (ret) {
131 dev_err(&dfi->edev->dev, "failed to enable dfi clk: %d\n", ret);
132 goto out;
133 }
134
135 /* clear DDRMON_CTRL setting */
136 writel_relaxed(HIWORD_UPDATE(0, DDRMON_CTRL_TIMER_CNT_EN | DDRMON_CTRL_SOFTWARE_EN |
137 DDRMON_CTRL_HARDWARE_EN), dfi_regs + DDRMON_CTRL);
138
139 /* set ddr type to dfi */
140 switch (dfi->ddr_type) {
141 case ROCKCHIP_DDRTYPE_LPDDR2:
142 case ROCKCHIP_DDRTYPE_LPDDR3:
143 writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR23, DDRMON_CTRL_DDR_TYPE_MASK),
144 dfi_regs + DDRMON_CTRL);
145 break;
146 case ROCKCHIP_DDRTYPE_LPDDR4:
147 case ROCKCHIP_DDRTYPE_LPDDR4X:
148 writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR4, DDRMON_CTRL_DDR_TYPE_MASK),
149 dfi_regs + DDRMON_CTRL);
150 break;
151 default:
152 break;
153 }
154
155 /* enable count, use software mode */
156 writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_SOFTWARE_EN, DDRMON_CTRL_SOFTWARE_EN),
157 dfi_regs + DDRMON_CTRL);
158 out:
159 mutex_unlock(&dfi->mutex);
160
161 return ret;
162 }
163
164 static void rockchip_dfi_disable(struct rockchip_dfi *dfi)
165 {
166 void __iomem *dfi_regs = dfi->regs;
167
168 mutex_lock(&dfi->mutex);
169
170 dfi->usecount--;
171
172 WARN_ON_ONCE(dfi->usecount < 0);
173
174 if (dfi->usecount > 0)
175 goto out;
176
177 writel_relaxed(HIWORD_UPDATE(0, DDRMON_CTRL_SOFTWARE_EN),
178 dfi_regs + DDRMON_CTRL);
179 clk_disable_unprepare(dfi->clk);
180 out:
181 mutex_unlock(&dfi->mutex);
182 }
183
184 static void rockchip_dfi_read_counters(struct rockchip_dfi *dfi, struct dmc_count *res)
185 {
186 u32 i;
187 void __iomem *dfi_regs = dfi->regs;
188
189 for (i = 0; i < dfi->max_channels; i++) {
190 if (!(dfi->channel_mask & BIT(i)))
191 continue;
192 res->c[i].read_access = readl_relaxed(dfi_regs +
193 DDRMON_CH0_RD_NUM + i * 20);
194 res->c[i].write_access = readl_relaxed(dfi_regs +
195 DDRMON_CH0_WR_NUM + i * 20);
196 res->c[i].access = readl_relaxed(dfi_regs +
197 DDRMON_CH0_DFI_ACCESS_NUM + i * 20);
198 res->c[i].clock_cycles = readl_relaxed(dfi_regs +
199 DDRMON_CH0_COUNT_NUM + i * 20);
200 }
201 }
202
> 203 static void rockchip_ddr_perf_counters_add(struct rockchip_dfi *dfi,
204 const struct dmc_count *now,
205 struct dmc_count *res)
206 {
207 const struct dmc_count *last = &dfi->last_perf_count;
208 int i;
209
210 for (i = 0; i < dfi->max_channels; i++) {
211 res->c[i].read_access = dfi->total_count.c[i].read_access +
212 (u32)(now->c[i].read_access - last->c[i].read_access);
213 res->c[i].write_access = dfi->total_count.c[i].write_access +
214 (u32)(now->c[i].write_access - last->c[i].write_access);
215 res->c[i].access = dfi->total_count.c[i].access +
216 (u32)(now->c[i].access - last->c[i].access);
217 res->c[i].clock_cycles = dfi->total_count.c[i].clock_cycles +
218 (u32)(now->c[i].clock_cycles - last->c[i].clock_cycles);
219 }
220 }
221
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
On 23. 10. 18. 15:16, Sascha Hauer wrote:
> As a matter of fact the regmap_pmu already is mandatory because
> it is used unconditionally in the driver. Bail out gracefully in
> probe() rather than crashing later.
>
> Fixes: b9d1262bca0af ("PM / devfreq: event: support rockchip dfi controller")
> Reviewed-by: Sebastian Reichel <[email protected]>
> Signed-off-by: Sascha Hauer <[email protected]>
> ---
>
> Notes:
> Changes since v4:
> - move to beginning of the series to make it easier to backport to stable
> - Add a Fixes: tag
> - add missing of_node_put()
>
> drivers/devfreq/event/rockchip-dfi.c | 15 ++++++++-------
> 1 file changed, 8 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c
> index 39ac069cabc75..74893c06aa087 100644
> --- a/drivers/devfreq/event/rockchip-dfi.c
> +++ b/drivers/devfreq/event/rockchip-dfi.c
> @@ -193,14 +193,15 @@ static int rockchip_dfi_probe(struct platform_device *pdev)
> return dev_err_probe(dev, PTR_ERR(data->clk),
> "Cannot get the clk pclk_ddr_mon\n");
>
> - /* try to find the optional reference to the pmu syscon */
> node = of_parse_phandle(np, "rockchip,pmu", 0);
> - if (node) {
> - data->regmap_pmu = syscon_node_to_regmap(node);
> - of_node_put(node);
> - if (IS_ERR(data->regmap_pmu))
> - return PTR_ERR(data->regmap_pmu);
> - }
> + if (!node)
> + return dev_err_probe(&pdev->dev, -ENODEV, "Can't find pmu_grf registers\n");
> +
> + data->regmap_pmu = syscon_node_to_regmap(node);
> + of_node_put(node);
> + if (IS_ERR(data->regmap_pmu))
> + return PTR_ERR(data->regmap_pmu);
> +
> data->dev = dev;
>
> desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
Already applied it on v7.
--
Best Regards,
Samsung Electronics
Chanwoo Choi
On 23. 10. 18. 15:16, Sascha Hauer wrote:
> No need for an extra allocation, just embed the struct
> devfreq_event_desc into the private data struct.
>
> Reviewed-by: Heiko Stuebner <[email protected]>
> Reviewed-by: Jonathan Cameron <[email protected]>
> Reviewed-by: Sebastian Reichel <[email protected]>
> Signed-off-by: Sascha Hauer <[email protected]>
> ---
> drivers/devfreq/event/rockchip-dfi.c | 8 ++------
> 1 file changed, 2 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c
> index 74893c06aa087..467f9f42d38f7 100644
> --- a/drivers/devfreq/event/rockchip-dfi.c
> +++ b/drivers/devfreq/event/rockchip-dfi.c
> @@ -49,7 +49,7 @@ struct dmc_usage {
> */
> struct rockchip_dfi {
> struct devfreq_event_dev *edev;
> - struct devfreq_event_desc *desc;
> + struct devfreq_event_desc desc;
> struct dmc_usage ch_usage[RK3399_DMC_NUM_CH];
> struct device *dev;
> void __iomem *regs;
> @@ -204,14 +204,10 @@ static int rockchip_dfi_probe(struct platform_device *pdev)
>
> data->dev = dev;
>
> - desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
> - if (!desc)
> - return -ENOMEM;
> -
> + desc = &data->desc;
> desc->ops = &rockchip_dfi_ops;
> desc->driver_data = data;
> desc->name = np->name;
> - data->desc = desc;
>
> data->edev = devm_devfreq_event_add_edev(&pdev->dev, desc);
> if (IS_ERR(data->edev)) {
Already applied it on v7.
--
Best Regards,
Samsung Electronics
Chanwoo Choi
On 23. 10. 18. 15:16, Sascha Hauer wrote:
> The variable name for the private data struct is 'info' in some
> functions and 'data' in others. Both names do not give a clue what
> type the variable has, so consistently use 'dfi'.
>
> Reviewed-by: Heiko Stuebner <[email protected]>
> Reviewed-by: Jonathan Cameron <[email protected]>
> Reviewed-by: Sebastian Reichel <[email protected]>
> Signed-off-by: Sascha Hauer <[email protected]>
> ---
> drivers/devfreq/event/rockchip-dfi.c | 72 ++++++++++++++--------------
> 1 file changed, 36 insertions(+), 36 deletions(-)
>
> diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c
> index 467f9f42d38f7..e19e5acaa362c 100644
> --- a/drivers/devfreq/event/rockchip-dfi.c
> +++ b/drivers/devfreq/event/rockchip-dfi.c
> @@ -59,13 +59,13 @@ struct rockchip_dfi {
>
> static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
> {
> - struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
> - void __iomem *dfi_regs = info->regs;
> + struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);
> + void __iomem *dfi_regs = dfi->regs;
> u32 val;
> u32 ddr_type;
>
> /* get ddr type */
> - regmap_read(info->regmap_pmu, RK3399_PMUGRF_OS_REG2, &val);
> + regmap_read(dfi->regmap_pmu, RK3399_PMUGRF_OS_REG2, &val);
> ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) &
> RK3399_PMUGRF_DDRTYPE_MASK;
>
> @@ -84,28 +84,28 @@ static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
>
> static void rockchip_dfi_stop_hardware_counter(struct devfreq_event_dev *edev)
> {
> - struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
> - void __iomem *dfi_regs = info->regs;
> + struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);
> + void __iomem *dfi_regs = dfi->regs;
>
> writel_relaxed(SOFTWARE_DIS, dfi_regs + DDRMON_CTRL);
> }
>
> static int rockchip_dfi_get_busier_ch(struct devfreq_event_dev *edev)
> {
> - struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
> + struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);
> u32 tmp, max = 0;
> u32 i, busier_ch = 0;
> - void __iomem *dfi_regs = info->regs;
> + void __iomem *dfi_regs = dfi->regs;
>
> rockchip_dfi_stop_hardware_counter(edev);
>
> /* Find out which channel is busier */
> for (i = 0; i < RK3399_DMC_NUM_CH; i++) {
> - info->ch_usage[i].access = readl_relaxed(dfi_regs +
> + dfi->ch_usage[i].access = readl_relaxed(dfi_regs +
> DDRMON_CH0_DFI_ACCESS_NUM + i * 20) * 4;
> - info->ch_usage[i].total = readl_relaxed(dfi_regs +
> + dfi->ch_usage[i].total = readl_relaxed(dfi_regs +
> DDRMON_CH0_COUNT_NUM + i * 20);
> - tmp = info->ch_usage[i].access;
> + tmp = dfi->ch_usage[i].access;
> if (tmp > max) {
> busier_ch = i;
> max = tmp;
> @@ -118,20 +118,20 @@ static int rockchip_dfi_get_busier_ch(struct devfreq_event_dev *edev)
>
> static int rockchip_dfi_disable(struct devfreq_event_dev *edev)
> {
> - struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
> + struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);
>
> rockchip_dfi_stop_hardware_counter(edev);
> - clk_disable_unprepare(info->clk);
> + clk_disable_unprepare(dfi->clk);
>
> return 0;
> }
>
> static int rockchip_dfi_enable(struct devfreq_event_dev *edev)
> {
> - struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
> + struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);
> int ret;
>
> - ret = clk_prepare_enable(info->clk);
> + ret = clk_prepare_enable(dfi->clk);
> if (ret) {
> dev_err(&edev->dev, "failed to enable dfi clk: %d\n", ret);
> return ret;
> @@ -149,13 +149,13 @@ static int rockchip_dfi_set_event(struct devfreq_event_dev *edev)
> static int rockchip_dfi_get_event(struct devfreq_event_dev *edev,
> struct devfreq_event_data *edata)
> {
> - struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
> + struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);
> int busier_ch;
>
> busier_ch = rockchip_dfi_get_busier_ch(edev);
>
> - edata->load_count = info->ch_usage[busier_ch].access;
> - edata->total_count = info->ch_usage[busier_ch].total;
> + edata->load_count = dfi->ch_usage[busier_ch].access;
> + edata->total_count = dfi->ch_usage[busier_ch].total;
>
> return 0;
> }
> @@ -176,47 +176,47 @@ MODULE_DEVICE_TABLE(of, rockchip_dfi_id_match);
> static int rockchip_dfi_probe(struct platform_device *pdev)
> {
> struct device *dev = &pdev->dev;
> - struct rockchip_dfi *data;
> + struct rockchip_dfi *dfi;
> struct devfreq_event_desc *desc;
> struct device_node *np = pdev->dev.of_node, *node;
>
> - data = devm_kzalloc(dev, sizeof(struct rockchip_dfi), GFP_KERNEL);
> - if (!data)
> + dfi = devm_kzalloc(dev, sizeof(*dfi), GFP_KERNEL);
> + if (!dfi)
> return -ENOMEM;
>
> - data->regs = devm_platform_ioremap_resource(pdev, 0);
> - if (IS_ERR(data->regs))
> - return PTR_ERR(data->regs);
> + dfi->regs = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(dfi->regs))
> + return PTR_ERR(dfi->regs);
>
> - data->clk = devm_clk_get(dev, "pclk_ddr_mon");
> - if (IS_ERR(data->clk))
> - return dev_err_probe(dev, PTR_ERR(data->clk),
> + dfi->clk = devm_clk_get(dev, "pclk_ddr_mon");
> + if (IS_ERR(dfi->clk))
> + return dev_err_probe(dev, PTR_ERR(dfi->clk),
> "Cannot get the clk pclk_ddr_mon\n");
>
> node = of_parse_phandle(np, "rockchip,pmu", 0);
> if (!node)
> return dev_err_probe(&pdev->dev, -ENODEV, "Can't find pmu_grf registers\n");
>
> - data->regmap_pmu = syscon_node_to_regmap(node);
> + dfi->regmap_pmu = syscon_node_to_regmap(node);
> of_node_put(node);
> - if (IS_ERR(data->regmap_pmu))
> - return PTR_ERR(data->regmap_pmu);
> + if (IS_ERR(dfi->regmap_pmu))
> + return PTR_ERR(dfi->regmap_pmu);
>
> - data->dev = dev;
> + dfi->dev = dev;
>
> - desc = &data->desc;
> + desc = &dfi->desc;
> desc->ops = &rockchip_dfi_ops;
> - desc->driver_data = data;
> + desc->driver_data = dfi;
> desc->name = np->name;
>
> - data->edev = devm_devfreq_event_add_edev(&pdev->dev, desc);
> - if (IS_ERR(data->edev)) {
> + dfi->edev = devm_devfreq_event_add_edev(&pdev->dev, desc);
> + if (IS_ERR(dfi->edev)) {
> dev_err(&pdev->dev,
> "failed to add devfreq-event device\n");
> - return PTR_ERR(data->edev);
> + return PTR_ERR(dfi->edev);
> }
>
> - platform_set_drvdata(pdev, data);
> + platform_set_drvdata(pdev, dfi);
>
> return 0;
> }
Already applied it on v7.
--
Best Regards,
Samsung Electronics
Chanwoo Choi
On 23. 10. 18. 15:16, Sascha Hauer wrote:
> Different Rockchip SoC variants have a different number of channels.
> Introduce a channel mask to make the number of channels configurable
> from SoC initialization code.
>
> Reviewed-by: Sebastian Reichel <[email protected]>
> Signed-off-by: Sascha Hauer <[email protected]>
> ---
>
> Notes:
> Changes since v7:
> - Loop only over channels present on a SoC
>
> drivers/devfreq/event/rockchip-dfi.c | 25 +++++++++++++++++++------
> 1 file changed, 19 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c
> index 126bb744645b6..28c18bbf6baa5 100644
> --- a/drivers/devfreq/event/rockchip-dfi.c
> +++ b/drivers/devfreq/event/rockchip-dfi.c
> @@ -18,10 +18,11 @@
> #include <linux/list.h>
> #include <linux/of.h>
> #include <linux/of_device.h>
> +#include <linux/bits.h>
>
> #include <soc/rockchip/rk3399_grf.h>
>
> -#define RK3399_DMC_NUM_CH 2
> +#define DMC_MAX_CHANNELS 2
>
> /* DDRMON_CTRL */
> #define DDRMON_CTRL 0x04
> @@ -44,7 +45,7 @@ struct dmc_count_channel {
> };
>
> struct dmc_count {
> - struct dmc_count_channel c[RK3399_DMC_NUM_CH];
> + struct dmc_count_channel c[DMC_MAX_CHANNELS];
> };
>
> /*
> @@ -61,6 +62,8 @@ struct rockchip_dfi {
> struct regmap *regmap_pmu;
> struct clk *clk;
> u32 ddr_type;
> + unsigned int channel_mask;
> + unsigned int max_channels;
> };
>
> static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
> @@ -95,7 +98,9 @@ static void rockchip_dfi_read_counters(struct devfreq_event_dev *edev, struct dm
> u32 i;
> void __iomem *dfi_regs = dfi->regs;
>
> - for (i = 0; i < RK3399_DMC_NUM_CH; i++) {
> + for (i = 0; i < dfi->max_channels; i++) {
> + if (!(dfi->channel_mask & BIT(i)))
> + continue;
> count->c[i].access = readl_relaxed(dfi_regs +
> DDRMON_CH0_DFI_ACCESS_NUM + i * 20);
> count->c[i].total = readl_relaxed(dfi_regs +
> @@ -145,9 +150,14 @@ static int rockchip_dfi_get_event(struct devfreq_event_dev *edev,
> rockchip_dfi_read_counters(edev, &count);
>
> /* We can only report one channel, so find the busiest one */
> - for (i = 0; i < RK3399_DMC_NUM_CH; i++) {
> - u32 a = count.c[i].access - last->c[i].access;
> - u32 t = count.c[i].total - last->c[i].total;
> + for (i = 0; i < dfi->max_channels; i++) {
> + u32 a, t;
> +
> + if (!(dfi->channel_mask & BIT(i)))
> + continue;
> +
> + a = count.c[i].access - last->c[i].access;
> + t = count.c[i].total - last->c[i].total;
>
> if (a > access) {
> access = a;
> @@ -185,6 +195,9 @@ static int rk3399_dfi_init(struct rockchip_dfi *dfi)
> dfi->ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) &
> RK3399_PMUGRF_DDRTYPE_MASK;
>
> + dfi->channel_mask = GENMASK(1, 0);
> + dfi->max_channels = 2;
> +
> return 0;
> };
>
Acked-by: Chanwoo Choi <[email protected]>
--
Best Regards,
Samsung Electronics
Chanwoo Choi
On 23. 10. 18. 15:16, Sascha Hauer wrote:
> This adds RK3568 support to the DFI driver. Only iniitialization
> differs from the currently supported RK3399.
>
> Signed-off-by: Sascha Hauer <[email protected]>
> ---
>
> Notes:
> Changes since v7:
> - Add comment to explain << 3
>
> drivers/devfreq/event/rockchip-dfi.c | 27 +++++++++++++++++++++++++++
> include/soc/rockchip/rk3568_grf.h | 12 ++++++++++++
> 2 files changed, 39 insertions(+)
> create mode 100644 include/soc/rockchip/rk3568_grf.h
>
> diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c
> index 12f9096879235..571d72d1abd1c 100644
> --- a/drivers/devfreq/event/rockchip-dfi.c
> +++ b/drivers/devfreq/event/rockchip-dfi.c
> @@ -23,6 +23,7 @@
>
> #include <soc/rockchip/rockchip_grf.h>
> #include <soc/rockchip/rk3399_grf.h>
> +#include <soc/rockchip/rk3568_grf.h>
>
> #define DMC_MAX_CHANNELS 2
>
> @@ -211,10 +212,36 @@ static int rk3399_dfi_init(struct rockchip_dfi *dfi)
> return 0;
> };
>
> +static int rk3568_dfi_init(struct rockchip_dfi *dfi)
> +{
> + struct regmap *regmap_pmu = dfi->regmap_pmu;
> + u32 reg2, reg3;
> +
> + regmap_read(regmap_pmu, RK3568_PMUGRF_OS_REG2, ®2);
> + regmap_read(regmap_pmu, RK3568_PMUGRF_OS_REG3, ®3);
> +
> + /* lower 3 bits of the DDR type */
> + dfi->ddr_type = FIELD_GET(RK3568_PMUGRF_OS_REG2_DRAMTYPE_INFO, reg2);
> +
> + /*
> + * For version three and higher the upper two bits of the DDR type are
> + * in RK3568_PMUGRF_OS_REG3
> + */
> + if (FIELD_GET(RK3568_PMUGRF_OS_REG3_SYSREG_VERSION, reg3) >= 0x3)
> + dfi->ddr_type |= FIELD_GET(RK3568_PMUGRF_OS_REG3_DRAMTYPE_INFO_V3, reg3) << 3;
> +
> + dfi->channel_mask = BIT(0);
> + dfi->max_channels = 1;
> +
> + return 0;
> +};
> +
> static const struct of_device_id rockchip_dfi_id_match[] = {
> { .compatible = "rockchip,rk3399-dfi", .data = rk3399_dfi_init },
> + { .compatible = "rockchip,rk3568-dfi", .data = rk3568_dfi_init },
> { },
> };
> +
> MODULE_DEVICE_TABLE(of, rockchip_dfi_id_match);
>
> static int rockchip_dfi_probe(struct platform_device *pdev)
> diff --git a/include/soc/rockchip/rk3568_grf.h b/include/soc/rockchip/rk3568_grf.h
> new file mode 100644
> index 0000000000000..575584e9d8834
> --- /dev/null
> +++ b/include/soc/rockchip/rk3568_grf.h
> @@ -0,0 +1,12 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +#ifndef __SOC_RK3568_GRF_H
> +#define __SOC_RK3568_GRF_H
> +
> +#define RK3568_PMUGRF_OS_REG2 0x208
> +#define RK3568_PMUGRF_OS_REG2_DRAMTYPE_INFO GENMASK(15, 13)
> +
> +#define RK3568_PMUGRF_OS_REG3 0x20c
> +#define RK3568_PMUGRF_OS_REG3_DRAMTYPE_INFO_V3 GENMASK(13, 12)
> +#define RK3568_PMUGRF_OS_REG3_SYSREG_VERSION GENMASK(31, 28)
> +
> +#endif /* __SOC_RK3568_GRF_H */
Acked-by: Chanwoo Choi <[email protected]>
--
Best Regards,
Samsung Electronics
Chanwoo Choi
On 23. 10. 18. 15:16, Sascha Hauer wrote:
> According to the downstream driver the DDRMON_CTRL_LPDDR23 bit must be
> set for both LPDDR2 and LPDDR3. Add the missing LPDDR2 case and while
> at it turn the if/else if/else into switch/case which makes it easier
> to read.
>
> Reviewed-by: Jonathan Cameron <[email protected]>
> Reviewed-by: Sebastian Reichel <[email protected]>
> Acked-by: Chanwoo Choi <[email protected]>
> Signed-off-by: Sascha Hauer <[email protected]>
> ---
> drivers/devfreq/event/rockchip-dfi.c | 11 +++++++++--
> 1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c
> index 571d72d1abd1c..8ce0191552ef1 100644
> --- a/drivers/devfreq/event/rockchip-dfi.c
> +++ b/drivers/devfreq/event/rockchip-dfi.c
> @@ -83,12 +83,19 @@ static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
> DDRMON_CTRL_HARDWARE_EN), dfi_regs + DDRMON_CTRL);
>
> /* set ddr type to dfi */
> - if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR3)
> + switch (dfi->ddr_type) {
> + case ROCKCHIP_DDRTYPE_LPDDR2:
> + case ROCKCHIP_DDRTYPE_LPDDR3:
> writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR23, DDRMON_CTRL_DDR_TYPE_MASK),
> dfi_regs + DDRMON_CTRL);
> - else if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR4)
> + break;
> + case ROCKCHIP_DDRTYPE_LPDDR4:
> writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR4, DDRMON_CTRL_DDR_TYPE_MASK),
> dfi_regs + DDRMON_CTRL);
> + break;
> + default:
> + break;
> + }
>
> /* enable count, use software mode */
> writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_SOFTWARE_EN, DDRMON_CTRL_SOFTWARE_EN),
Acked-by: Chanwoo Choi <[email protected]>
--
Best Regards,
Samsung Electronics
Chanwoo Choi
Hi Sascha,
Could you plesae fix the following kernel build report?
On 23. 10. 18. 16:58, kernel test robot wrote:
> Hi Sascha,
>
> kernel test robot noticed the following build warnings:
>
> [auto build test WARNING on linus/master]
> [also build test WARNING on v6.6-rc6]
> [cannot apply to next-20231018]
> [If your patch is applied to the wrong git tree, kindly drop us a note.
> And when submitting patch, we suggest to use '--base' as documented in
> https://git-scm.com/docs/git-format-patch#_base_tree_information]
>
> url: https://github.com/intel-lab-lkp/linux/commits/Sascha-Hauer/PM-devfreq-rockchip-dfi-Make-pmu-regmap-mandatory/20231018-142228
> base: linus/master
> patch link: https://lore.kernel.org/r/20231018061714.3553817-17-s.hauer%40pengutronix.de
> patch subject: [PATCH v8 16/26] PM / devfreq: rockchip-dfi: Add perf support
> config: m68k-allyesconfig (https://download.01.org/0day-ci/archive/20231018/[email protected]/config)
> compiler: m68k-linux-gcc (GCC) 13.2.0
> reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20231018/[email protected]/reproduce)
>
> If you fix the issue in a separate patch/commit (i.e. not just a new version of
> the same patch/commit), kindly add following tags
> | Reported-by: kernel test robot <[email protected]>
> | Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/
>
> All warnings (new ones prefixed by >>):
>
>>> drivers/devfreq/event/rockchip-dfi.c:203:13: warning: 'rockchip_ddr_perf_counters_add' defined but not used [-Wunused-function]
> 203 | static void rockchip_ddr_perf_counters_add(struct rockchip_dfi *dfi,
> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> --
>>> drivers/devfreq/event/rockchip-dfi.c:79: warning: Function parameter or member 'write_access' not described in 'dmc_count_channel'
>
>
> vim +/rockchip_ddr_perf_counters_add +203 drivers/devfreq/event/rockchip-dfi.c
>
> 66
> 67 /**
> 68 * struct dmc_count_channel - structure to hold counter values from the DDR controller
> 69 * @access: Number of read and write accesses
> 70 * @clock_cycles: DDR clock cycles
> 71 * @read_access: number of read accesses
> 72 * @write_acccess: number of write accesses
> 73 */
> 74 struct dmc_count_channel {
> 75 u64 access;
> 76 u64 clock_cycles;
> 77 u64 read_access;
> 78 u64 write_access;
> > 79 };
> 80
> 81 struct dmc_count {
> 82 struct dmc_count_channel c[DMC_MAX_CHANNELS];
> 83 };
> 84
> 85 /*
> 86 * The dfi controller can monitor DDR load. It has an upper and lower threshold
> 87 * for the operating points. Whenever the usage leaves these bounds an event is
> 88 * generated to indicate the DDR frequency should be changed.
> 89 */
> 90 struct rockchip_dfi {
> 91 struct devfreq_event_dev *edev;
> 92 struct devfreq_event_desc desc;
> 93 struct dmc_count last_event_count;
> 94
> 95 struct dmc_count last_perf_count;
> 96 struct dmc_count total_count;
> 97 seqlock_t count_seqlock; /* protects last_perf_count and total_count */
> 98
> 99 struct device *dev;
> 100 void __iomem *regs;
> 101 struct regmap *regmap_pmu;
> 102 struct clk *clk;
> 103 int usecount;
> 104 struct mutex mutex;
> 105 u32 ddr_type;
> 106 unsigned int channel_mask;
> 107 unsigned int max_channels;
> 108 enum cpuhp_state cpuhp_state;
> 109 struct hlist_node node;
> 110 struct pmu pmu;
> 111 struct hrtimer timer;
> 112 unsigned int cpu;
> 113 int active_events;
> 114 int burst_len;
> 115 int buswidth[DMC_MAX_CHANNELS];
> 116 };
> 117
> 118 static int rockchip_dfi_enable(struct rockchip_dfi *dfi)
> 119 {
> 120 void __iomem *dfi_regs = dfi->regs;
> 121 int ret = 0;
> 122
> 123 mutex_lock(&dfi->mutex);
> 124
> 125 dfi->usecount++;
> 126 if (dfi->usecount > 1)
> 127 goto out;
> 128
> 129 ret = clk_prepare_enable(dfi->clk);
> 130 if (ret) {
> 131 dev_err(&dfi->edev->dev, "failed to enable dfi clk: %d\n", ret);
> 132 goto out;
> 133 }
> 134
> 135 /* clear DDRMON_CTRL setting */
> 136 writel_relaxed(HIWORD_UPDATE(0, DDRMON_CTRL_TIMER_CNT_EN | DDRMON_CTRL_SOFTWARE_EN |
> 137 DDRMON_CTRL_HARDWARE_EN), dfi_regs + DDRMON_CTRL);
> 138
> 139 /* set ddr type to dfi */
> 140 switch (dfi->ddr_type) {
> 141 case ROCKCHIP_DDRTYPE_LPDDR2:
> 142 case ROCKCHIP_DDRTYPE_LPDDR3:
> 143 writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR23, DDRMON_CTRL_DDR_TYPE_MASK),
> 144 dfi_regs + DDRMON_CTRL);
> 145 break;
> 146 case ROCKCHIP_DDRTYPE_LPDDR4:
> 147 case ROCKCHIP_DDRTYPE_LPDDR4X:
> 148 writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR4, DDRMON_CTRL_DDR_TYPE_MASK),
> 149 dfi_regs + DDRMON_CTRL);
> 150 break;
> 151 default:
> 152 break;
> 153 }
> 154
> 155 /* enable count, use software mode */
> 156 writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_SOFTWARE_EN, DDRMON_CTRL_SOFTWARE_EN),
> 157 dfi_regs + DDRMON_CTRL);
> 158 out:
> 159 mutex_unlock(&dfi->mutex);
> 160
> 161 return ret;
> 162 }
> 163
> 164 static void rockchip_dfi_disable(struct rockchip_dfi *dfi)
> 165 {
> 166 void __iomem *dfi_regs = dfi->regs;
> 167
> 168 mutex_lock(&dfi->mutex);
> 169
> 170 dfi->usecount--;
> 171
> 172 WARN_ON_ONCE(dfi->usecount < 0);
> 173
> 174 if (dfi->usecount > 0)
> 175 goto out;
> 176
> 177 writel_relaxed(HIWORD_UPDATE(0, DDRMON_CTRL_SOFTWARE_EN),
> 178 dfi_regs + DDRMON_CTRL);
> 179 clk_disable_unprepare(dfi->clk);
> 180 out:
> 181 mutex_unlock(&dfi->mutex);
> 182 }
> 183
> 184 static void rockchip_dfi_read_counters(struct rockchip_dfi *dfi, struct dmc_count *res)
> 185 {
> 186 u32 i;
> 187 void __iomem *dfi_regs = dfi->regs;
> 188
> 189 for (i = 0; i < dfi->max_channels; i++) {
> 190 if (!(dfi->channel_mask & BIT(i)))
> 191 continue;
> 192 res->c[i].read_access = readl_relaxed(dfi_regs +
> 193 DDRMON_CH0_RD_NUM + i * 20);
> 194 res->c[i].write_access = readl_relaxed(dfi_regs +
> 195 DDRMON_CH0_WR_NUM + i * 20);
> 196 res->c[i].access = readl_relaxed(dfi_regs +
> 197 DDRMON_CH0_DFI_ACCESS_NUM + i * 20);
> 198 res->c[i].clock_cycles = readl_relaxed(dfi_regs +
> 199 DDRMON_CH0_COUNT_NUM + i * 20);
> 200 }
> 201 }
> 202
> > 203 static void rockchip_ddr_perf_counters_add(struct rockchip_dfi *dfi,
> 204 const struct dmc_count *now,
> 205 struct dmc_count *res)
> 206 {
> 207 const struct dmc_count *last = &dfi->last_perf_count;
> 208 int i;
> 209
> 210 for (i = 0; i < dfi->max_channels; i++) {
> 211 res->c[i].read_access = dfi->total_count.c[i].read_access +
> 212 (u32)(now->c[i].read_access - last->c[i].read_access);
> 213 res->c[i].write_access = dfi->total_count.c[i].write_access +
> 214 (u32)(now->c[i].write_access - last->c[i].write_access);
> 215 res->c[i].access = dfi->total_count.c[i].access +
> 216 (u32)(now->c[i].access - last->c[i].access);
> 217 res->c[i].clock_cycles = dfi->total_count.c[i].clock_cycles +
> 218 (u32)(now->c[i].clock_cycles - last->c[i].clock_cycles);
> 219 }
> 220 }
> 221
>
--
Best Regards,
Samsung Electronics
Chanwoo Choi
On 23. 10. 18. 15:17, Sascha Hauer wrote:
> Add support for the RK3588 to the driver. The RK3588 has four DDR
> channels with a register stride of 0x4000 between the channel
> registers, also it has a DDRMON_CTRL register per channel.
>
> Reviewed-by: Jonathan Cameron <[email protected]>
> Reviewed-by: Sebastian Reichel <[email protected]>
> Signed-off-by: Sascha Hauer <[email protected]>
> ---
> drivers/devfreq/event/rockchip-dfi.c | 36 +++++++++++++++++++++++++++-
> include/soc/rockchip/rk3588_grf.h | 18 ++++++++++++++
> 2 files changed, 53 insertions(+), 1 deletion(-)
> create mode 100644 include/soc/rockchip/rk3588_grf.h
>
> diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c
> index bf38829a2a4af..794f36e7eebd1 100644
> --- a/drivers/devfreq/event/rockchip-dfi.c
> +++ b/drivers/devfreq/event/rockchip-dfi.c
> @@ -26,8 +26,9 @@
> #include <soc/rockchip/rockchip_grf.h>
> #include <soc/rockchip/rk3399_grf.h>
> #include <soc/rockchip/rk3568_grf.h>
> +#include <soc/rockchip/rk3588_grf.h>
>
> -#define DMC_MAX_CHANNELS 2
> +#define DMC_MAX_CHANNELS 4
>
> #define HIWORD_UPDATE(val, mask) ((val) | (mask) << 16)
>
> @@ -723,9 +724,42 @@ static int rk3568_dfi_init(struct rockchip_dfi *dfi)
> return 0;
> };
>
> +static int rk3588_dfi_init(struct rockchip_dfi *dfi)
> +{
> + struct regmap *regmap_pmu = dfi->regmap_pmu;
> + u32 reg2, reg3, reg4;
> +
> + regmap_read(regmap_pmu, RK3588_PMUGRF_OS_REG2, ®2);
> + regmap_read(regmap_pmu, RK3588_PMUGRF_OS_REG3, ®3);
> + regmap_read(regmap_pmu, RK3588_PMUGRF_OS_REG4, ®4);
> +
> + /* lower 3 bits of the DDR type */
> + dfi->ddr_type = FIELD_GET(RK3588_PMUGRF_OS_REG2_DRAMTYPE_INFO, reg2);
> +
> + /*
> + * For version three and higher the upper two bits of the DDR type are
> + * in RK3588_PMUGRF_OS_REG3
> + */
> + if (FIELD_GET(RK3588_PMUGRF_OS_REG3_SYSREG_VERSION, reg3) >= 0x3)
> + dfi->ddr_type |= FIELD_GET(RK3588_PMUGRF_OS_REG3_DRAMTYPE_INFO_V3, reg3) << 3;
> +
> + dfi->buswidth[0] = FIELD_GET(RK3588_PMUGRF_OS_REG2_BW_CH0, reg2) == 0 ? 4 : 2;
> + dfi->buswidth[1] = FIELD_GET(RK3588_PMUGRF_OS_REG2_BW_CH1, reg2) == 0 ? 4 : 2;
> + dfi->buswidth[2] = FIELD_GET(RK3568_PMUGRF_OS_REG2_BW_CH0, reg4) == 0 ? 4 : 2;
> + dfi->buswidth[3] = FIELD_GET(RK3588_PMUGRF_OS_REG2_BW_CH1, reg4) == 0 ? 4 : 2;
> + dfi->channel_mask = FIELD_GET(RK3588_PMUGRF_OS_REG2_CH_INFO, reg2) |
> + FIELD_GET(RK3588_PMUGRF_OS_REG2_CH_INFO, reg4) << 2;
> + dfi->max_channels = 4;
> +
> + dfi->ddrmon_stride = 0x4000;
> +
> + return 0;
> +};
> +
> static const struct of_device_id rockchip_dfi_id_match[] = {
> { .compatible = "rockchip,rk3399-dfi", .data = rk3399_dfi_init },
> { .compatible = "rockchip,rk3568-dfi", .data = rk3568_dfi_init },
> + { .compatible = "rockchip,rk3588-dfi", .data = rk3588_dfi_init },
> { },
> };
>
> diff --git a/include/soc/rockchip/rk3588_grf.h b/include/soc/rockchip/rk3588_grf.h
> new file mode 100644
> index 0000000000000..630b35a550640
> --- /dev/null
> +++ b/include/soc/rockchip/rk3588_grf.h
> @@ -0,0 +1,18 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +#ifndef __SOC_RK3588_GRF_H
> +#define __SOC_RK3588_GRF_H
> +
> +#define RK3588_PMUGRF_OS_REG2 0x208
> +#define RK3588_PMUGRF_OS_REG2_DRAMTYPE_INFO GENMASK(15, 13)
> +#define RK3588_PMUGRF_OS_REG2_BW_CH0 GENMASK(3, 2)
> +#define RK3588_PMUGRF_OS_REG2_BW_CH1 GENMASK(19, 18)
> +#define RK3588_PMUGRF_OS_REG2_CH_INFO GENMASK(29, 28)
> +
> +#define RK3588_PMUGRF_OS_REG3 0x20c
> +#define RK3588_PMUGRF_OS_REG3_DRAMTYPE_INFO_V3 GENMASK(13, 12)
> +#define RK3588_PMUGRF_OS_REG3_SYSREG_VERSION GENMASK(31, 28)
> +
> +#define RK3588_PMUGRF_OS_REG4 0x210
> +#define RK3588_PMUGRF_OS_REG5 0x214
> +
> +#endif /* __SOC_RK3588_GRF_H */
Acked-by: Chanwoo Choi <[email protected]>
--
Best Regards,
Samsung Electronics
Chanwoo Choi
Hi Sascha and Heiko,
I finished the review from 01 ~ 22 patches.
- 01-05 patches are merged.
- 06-22 patches with acked tags.
Some patches modifies the 'include/soc/rockchip/*' files.
After getting the ack from rockchip maintainer (Heiko Stuebner),
I'll merge patches from 06 ~ 22 patches to devfreq.git.
Best Regards,
Chanwoo Choi
On 23. 10. 18. 15:16, Sascha Hauer wrote:
> This series integrates the recent review feedback from Chanwoo Choi to
> v7.
>
> Chanwoo, I am sending the full patchset again for people to try this
> series. You said that you applied 1-5 already, so please start picking
> from 6/26.
>
> Sascha
>
> Sascha Hauer (26):
> PM / devfreq: rockchip-dfi: Make pmu regmap mandatory
> PM / devfreq: rockchip-dfi: Embed desc into private data struct
> PM / devfreq: rockchip-dfi: use consistent name for private data
> struct
> PM / devfreq: rockchip-dfi: Add SoC specific init function
> PM / devfreq: rockchip-dfi: dfi store raw values in counter struct
> PM / devfreq: rockchip-dfi: Use free running counter
> PM / devfreq: rockchip-dfi: introduce channel mask
> PM / devfreq: rk3399_dmc,dfi: generalize DDRTYPE defines
> PM / devfreq: rockchip-dfi: Clean up DDR type register defines
> PM / devfreq: rockchip-dfi: Add RK3568 support
> PM / devfreq: rockchip-dfi: Handle LPDDR2 correctly
> PM / devfreq: rockchip-dfi: Handle LPDDR4X
> PM / devfreq: rockchip-dfi: Pass private data struct to internal
> functions
> PM / devfreq: rockchip-dfi: Prepare for multiple users
> PM / devfreq: rockchip-dfi: give variable a better name
> PM / devfreq: rockchip-dfi: Add perf support
> PM / devfreq: rockchip-dfi: make register stride SoC specific
> PM / devfreq: rockchip-dfi: account for multiple DDRMON_CTRL registers
> PM / devfreq: rockchip-dfi: add support for RK3588
> dt-bindings: devfreq: event: convert Rockchip DFI binding to yaml
> dt-bindings: devfreq: event: rockchip,dfi: Add rk3568 support
> dt-bindings: devfreq: event: rockchip,dfi: Add rk3588 support
> dt-bindings: soc: rockchip: grf: add rockchip,rk3588-pmugrf
> arm64: dts: rockchip: rk3399: Enable DFI
> arm64: dts: rockchip: rk356x: Add DFI
> arm64: dts: rockchip: rk3588s: Add DFI
>
> .../bindings/devfreq/event/rockchip,dfi.yaml | 74 ++
> .../bindings/devfreq/event/rockchip-dfi.txt | 18 -
> .../rockchip,rk3399-dmc.yaml | 2 +-
> .../devicetree/bindings/soc/rockchip/grf.yaml | 1 +
> arch/arm64/boot/dts/rockchip/rk3399.dtsi | 1 -
> arch/arm64/boot/dts/rockchip/rk356x.dtsi | 7 +
> arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 16 +
> drivers/devfreq/event/rockchip-dfi.c | 814 +++++++++++++++---
> drivers/devfreq/rk3399_dmc.c | 10 +-
> include/soc/rockchip/rk3399_grf.h | 9 +-
> include/soc/rockchip/rk3568_grf.h | 13 +
> include/soc/rockchip/rk3588_grf.h | 18 +
> include/soc/rockchip/rockchip_grf.h | 18 +
> 13 files changed, 863 insertions(+), 138 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml
> delete mode 100644 Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt
> create mode 100644 include/soc/rockchip/rk3568_grf.h
> create mode 100644 include/soc/rockchip/rk3588_grf.h
> create mode 100644 include/soc/rockchip/rockchip_grf.h
>
Am Mittwoch, 18. Oktober 2023, 08:16:56 CEST schrieb Sascha Hauer:
> The DDRTYPE defines are named to be RK3399 specific, but they can be
> used for other Rockchip SoCs as well, so replace the RK3399_PMUGRF_
> prefix with ROCKCHIP_. They are defined in a SoC specific header
> file, so when generalizing the prefix also move the new defines to
> a SoC agnostic header file. While at it use GENMASK to define the
> DDRTYPE bitfield and give it a name including the full register name.
>
> Reviewed-by: Sebastian Reichel <[email protected]>
> Acked-by: Chanwoo Choi <[email protected]>
> Signed-off-by: Sascha Hauer <[email protected]>
Acked-by: Heiko Stuebner <[email protected]>
Am Mittwoch, 18. Oktober 2023, 08:16:58 CEST schrieb Sascha Hauer:
> This adds RK3568 support to the DFI driver. Only iniitialization
> differs from the currently supported RK3399.
>
> Signed-off-by: Sascha Hauer <[email protected]>
> ---
>
> Notes:
> Changes since v7:
> - Add comment to explain << 3
>
> drivers/devfreq/event/rockchip-dfi.c | 27 +++++++++++++++++++++++++++
> include/soc/rockchip/rk3568_grf.h | 12 ++++++++++++
> 2 files changed, 39 insertions(+)
> create mode 100644 include/soc/rockchip/rk3568_grf.h
Acked-by: Heiko Stuebner <[email protected]>
Am Mittwoch, 18. Oktober 2023, 08:17:04 CEST schrieb Sascha Hauer:
> The DFI is a unit which is suitable for measuring DDR utilization, but
> so far it could only be used as an event driver for the DDR frequency
> scaling driver. This adds perf support to the DFI driver.
>
> Usage with the 'perf' tool can look like:
>
> perf stat -a -e rockchip_ddr/cycles/,\
> rockchip_ddr/read-bytes/,\
> rockchip_ddr/write-bytes/,\
> rockchip_ddr/bytes/ sleep 1
>
> Performance counter stats for 'system wide':
>
> 1582524826 rockchip_ddr/cycles/
> 1802.25 MB rockchip_ddr/read-bytes/
> 1793.72 MB rockchip_ddr/write-bytes/
> 3595.90 MB rockchip_ddr/bytes/
>
> 1.014369709 seconds time elapsed
>
> perf support has been tested on a RK3568 and a RK3399, the latter with
> dual channel DDR.
>
> Reviewed-by: Sebastian Reichel <[email protected]>
> Acked-by: Chanwoo Choi <[email protected]>
> Signed-off-by: Sascha Hauer <[email protected]>
Acked-by: Heiko Stuebner <[email protected]>
Am Mittwoch, 18. Oktober 2023, 08:17:07 CEST schrieb Sascha Hauer:
> Add support for the RK3588 to the driver. The RK3588 has four DDR
> channels with a register stride of 0x4000 between the channel
> registers, also it has a DDRMON_CTRL register per channel.
>
> Reviewed-by: Jonathan Cameron <[email protected]>
> Reviewed-by: Sebastian Reichel <[email protected]>
> Signed-off-by: Sascha Hauer <[email protected]>
> ---
> drivers/devfreq/event/rockchip-dfi.c | 36 +++++++++++++++++++++++++++-
> include/soc/rockchip/rk3588_grf.h | 18 ++++++++++++++
> 2 files changed, 53 insertions(+), 1 deletion(-)
> create mode 100644 include/soc/rockchip/rk3588_grf.h
Acked-by: Heiko Stuebner <[email protected]>
Hi,
Am Mittwoch, 18. Oktober 2023, 17:21:07 CEST schrieb Chanwoo Choi:
> Hi Sascha and Heiko,
>
> I finished the review from 01 ~ 22 patches.
> - 01-05 patches are merged.
> - 06-22 patches with acked tags.
>
>
> Some patches modifies the 'include/soc/rockchip/*' files.
> After getting the ack from rockchip maintainer (Heiko Stuebner),
> I'll merge patches from 06 ~ 22 patches to devfreq.git.
I do hope I caught all patches that needed Acks from that range.
The changes to the soc includes all looked fine, so if I forgot to Ack
a patch from that 1-22 range, here is a blanked
Acked-by: Heiko Stuebner <[email protected]>
for those.
Thanks for reviewing that big series
Heiko
The DFI is a unit which is suitable for measuring DDR utilization, but
so far it could only be used as an event driver for the DDR frequency
scaling driver. This adds perf support to the DFI driver.
Usage with the 'perf' tool can look like:
perf stat -a -e rockchip_ddr/cycles/,\
rockchip_ddr/read-bytes/,\
rockchip_ddr/write-bytes/,\
rockchip_ddr/bytes/ sleep 1
Performance counter stats for 'system wide':
1582524826 rockchip_ddr/cycles/
1802.25 MB rockchip_ddr/read-bytes/
1793.72 MB rockchip_ddr/write-bytes/
3595.90 MB rockchip_ddr/bytes/
1.014369709 seconds time elapsed
perf support has been tested on a RK3568 and a RK3399, the latter with
dual channel DDR.
Reviewed-by: Sebastian Reichel <[email protected]>
Acked-by: Chanwoo Choi <[email protected]>
Signed-off-by: Sascha Hauer <[email protected]>
---
Notes:
Changes since v8:
- Move rockchip_ddr_perf_counters_add() inside #ifdef CONFIG_PERF_EVENTS
to avoid unused function warning with CONFIG_PERF_EVENTS disabled
Changes since v7:
- rename variable 'c' to 'count'
Changes since v5:
- Add missing initialization of &dfi->last_perf_count
Changes since v4:
- use __stringify to ensure event type definitions and event numbers in sysfs are consistent
- only use 64bit values in structs holding counters
- support monitoring individual DDR channels
- fix return value in rockchip_ddr_perf_event_init(): -EOPNOTSUPP -> -EINVAL
- check for invalid event->attr.config values
- start hrtimer to trigger in one second, not immediately
- use devm_add_action_or_reset()
- add suppress_bind_attrs
- enable DDRMON during probe when perf is enabled
- use a seqlock to protect perf reading the counters from the hrtimer callback modifying them
drivers/devfreq/event/rockchip-dfi.c | 440 ++++++++++++++++++++++++++-
include/soc/rockchip/rk3399_grf.h | 2 +
include/soc/rockchip/rk3568_grf.h | 1 +
3 files changed, 438 insertions(+), 5 deletions(-)
diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c
index 3d5c6d737ccd9..a7d7b61518fec 100644
--- a/drivers/devfreq/event/rockchip-dfi.c
+++ b/drivers/devfreq/event/rockchip-dfi.c
@@ -16,10 +16,12 @@
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/list.h>
+#include <linux/seqlock.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/bitfield.h>
#include <linux/bits.h>
+#include <linux/perf_event.h>
#include <soc/rockchip/rockchip_grf.h>
#include <soc/rockchip/rk3399_grf.h>
@@ -41,19 +43,39 @@
DDRMON_CTRL_LPDDR4 | \
DDRMON_CTRL_LPDDR23)
+#define DDRMON_CH0_WR_NUM 0x20
+#define DDRMON_CH0_RD_NUM 0x24
#define DDRMON_CH0_COUNT_NUM 0x28
#define DDRMON_CH0_DFI_ACCESS_NUM 0x2c
#define DDRMON_CH1_COUNT_NUM 0x3c
#define DDRMON_CH1_DFI_ACCESS_NUM 0x40
+#define PERF_EVENT_CYCLES 0x0
+#define PERF_EVENT_READ_BYTES 0x1
+#define PERF_EVENT_WRITE_BYTES 0x2
+#define PERF_EVENT_READ_BYTES0 0x3
+#define PERF_EVENT_WRITE_BYTES0 0x4
+#define PERF_EVENT_READ_BYTES1 0x5
+#define PERF_EVENT_WRITE_BYTES1 0x6
+#define PERF_EVENT_READ_BYTES2 0x7
+#define PERF_EVENT_WRITE_BYTES2 0x8
+#define PERF_EVENT_READ_BYTES3 0x9
+#define PERF_EVENT_WRITE_BYTES3 0xa
+#define PERF_EVENT_BYTES 0xb
+#define PERF_ACCESS_TYPE_MAX 0xc
+
/**
* struct dmc_count_channel - structure to hold counter values from the DDR controller
* @access: Number of read and write accesses
* @clock_cycles: DDR clock cycles
+ * @read_access: number of read accesses
+ * @write_acccess: number of write accesses
*/
struct dmc_count_channel {
- u32 access;
- u32 clock_cycles;
+ u64 access;
+ u64 clock_cycles;
+ u64 read_access;
+ u64 write_access;
};
struct dmc_count {
@@ -69,6 +91,11 @@ struct rockchip_dfi {
struct devfreq_event_dev *edev;
struct devfreq_event_desc desc;
struct dmc_count last_event_count;
+
+ struct dmc_count last_perf_count;
+ struct dmc_count total_count;
+ seqlock_t count_seqlock; /* protects last_perf_count and total_count */
+
struct device *dev;
void __iomem *regs;
struct regmap *regmap_pmu;
@@ -78,6 +105,14 @@ struct rockchip_dfi {
u32 ddr_type;
unsigned int channel_mask;
unsigned int max_channels;
+ enum cpuhp_state cpuhp_state;
+ struct hlist_node node;
+ struct pmu pmu;
+ struct hrtimer timer;
+ unsigned int cpu;
+ int active_events;
+ int burst_len;
+ int buswidth[DMC_MAX_CHANNELS];
};
static int rockchip_dfi_enable(struct rockchip_dfi *dfi)
@@ -146,7 +181,7 @@ static void rockchip_dfi_disable(struct rockchip_dfi *dfi)
mutex_unlock(&dfi->mutex);
}
-static void rockchip_dfi_read_counters(struct rockchip_dfi *dfi, struct dmc_count *count)
+static void rockchip_dfi_read_counters(struct rockchip_dfi *dfi, struct dmc_count *res)
{
u32 i;
void __iomem *dfi_regs = dfi->regs;
@@ -154,9 +189,13 @@ static void rockchip_dfi_read_counters(struct rockchip_dfi *dfi, struct dmc_coun
for (i = 0; i < dfi->max_channels; i++) {
if (!(dfi->channel_mask & BIT(i)))
continue;
- count->c[i].access = readl_relaxed(dfi_regs +
+ res->c[i].read_access = readl_relaxed(dfi_regs +
+ DDRMON_CH0_RD_NUM + i * 20);
+ res->c[i].write_access = readl_relaxed(dfi_regs +
+ DDRMON_CH0_WR_NUM + i * 20);
+ res->c[i].access = readl_relaxed(dfi_regs +
DDRMON_CH0_DFI_ACCESS_NUM + i * 20);
- count->c[i].clock_cycles = readl_relaxed(dfi_regs +
+ res->c[i].clock_cycles = readl_relaxed(dfi_regs +
DDRMON_CH0_COUNT_NUM + i * 20);
}
}
@@ -224,6 +263,387 @@ static const struct devfreq_event_ops rockchip_dfi_ops = {
.set_event = rockchip_dfi_set_event,
};
+#ifdef CONFIG_PERF_EVENTS
+
+static void rockchip_ddr_perf_counters_add(struct rockchip_dfi *dfi,
+ const struct dmc_count *now,
+ struct dmc_count *res)
+{
+ const struct dmc_count *last = &dfi->last_perf_count;
+ int i;
+
+ for (i = 0; i < dfi->max_channels; i++) {
+ res->c[i].read_access = dfi->total_count.c[i].read_access +
+ (u32)(now->c[i].read_access - last->c[i].read_access);
+ res->c[i].write_access = dfi->total_count.c[i].write_access +
+ (u32)(now->c[i].write_access - last->c[i].write_access);
+ res->c[i].access = dfi->total_count.c[i].access +
+ (u32)(now->c[i].access - last->c[i].access);
+ res->c[i].clock_cycles = dfi->total_count.c[i].clock_cycles +
+ (u32)(now->c[i].clock_cycles - last->c[i].clock_cycles);
+ }
+}
+
+static ssize_t ddr_perf_cpumask_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct pmu *pmu = dev_get_drvdata(dev);
+ struct rockchip_dfi *dfi = container_of(pmu, struct rockchip_dfi, pmu);
+
+ return cpumap_print_to_pagebuf(true, buf, cpumask_of(dfi->cpu));
+}
+
+static struct device_attribute ddr_perf_cpumask_attr =
+ __ATTR(cpumask, 0444, ddr_perf_cpumask_show, NULL);
+
+static struct attribute *ddr_perf_cpumask_attrs[] = {
+ &ddr_perf_cpumask_attr.attr,
+ NULL,
+};
+
+static const struct attribute_group ddr_perf_cpumask_attr_group = {
+ .attrs = ddr_perf_cpumask_attrs,
+};
+
+PMU_EVENT_ATTR_STRING(cycles, ddr_pmu_cycles, "event="__stringify(PERF_EVENT_CYCLES))
+
+#define DFI_PMU_EVENT_ATTR(_name, _var, _str) \
+ PMU_EVENT_ATTR_STRING(_name, _var, _str); \
+ PMU_EVENT_ATTR_STRING(_name.unit, _var##_unit, "MB"); \
+ PMU_EVENT_ATTR_STRING(_name.scale, _var##_scale, "9.536743164e-07")
+
+DFI_PMU_EVENT_ATTR(read-bytes0, ddr_pmu_read_bytes0, "event="__stringify(PERF_EVENT_READ_BYTES0));
+DFI_PMU_EVENT_ATTR(write-bytes0, ddr_pmu_write_bytes0, "event="__stringify(PERF_EVENT_WRITE_BYTES0));
+
+DFI_PMU_EVENT_ATTR(read-bytes1, ddr_pmu_read_bytes1, "event="__stringify(PERF_EVENT_READ_BYTES1));
+DFI_PMU_EVENT_ATTR(write-bytes1, ddr_pmu_write_bytes1, "event="__stringify(PERF_EVENT_WRITE_BYTES1));
+
+DFI_PMU_EVENT_ATTR(read-bytes2, ddr_pmu_read_bytes2, "event="__stringify(PERF_EVENT_READ_BYTES2));
+DFI_PMU_EVENT_ATTR(write-bytes2, ddr_pmu_write_bytes2, "event="__stringify(PERF_EVENT_WRITE_BYTES2));
+
+DFI_PMU_EVENT_ATTR(read-bytes3, ddr_pmu_read_bytes3, "event="__stringify(PERF_EVENT_READ_BYTES3));
+DFI_PMU_EVENT_ATTR(write-bytes3, ddr_pmu_write_bytes3, "event="__stringify(PERF_EVENT_WRITE_BYTES3));
+
+DFI_PMU_EVENT_ATTR(read-bytes, ddr_pmu_read_bytes, "event="__stringify(PERF_EVENT_READ_BYTES));
+DFI_PMU_EVENT_ATTR(write-bytes, ddr_pmu_write_bytes, "event="__stringify(PERF_EVENT_WRITE_BYTES));
+
+DFI_PMU_EVENT_ATTR(bytes, ddr_pmu_bytes, "event="__stringify(PERF_EVENT_BYTES));
+
+#define DFI_ATTR_MB(_name) \
+ &_name.attr.attr, \
+ &_name##_unit.attr.attr, \
+ &_name##_scale.attr.attr
+
+static struct attribute *ddr_perf_events_attrs[] = {
+ &ddr_pmu_cycles.attr.attr,
+ DFI_ATTR_MB(ddr_pmu_read_bytes),
+ DFI_ATTR_MB(ddr_pmu_write_bytes),
+ DFI_ATTR_MB(ddr_pmu_read_bytes0),
+ DFI_ATTR_MB(ddr_pmu_write_bytes0),
+ DFI_ATTR_MB(ddr_pmu_read_bytes1),
+ DFI_ATTR_MB(ddr_pmu_write_bytes1),
+ DFI_ATTR_MB(ddr_pmu_read_bytes2),
+ DFI_ATTR_MB(ddr_pmu_write_bytes2),
+ DFI_ATTR_MB(ddr_pmu_read_bytes3),
+ DFI_ATTR_MB(ddr_pmu_write_bytes3),
+ DFI_ATTR_MB(ddr_pmu_bytes),
+ NULL,
+};
+
+static const struct attribute_group ddr_perf_events_attr_group = {
+ .name = "events",
+ .attrs = ddr_perf_events_attrs,
+};
+
+PMU_FORMAT_ATTR(event, "config:0-7");
+
+static struct attribute *ddr_perf_format_attrs[] = {
+ &format_attr_event.attr,
+ NULL,
+};
+
+static const struct attribute_group ddr_perf_format_attr_group = {
+ .name = "format",
+ .attrs = ddr_perf_format_attrs,
+};
+
+static const struct attribute_group *attr_groups[] = {
+ &ddr_perf_events_attr_group,
+ &ddr_perf_cpumask_attr_group,
+ &ddr_perf_format_attr_group,
+ NULL,
+};
+
+static int rockchip_ddr_perf_event_init(struct perf_event *event)
+{
+ struct rockchip_dfi *dfi = container_of(event->pmu, struct rockchip_dfi, pmu);
+
+ if (event->attr.type != event->pmu->type)
+ return -ENOENT;
+
+ if (event->attach_state & PERF_ATTACH_TASK)
+ return -EINVAL;
+
+ if (event->cpu < 0) {
+ dev_warn(dfi->dev, "Can't provide per-task data!\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static u64 rockchip_ddr_perf_event_get_count(struct perf_event *event)
+{
+ struct rockchip_dfi *dfi = container_of(event->pmu, struct rockchip_dfi, pmu);
+ int blen = dfi->burst_len;
+ struct dmc_count total, now;
+ unsigned int seq;
+ u64 count = 0;
+ int i;
+
+ rockchip_dfi_read_counters(dfi, &now);
+
+ do {
+ seq = read_seqbegin(&dfi->count_seqlock);
+ rockchip_ddr_perf_counters_add(dfi, &now, &total);
+ } while (read_seqretry(&dfi->count_seqlock, seq));
+
+ switch (event->attr.config) {
+ case PERF_EVENT_CYCLES:
+ count = total.c[0].clock_cycles;
+ break;
+ case PERF_EVENT_READ_BYTES:
+ for (i = 0; i < dfi->max_channels; i++)
+ count += total.c[i].read_access * blen * dfi->buswidth[i];
+ break;
+ case PERF_EVENT_WRITE_BYTES:
+ for (i = 0; i < dfi->max_channels; i++)
+ count += total.c[i].write_access * blen * dfi->buswidth[i];
+ break;
+ case PERF_EVENT_READ_BYTES0:
+ count = total.c[0].read_access * blen * dfi->buswidth[0];
+ break;
+ case PERF_EVENT_WRITE_BYTES0:
+ count = total.c[0].write_access * blen * dfi->buswidth[0];
+ break;
+ case PERF_EVENT_READ_BYTES1:
+ count = total.c[1].read_access * blen * dfi->buswidth[1];
+ break;
+ case PERF_EVENT_WRITE_BYTES1:
+ count = total.c[1].write_access * blen * dfi->buswidth[1];
+ break;
+ case PERF_EVENT_READ_BYTES2:
+ count = total.c[2].read_access * blen * dfi->buswidth[2];
+ break;
+ case PERF_EVENT_WRITE_BYTES2:
+ count = total.c[2].write_access * blen * dfi->buswidth[2];
+ break;
+ case PERF_EVENT_READ_BYTES3:
+ count = total.c[3].read_access * blen * dfi->buswidth[3];
+ break;
+ case PERF_EVENT_WRITE_BYTES3:
+ count = total.c[3].write_access * blen * dfi->buswidth[3];
+ break;
+ case PERF_EVENT_BYTES:
+ for (i = 0; i < dfi->max_channels; i++)
+ count += total.c[i].access * blen * dfi->buswidth[i];
+ break;
+ }
+
+ return count;
+}
+
+static void rockchip_ddr_perf_event_update(struct perf_event *event)
+{
+ u64 now;
+ s64 prev;
+
+ if (event->attr.config >= PERF_ACCESS_TYPE_MAX)
+ return;
+
+ now = rockchip_ddr_perf_event_get_count(event);
+ prev = local64_xchg(&event->hw.prev_count, now);
+ local64_add(now - prev, &event->count);
+}
+
+static void rockchip_ddr_perf_event_start(struct perf_event *event, int flags)
+{
+ u64 now = rockchip_ddr_perf_event_get_count(event);
+
+ local64_set(&event->hw.prev_count, now);
+}
+
+static int rockchip_ddr_perf_event_add(struct perf_event *event, int flags)
+{
+ struct rockchip_dfi *dfi = container_of(event->pmu, struct rockchip_dfi, pmu);
+
+ dfi->active_events++;
+
+ if (dfi->active_events == 1) {
+ dfi->total_count = (struct dmc_count){};
+ rockchip_dfi_read_counters(dfi, &dfi->last_perf_count);
+ hrtimer_start(&dfi->timer, ns_to_ktime(NSEC_PER_SEC), HRTIMER_MODE_REL);
+ }
+
+ if (flags & PERF_EF_START)
+ rockchip_ddr_perf_event_start(event, flags);
+
+ return 0;
+}
+
+static void rockchip_ddr_perf_event_stop(struct perf_event *event, int flags)
+{
+ rockchip_ddr_perf_event_update(event);
+}
+
+static void rockchip_ddr_perf_event_del(struct perf_event *event, int flags)
+{
+ struct rockchip_dfi *dfi = container_of(event->pmu, struct rockchip_dfi, pmu);
+
+ rockchip_ddr_perf_event_stop(event, PERF_EF_UPDATE);
+
+ dfi->active_events--;
+
+ if (dfi->active_events == 0)
+ hrtimer_cancel(&dfi->timer);
+}
+
+static enum hrtimer_restart rockchip_dfi_timer(struct hrtimer *timer)
+{
+ struct rockchip_dfi *dfi = container_of(timer, struct rockchip_dfi, timer);
+ struct dmc_count now, total;
+
+ rockchip_dfi_read_counters(dfi, &now);
+
+ write_seqlock(&dfi->count_seqlock);
+
+ rockchip_ddr_perf_counters_add(dfi, &now, &total);
+ dfi->total_count = total;
+ dfi->last_perf_count = now;
+
+ write_sequnlock(&dfi->count_seqlock);
+
+ hrtimer_forward_now(&dfi->timer, ns_to_ktime(NSEC_PER_SEC));
+
+ return HRTIMER_RESTART;
+};
+
+static int ddr_perf_offline_cpu(unsigned int cpu, struct hlist_node *node)
+{
+ struct rockchip_dfi *dfi = hlist_entry_safe(node, struct rockchip_dfi, node);
+ int target;
+
+ if (cpu != dfi->cpu)
+ return 0;
+
+ target = cpumask_any_but(cpu_online_mask, cpu);
+ if (target >= nr_cpu_ids)
+ return 0;
+
+ perf_pmu_migrate_context(&dfi->pmu, cpu, target);
+ dfi->cpu = target;
+
+ return 0;
+}
+
+static void rockchip_ddr_cpuhp_remove_state(void *data)
+{
+ struct rockchip_dfi *dfi = data;
+
+ cpuhp_remove_multi_state(dfi->cpuhp_state);
+
+ rockchip_dfi_disable(dfi);
+}
+
+static void rockchip_ddr_cpuhp_remove_instance(void *data)
+{
+ struct rockchip_dfi *dfi = data;
+
+ cpuhp_state_remove_instance_nocalls(dfi->cpuhp_state, &dfi->node);
+}
+
+static void rockchip_ddr_perf_remove(void *data)
+{
+ struct rockchip_dfi *dfi = data;
+
+ perf_pmu_unregister(&dfi->pmu);
+}
+
+static int rockchip_ddr_perf_init(struct rockchip_dfi *dfi)
+{
+ struct pmu *pmu = &dfi->pmu;
+ int ret;
+
+ seqlock_init(&dfi->count_seqlock);
+
+ pmu->module = THIS_MODULE;
+ pmu->capabilities = PERF_PMU_CAP_NO_EXCLUDE;
+ pmu->task_ctx_nr = perf_invalid_context;
+ pmu->attr_groups = attr_groups;
+ pmu->event_init = rockchip_ddr_perf_event_init;
+ pmu->add = rockchip_ddr_perf_event_add;
+ pmu->del = rockchip_ddr_perf_event_del;
+ pmu->start = rockchip_ddr_perf_event_start;
+ pmu->stop = rockchip_ddr_perf_event_stop;
+ pmu->read = rockchip_ddr_perf_event_update;
+
+ dfi->cpu = raw_smp_processor_id();
+
+ ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
+ "rockchip_ddr_perf_pmu",
+ NULL,
+ ddr_perf_offline_cpu);
+
+ if (ret < 0) {
+ dev_err(dfi->dev, "cpuhp_setup_state_multi failed: %d\n", ret);
+ return ret;
+ }
+
+ dfi->cpuhp_state = ret;
+
+ rockchip_dfi_enable(dfi);
+
+ ret = devm_add_action_or_reset(dfi->dev, rockchip_ddr_cpuhp_remove_state, dfi);
+ if (ret)
+ return ret;
+
+ ret = cpuhp_state_add_instance_nocalls(dfi->cpuhp_state, &dfi->node);
+ if (ret) {
+ dev_err(dfi->dev, "Error %d registering hotplug\n", ret);
+ return ret;
+ }
+
+ ret = devm_add_action_or_reset(dfi->dev, rockchip_ddr_cpuhp_remove_instance, dfi);
+ if (ret)
+ return ret;
+
+ hrtimer_init(&dfi->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
+ dfi->timer.function = rockchip_dfi_timer;
+
+ switch (dfi->ddr_type) {
+ case ROCKCHIP_DDRTYPE_LPDDR2:
+ case ROCKCHIP_DDRTYPE_LPDDR3:
+ dfi->burst_len = 8;
+ break;
+ case ROCKCHIP_DDRTYPE_LPDDR4:
+ case ROCKCHIP_DDRTYPE_LPDDR4X:
+ dfi->burst_len = 16;
+ break;
+ }
+
+ ret = perf_pmu_register(pmu, "rockchip_ddr", -1);
+ if (ret)
+ return ret;
+
+ return devm_add_action_or_reset(dfi->dev, rockchip_ddr_perf_remove, dfi);
+}
+#else
+static int rockchip_ddr_perf_init(struct rockchip_dfi *dfi)
+{
+ return 0;
+}
+#endif
+
static int rk3399_dfi_init(struct rockchip_dfi *dfi)
{
struct regmap *regmap_pmu = dfi->regmap_pmu;
@@ -241,6 +661,9 @@ static int rk3399_dfi_init(struct rockchip_dfi *dfi)
dfi->channel_mask = GENMASK(1, 0);
dfi->max_channels = 2;
+ dfi->buswidth[0] = FIELD_GET(RK3399_PMUGRF_OS_REG2_BW_CH0, val) == 0 ? 4 : 2;
+ dfi->buswidth[1] = FIELD_GET(RK3399_PMUGRF_OS_REG2_BW_CH1, val) == 0 ? 4 : 2;
+
return 0;
};
@@ -265,6 +688,8 @@ static int rk3568_dfi_init(struct rockchip_dfi *dfi)
dfi->channel_mask = BIT(0);
dfi->max_channels = 1;
+ dfi->buswidth[0] = FIELD_GET(RK3568_PMUGRF_OS_REG2_BW_CH0, reg2) == 0 ? 4 : 2;
+
return 0;
};
@@ -325,6 +750,10 @@ static int rockchip_dfi_probe(struct platform_device *pdev)
return PTR_ERR(dfi->edev);
}
+ ret = rockchip_ddr_perf_init(dfi);
+ if (ret)
+ return ret;
+
platform_set_drvdata(pdev, dfi);
return 0;
@@ -335,6 +764,7 @@ static struct platform_driver rockchip_dfi_driver = {
.driver = {
.name = "rockchip-dfi",
.of_match_table = rockchip_dfi_id_match,
+ .suppress_bind_attrs = true,
},
};
module_platform_driver(rockchip_dfi_driver);
diff --git a/include/soc/rockchip/rk3399_grf.h b/include/soc/rockchip/rk3399_grf.h
index 775f8444bea8d..39cd44cec982f 100644
--- a/include/soc/rockchip/rk3399_grf.h
+++ b/include/soc/rockchip/rk3399_grf.h
@@ -12,5 +12,7 @@
/* PMU GRF Registers */
#define RK3399_PMUGRF_OS_REG2 0x308
#define RK3399_PMUGRF_OS_REG2_DDRTYPE GENMASK(15, 13)
+#define RK3399_PMUGRF_OS_REG2_BW_CH0 GENMASK(3, 2)
+#define RK3399_PMUGRF_OS_REG2_BW_CH1 GENMASK(19, 18)
#endif
diff --git a/include/soc/rockchip/rk3568_grf.h b/include/soc/rockchip/rk3568_grf.h
index 575584e9d8834..52853efd6720e 100644
--- a/include/soc/rockchip/rk3568_grf.h
+++ b/include/soc/rockchip/rk3568_grf.h
@@ -4,6 +4,7 @@
#define RK3568_PMUGRF_OS_REG2 0x208
#define RK3568_PMUGRF_OS_REG2_DRAMTYPE_INFO GENMASK(15, 13)
+#define RK3568_PMUGRF_OS_REG2_BW_CH0 GENMASK(3, 2)
#define RK3568_PMUGRF_OS_REG3 0x20c
#define RK3568_PMUGRF_OS_REG3_DRAMTYPE_INFO_V3 GENMASK(13, 12)
--
2.39.2
Hi Chanwoo,
On Thu, Oct 19, 2023 at 12:11:14AM +0900, Chanwoo Choi wrote:
> Hi Sascha,
>
> Could you plesae fix the following kernel build report?
Just did that as a reply to the original patch. I moved
rockchip_ddr_perf_counters_add() inside the #ifdef CONFIG_PERF_EVENTS
Thanks for reviewing this series and for bringing it forward.
Sascha
>
> On 23. 10. 18. 16:58, kernel test robot wrote:
> > Hi Sascha,
> >
> > kernel test robot noticed the following build warnings:
> >
> > [auto build test WARNING on linus/master]
> > [also build test WARNING on v6.6-rc6]
> > [cannot apply to next-20231018]
> > [If your patch is applied to the wrong git tree, kindly drop us a note.
> > And when submitting patch, we suggest to use '--base' as documented in
> > https://git-scm.com/docs/git-format-patch#_base_tree_information]
> >
> > url: https://github.com/intel-lab-lkp/linux/commits/Sascha-Hauer/PM-devfreq-rockchip-dfi-Make-pmu-regmap-mandatory/20231018-142228
> > base: linus/master
> > patch link: https://lore.kernel.org/r/20231018061714.3553817-17-s.hauer%40pengutronix.de
> > patch subject: [PATCH v8 16/26] PM / devfreq: rockchip-dfi: Add perf support
> > config: m68k-allyesconfig (https://download.01.org/0day-ci/archive/20231018/[email protected]/config)
> > compiler: m68k-linux-gcc (GCC) 13.2.0
> > reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20231018/[email protected]/reproduce)
> >
> > If you fix the issue in a separate patch/commit (i.e. not just a new version of
> > the same patch/commit), kindly add following tags
> > | Reported-by: kernel test robot <[email protected]>
> > | Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/
> >
> > All warnings (new ones prefixed by >>):
> >
> >>> drivers/devfreq/event/rockchip-dfi.c:203:13: warning: 'rockchip_ddr_perf_counters_add' defined but not used [-Wunused-function]
> > 203 | static void rockchip_ddr_perf_counters_add(struct rockchip_dfi *dfi,
> > | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> > --
> >>> drivers/devfreq/event/rockchip-dfi.c:79: warning: Function parameter or member 'write_access' not described in 'dmc_count_channel'
> >
> >
> > vim +/rockchip_ddr_perf_counters_add +203 drivers/devfreq/event/rockchip-dfi.c
> >
> > 66
> > 67 /**
> > 68 * struct dmc_count_channel - structure to hold counter values from the DDR controller
> > 69 * @access: Number of read and write accesses
> > 70 * @clock_cycles: DDR clock cycles
> > 71 * @read_access: number of read accesses
> > 72 * @write_acccess: number of write accesses
> > 73 */
> > 74 struct dmc_count_channel {
> > 75 u64 access;
> > 76 u64 clock_cycles;
> > 77 u64 read_access;
> > 78 u64 write_access;
> > > 79 };
> > 80
> > 81 struct dmc_count {
> > 82 struct dmc_count_channel c[DMC_MAX_CHANNELS];
> > 83 };
> > 84
> > 85 /*
> > 86 * The dfi controller can monitor DDR load. It has an upper and lower threshold
> > 87 * for the operating points. Whenever the usage leaves these bounds an event is
> > 88 * generated to indicate the DDR frequency should be changed.
> > 89 */
> > 90 struct rockchip_dfi {
> > 91 struct devfreq_event_dev *edev;
> > 92 struct devfreq_event_desc desc;
> > 93 struct dmc_count last_event_count;
> > 94
> > 95 struct dmc_count last_perf_count;
> > 96 struct dmc_count total_count;
> > 97 seqlock_t count_seqlock; /* protects last_perf_count and total_count */
> > 98
> > 99 struct device *dev;
> > 100 void __iomem *regs;
> > 101 struct regmap *regmap_pmu;
> > 102 struct clk *clk;
> > 103 int usecount;
> > 104 struct mutex mutex;
> > 105 u32 ddr_type;
> > 106 unsigned int channel_mask;
> > 107 unsigned int max_channels;
> > 108 enum cpuhp_state cpuhp_state;
> > 109 struct hlist_node node;
> > 110 struct pmu pmu;
> > 111 struct hrtimer timer;
> > 112 unsigned int cpu;
> > 113 int active_events;
> > 114 int burst_len;
> > 115 int buswidth[DMC_MAX_CHANNELS];
> > 116 };
> > 117
> > 118 static int rockchip_dfi_enable(struct rockchip_dfi *dfi)
> > 119 {
> > 120 void __iomem *dfi_regs = dfi->regs;
> > 121 int ret = 0;
> > 122
> > 123 mutex_lock(&dfi->mutex);
> > 124
> > 125 dfi->usecount++;
> > 126 if (dfi->usecount > 1)
> > 127 goto out;
> > 128
> > 129 ret = clk_prepare_enable(dfi->clk);
> > 130 if (ret) {
> > 131 dev_err(&dfi->edev->dev, "failed to enable dfi clk: %d\n", ret);
> > 132 goto out;
> > 133 }
> > 134
> > 135 /* clear DDRMON_CTRL setting */
> > 136 writel_relaxed(HIWORD_UPDATE(0, DDRMON_CTRL_TIMER_CNT_EN | DDRMON_CTRL_SOFTWARE_EN |
> > 137 DDRMON_CTRL_HARDWARE_EN), dfi_regs + DDRMON_CTRL);
> > 138
> > 139 /* set ddr type to dfi */
> > 140 switch (dfi->ddr_type) {
> > 141 case ROCKCHIP_DDRTYPE_LPDDR2:
> > 142 case ROCKCHIP_DDRTYPE_LPDDR3:
> > 143 writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR23, DDRMON_CTRL_DDR_TYPE_MASK),
> > 144 dfi_regs + DDRMON_CTRL);
> > 145 break;
> > 146 case ROCKCHIP_DDRTYPE_LPDDR4:
> > 147 case ROCKCHIP_DDRTYPE_LPDDR4X:
> > 148 writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR4, DDRMON_CTRL_DDR_TYPE_MASK),
> > 149 dfi_regs + DDRMON_CTRL);
> > 150 break;
> > 151 default:
> > 152 break;
> > 153 }
> > 154
> > 155 /* enable count, use software mode */
> > 156 writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_SOFTWARE_EN, DDRMON_CTRL_SOFTWARE_EN),
> > 157 dfi_regs + DDRMON_CTRL);
> > 158 out:
> > 159 mutex_unlock(&dfi->mutex);
> > 160
> > 161 return ret;
> > 162 }
> > 163
> > 164 static void rockchip_dfi_disable(struct rockchip_dfi *dfi)
> > 165 {
> > 166 void __iomem *dfi_regs = dfi->regs;
> > 167
> > 168 mutex_lock(&dfi->mutex);
> > 169
> > 170 dfi->usecount--;
> > 171
> > 172 WARN_ON_ONCE(dfi->usecount < 0);
> > 173
> > 174 if (dfi->usecount > 0)
> > 175 goto out;
> > 176
> > 177 writel_relaxed(HIWORD_UPDATE(0, DDRMON_CTRL_SOFTWARE_EN),
> > 178 dfi_regs + DDRMON_CTRL);
> > 179 clk_disable_unprepare(dfi->clk);
> > 180 out:
> > 181 mutex_unlock(&dfi->mutex);
> > 182 }
> > 183
> > 184 static void rockchip_dfi_read_counters(struct rockchip_dfi *dfi, struct dmc_count *res)
> > 185 {
> > 186 u32 i;
> > 187 void __iomem *dfi_regs = dfi->regs;
> > 188
> > 189 for (i = 0; i < dfi->max_channels; i++) {
> > 190 if (!(dfi->channel_mask & BIT(i)))
> > 191 continue;
> > 192 res->c[i].read_access = readl_relaxed(dfi_regs +
> > 193 DDRMON_CH0_RD_NUM + i * 20);
> > 194 res->c[i].write_access = readl_relaxed(dfi_regs +
> > 195 DDRMON_CH0_WR_NUM + i * 20);
> > 196 res->c[i].access = readl_relaxed(dfi_regs +
> > 197 DDRMON_CH0_DFI_ACCESS_NUM + i * 20);
> > 198 res->c[i].clock_cycles = readl_relaxed(dfi_regs +
> > 199 DDRMON_CH0_COUNT_NUM + i * 20);
> > 200 }
> > 201 }
> > 202
> > > 203 static void rockchip_ddr_perf_counters_add(struct rockchip_dfi *dfi,
> > 204 const struct dmc_count *now,
> > 205 struct dmc_count *res)
> > 206 {
> > 207 const struct dmc_count *last = &dfi->last_perf_count;
> > 208 int i;
> > 209
> > 210 for (i = 0; i < dfi->max_channels; i++) {
> > 211 res->c[i].read_access = dfi->total_count.c[i].read_access +
> > 212 (u32)(now->c[i].read_access - last->c[i].read_access);
> > 213 res->c[i].write_access = dfi->total_count.c[i].write_access +
> > 214 (u32)(now->c[i].write_access - last->c[i].write_access);
> > 215 res->c[i].access = dfi->total_count.c[i].access +
> > 216 (u32)(now->c[i].access - last->c[i].access);
> > 217 res->c[i].clock_cycles = dfi->total_count.c[i].clock_cycles +
> > 218 (u32)(now->c[i].clock_cycles - last->c[i].clock_cycles);
> > 219 }
> > 220 }
> > 221
> >
>
> --
> Best Regards,
> Samsung Electronics
> Chanwoo Choi
>
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
On Wed, 18 Oct 2023 08:16:48 +0200, Sascha Hauer wrote:
> This series integrates the recent review feedback from Chanwoo Choi to
> v7.
>
> Chanwoo, I am sending the full patchset again for people to try this
> series. You said that you applied 1-5 already, so please start picking
> from 6/26.
>
> [...]
Applied, thanks!
[23/26] dt-bindings: soc: rockchip: grf: add rockchip,rk3588-pmugrf
commit: 3bd1c0c62bad8ea7f9cc6662e754f77ec8baa46e
I've grabbed the pmugrf compatible addition for now, so I can send
out the pull request for my "drivers" branch.
Best regards,
--
Heiko Stuebner <[email protected]>
> -----Original Message-----
> From: Chanwoo Choi <[email protected]>
> Sent: Thursday, October 19, 2023 12:06 AM
> To: Sascha Hauer <[email protected]>; linux-
> [email protected]
> Cc: [email protected]; [email protected];
> [email protected]; Heiko Stuebner <[email protected]>; Kyungmin Park
> <[email protected]>; MyungJoo Ham <[email protected]>; Will
> Deacon <[email protected]>; Mark Rutland <[email protected]>;
> [email protected]; Michael Riesch <[email protected]>;
> Robin Murphy <[email protected]>; Vincent Legoll
> <[email protected]>; Rob Herring <[email protected]>; Krzysztof
> Kozlowski <[email protected]>; Conor Dooley
> <[email protected]>; [email protected]; Sebastian Reichel
> <[email protected]>
> Subject: Re: [PATCH v8 07/26] PM / devfreq: rockchip-dfi: introduce
> channel mask
>
> On 23. 10. 18. 15:16, Sascha Hauer wrote:
> > Different Rockchip SoC variants have a different number of channels.
> > Introduce a channel mask to make the number of channels configurable
> > from SoC initialization code.
> >
> > Reviewed-by: Sebastian Reichel <[email protected]>
> > Signed-off-by: Sascha Hauer <[email protected]>
> > ---
> >
> > Notes:
> > Changes since v7:
> > - Loop only over channels present on a SoC
> >
> > drivers/devfreq/event/rockchip-dfi.c | 25 +++++++++++++++++++------
> > 1 file changed, 19 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/devfreq/event/rockchip-dfi.c
> > b/drivers/devfreq/event/rockchip-dfi.c
> > index 126bb744645b6..28c18bbf6baa5 100644
> > --- a/drivers/devfreq/event/rockchip-dfi.c
> > +++ b/drivers/devfreq/event/rockchip-dfi.c
> > @@ -18,10 +18,11 @@
> > #include <linux/list.h>
> > #include <linux/of.h>
> > #include <linux/of_device.h>
> > +#include <linux/bits.h>
> >
> > #include <soc/rockchip/rk3399_grf.h>
> >
> > -#define RK3399_DMC_NUM_CH 2
> > +#define DMC_MAX_CHANNELS 2
> >
> > /* DDRMON_CTRL */
> > #define DDRMON_CTRL 0x04
> > @@ -44,7 +45,7 @@ struct dmc_count_channel { };
> >
> > struct dmc_count {
> > - struct dmc_count_channel c[RK3399_DMC_NUM_CH];
> > + struct dmc_count_channel c[DMC_MAX_CHANNELS];
> > };
> >
> > /*
> > @@ -61,6 +62,8 @@ struct rockchip_dfi {
> > struct regmap *regmap_pmu;
> > struct clk *clk;
> > u32 ddr_type;
> > + unsigned int channel_mask;
> > + unsigned int max_channels;
> > };
> >
> > static void rockchip_dfi_start_hardware_counter(struct
> > devfreq_event_dev *edev) @@ -95,7 +98,9 @@ static void
> rockchip_dfi_read_counters(struct devfreq_event_dev *edev, struct dm
> > u32 i;
> > void __iomem *dfi_regs = dfi->regs;
> >
> > - for (i = 0; i < RK3399_DMC_NUM_CH; i++) {
> > + for (i = 0; i < dfi->max_channels; i++) {
> > + if (!(dfi->channel_mask & BIT(i)))
> > + continue;
> > count->c[i].access = readl_relaxed(dfi_regs +
> > DDRMON_CH0_DFI_ACCESS_NUM + i * 20);
> > count->c[i].total = readl_relaxed(dfi_regs + @@ -145,9
> +150,14 @@
> > static int rockchip_dfi_get_event(struct devfreq_event_dev *edev,
> > rockchip_dfi_read_counters(edev, &count);
> >
> > /* We can only report one channel, so find the busiest one */
> > - for (i = 0; i < RK3399_DMC_NUM_CH; i++) {
> > - u32 a = count.c[i].access - last->c[i].access;
> > - u32 t = count.c[i].total - last->c[i].total;
> > + for (i = 0; i < dfi->max_channels; i++) {
> > + u32 a, t;
> > +
> > + if (!(dfi->channel_mask & BIT(i)))
> > + continue;
> > +
> > + a = count.c[i].access - last->c[i].access;
> > + t = count.c[i].total - last->c[i].total;
> >
> > if (a > access) {
> > access = a;
> > @@ -185,6 +195,9 @@ static int rk3399_dfi_init(struct rockchip_dfi *dfi)
> > dfi->ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) &
> > RK3399_PMUGRF_DDRTYPE_MASK;
> >
> > + dfi->channel_mask = GENMASK(1, 0);
> > + dfi->max_channels = 2;
> > +
> > return 0;
> > };
> >
>
> Acked-by: Chanwoo Choi <[email protected]>
>
Applied it. Thanks.
Best Regards,
Chanwoo Choi
> -----Original Message-----
> From: Sascha Hauer <[email protected]>
> Sent: Wednesday, October 18, 2023 3:17 PM
> To: [email protected]
> Cc: [email protected]; [email protected];
> [email protected]; Heiko Stuebner <[email protected]>; Chanwoo Choi
> <[email protected]>; Kyungmin Park <[email protected]>; MyungJoo
> Ham <[email protected]>; Will Deacon <[email protected]>; Mark
> Rutland <[email protected]>; [email protected]; Michael Riesch
> <[email protected]>; Robin Murphy <[email protected]>;
> Vincent Legoll <[email protected]>; Rob Herring
> <[email protected]>; Krzysztof Kozlowski
> <[email protected]>; Conor Dooley <[email protected]>;
> [email protected]; Sebastian Reichel
> <[email protected]>; Sascha Hauer <[email protected]>;
> Chanwoo Choi <[email protected]>
> Subject: [PATCH v8 08/26] PM / devfreq: rk3399_dmc,dfi: generalize DDRTYPE
> defines
>
> The DDRTYPE defines are named to be RK3399 specific, but they can be used
> for other Rockchip SoCs as well, so replace the RK3399_PMUGRF_ prefix with
> ROCKCHIP_. They are defined in a SoC specific header file, so when
> generalizing the prefix also move the new defines to a SoC agnostic header
> file. While at it use GENMASK to define the DDRTYPE bitfield and give it a
> name including the full register name.
>
> Reviewed-by: Sebastian Reichel <[email protected]>
> Acked-by: Chanwoo Choi <[email protected]>
> Signed-off-by: Sascha Hauer <[email protected]>
> ---
> drivers/devfreq/event/rockchip-dfi.c | 9 +++++----
> drivers/devfreq/rk3399_dmc.c | 10 +++++-----
> include/soc/rockchip/rk3399_grf.h | 7 +------
> include/soc/rockchip/rockchip_grf.h | 17 +++++++++++++++++
> 4 files changed, 28 insertions(+), 15 deletions(-) create mode 100644
> include/soc/rockchip/rockchip_grf.h
>
> diff --git a/drivers/devfreq/event/rockchip-dfi.c
> b/drivers/devfreq/event/rockchip-dfi.c
> index 28c18bbf6baa5..82d18c60538a5 100644
> --- a/drivers/devfreq/event/rockchip-dfi.c
> +++ b/drivers/devfreq/event/rockchip-dfi.c
> @@ -18,8 +18,10 @@
> #include <linux/list.h>
> #include <linux/of.h>
> #include <linux/of_device.h>
> +#include <linux/bitfield.h>
> #include <linux/bits.h>
>
> +#include <soc/rockchip/rockchip_grf.h>
> #include <soc/rockchip/rk3399_grf.h>
>
> #define DMC_MAX_CHANNELS 2
> @@ -75,9 +77,9 @@ static void rockchip_dfi_start_hardware_counter(struct
> devfreq_event_dev *edev)
> writel_relaxed(CLR_DDRMON_CTRL, dfi_regs + DDRMON_CTRL);
>
> /* set ddr type to dfi */
> - if (dfi->ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR3)
> + if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR3)
> writel_relaxed(LPDDR3_EN, dfi_regs + DDRMON_CTRL);
> - else if (dfi->ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR4)
> + else if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR4)
> writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL);
>
> /* enable count, use software mode */
> @@ -192,8 +194,7 @@ static int rk3399_dfi_init(struct rockchip_dfi *dfi)
>
> /* get ddr type */
> regmap_read(regmap_pmu, RK3399_PMUGRF_OS_REG2, &val);
> - dfi->ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) &
> - RK3399_PMUGRF_DDRTYPE_MASK;
> + dfi->ddr_type = FIELD_GET(RK3399_PMUGRF_OS_REG2_DDRTYPE, val);
>
> dfi->channel_mask = GENMASK(1, 0);
> dfi->max_channels = 2;
> diff --git a/drivers/devfreq/rk3399_dmc.c b/drivers/devfreq/rk3399_dmc.c
> index daff407026157..fd2c5ffedf41e 100644
> --- a/drivers/devfreq/rk3399_dmc.c
> +++ b/drivers/devfreq/rk3399_dmc.c
> @@ -22,6 +22,7 @@
> #include <linux/suspend.h>
>
> #include <soc/rockchip/pm_domains.h>
> +#include <soc/rockchip/rockchip_grf.h>
> #include <soc/rockchip/rk3399_grf.h>
> #include <soc/rockchip/rockchip_sip.h>
>
> @@ -381,17 +382,16 @@ static int rk3399_dmcfreq_probe(struct
> platform_device *pdev)
> }
>
> regmap_read(data->regmap_pmu, RK3399_PMUGRF_OS_REG2, &val);
> - ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) &
> - RK3399_PMUGRF_DDRTYPE_MASK;
> + ddr_type = FIELD_GET(RK3399_PMUGRF_OS_REG2_DDRTYPE, val);
>
> switch (ddr_type) {
> - case RK3399_PMUGRF_DDRTYPE_DDR3:
> + case ROCKCHIP_DDRTYPE_DDR3:
> data->odt_dis_freq = data->ddr3_odt_dis_freq;
> break;
> - case RK3399_PMUGRF_DDRTYPE_LPDDR3:
> + case ROCKCHIP_DDRTYPE_LPDDR3:
> data->odt_dis_freq = data->lpddr3_odt_dis_freq;
> break;
> - case RK3399_PMUGRF_DDRTYPE_LPDDR4:
> + case ROCKCHIP_DDRTYPE_LPDDR4:
> data->odt_dis_freq = data->lpddr4_odt_dis_freq;
> break;
> default:
> diff --git a/include/soc/rockchip/rk3399_grf.h
> b/include/soc/rockchip/rk3399_grf.h
> index 3eebabcb28123..775f8444bea8d 100644
> --- a/include/soc/rockchip/rk3399_grf.h
> +++ b/include/soc/rockchip/rk3399_grf.h
> @@ -11,11 +11,6 @@
>
> /* PMU GRF Registers */
> #define RK3399_PMUGRF_OS_REG2 0x308
> -#define RK3399_PMUGRF_DDRTYPE_SHIFT 13
> -#define RK3399_PMUGRF_DDRTYPE_MASK 7
> -#define RK3399_PMUGRF_DDRTYPE_DDR3 3
> -#define RK3399_PMUGRF_DDRTYPE_LPDDR2 5
> -#define RK3399_PMUGRF_DDRTYPE_LPDDR3 6
> -#define RK3399_PMUGRF_DDRTYPE_LPDDR4 7
> +#define RK3399_PMUGRF_OS_REG2_DDRTYPE GENMASK(15, 13)
>
> #endif
> diff --git a/include/soc/rockchip/rockchip_grf.h
> b/include/soc/rockchip/rockchip_grf.h
> new file mode 100644
> index 0000000000000..dde1a9796ccb5
> --- /dev/null
> +++ b/include/soc/rockchip/rockchip_grf.h
> @@ -0,0 +1,17 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Rockchip General Register Files definitions */
> +
> +#ifndef __SOC_ROCKCHIP_GRF_H
> +#define __SOC_ROCKCHIP_GRF_H
> +
> +/* Rockchip DDRTYPE defines */
> +enum {
> + ROCKCHIP_DDRTYPE_DDR3 = 3,
> + ROCKCHIP_DDRTYPE_LPDDR2 = 5,
> + ROCKCHIP_DDRTYPE_LPDDR3 = 6,
> + ROCKCHIP_DDRTYPE_LPDDR4 = 7,
> +};
> +
> +#endif /* __SOC_ROCKCHIP_GRF_H */
> --
> 2.39.2
Applied it. Thanks
Best Regards,
Chanwoo Choi
> -----Original Message-----
> From: Sascha Hauer <[email protected]>
> Sent: Wednesday, October 18, 2023 3:17 PM
> To: [email protected]
> Cc: [email protected]; [email protected];
> [email protected]; Heiko Stuebner <[email protected]>; Chanwoo Choi
> <[email protected]>; Kyungmin Park <[email protected]>; MyungJoo
> Ham <[email protected]>; Will Deacon <[email protected]>; Mark
> Rutland <[email protected]>; [email protected]; Michael Riesch
> <[email protected]>; Robin Murphy <[email protected]>;
> Vincent Legoll <[email protected]>; Rob Herring
> <[email protected]>; Krzysztof Kozlowski
> <[email protected]>; Conor Dooley <[email protected]>;
> [email protected]; Sebastian Reichel
> <[email protected]>; Sascha Hauer <[email protected]>;
> Chanwoo Choi <[email protected]>
> Subject: [PATCH v8 09/26] PM / devfreq: rockchip-dfi: Clean up DDR type
> register defines
>
> Use the HIWORD_UPDATE() define known from other rockchip drivers to make
> the defines look less odd to the readers who've seen other rockchip
> drivers.
>
> The HIWORD registers have their functional bits in the lower 16 bits
> whereas the upper 16 bits contain a mask. Only the functional bits that
> have the corresponding mask bit set are modified during a write. Although
> the register writes look different, the end result should be the same, at
> least there's no functional change intended with this patch.
>
> Signed-off-by: Sascha Hauer <[email protected]>
> Reviewed-by: Sebastian Reichel <[email protected]>
> Acked-by: Chanwoo Choi <[email protected]>
> ---
> drivers/devfreq/event/rockchip-dfi.c | 33 ++++++++++++++++++----------
> 1 file changed, 21 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/devfreq/event/rockchip-dfi.c
> b/drivers/devfreq/event/rockchip-dfi.c
> index 82d18c60538a5..12f9096879235 100644
> --- a/drivers/devfreq/event/rockchip-dfi.c
> +++ b/drivers/devfreq/event/rockchip-dfi.c
> @@ -26,15 +26,19 @@
>
> #define DMC_MAX_CHANNELS 2
>
> +#define HIWORD_UPDATE(val, mask) ((val) | (mask) << 16)
> +
> /* DDRMON_CTRL */
> #define DDRMON_CTRL 0x04
> -#define CLR_DDRMON_CTRL (0x1f0000 << 0)
> -#define LPDDR4_EN (0x10001 << 4)
> -#define HARDWARE_EN (0x10001 << 3)
> -#define LPDDR3_EN (0x10001 << 2)
> -#define SOFTWARE_EN (0x10001 << 1)
> -#define SOFTWARE_DIS (0x10000 << 1)
> -#define TIME_CNT_EN (0x10001 << 0)
> +#define DDRMON_CTRL_DDR4 BIT(5)
> +#define DDRMON_CTRL_LPDDR4 BIT(4)
> +#define DDRMON_CTRL_HARDWARE_EN BIT(3)
> +#define DDRMON_CTRL_LPDDR23 BIT(2)
> +#define DDRMON_CTRL_SOFTWARE_EN BIT(1)
> +#define DDRMON_CTRL_TIMER_CNT_EN BIT(0)
> +#define DDRMON_CTRL_DDR_TYPE_MASK (DDRMON_CTRL_DDR4 | \
> + DDRMON_CTRL_LPDDR4 | \
> + DDRMON_CTRL_LPDDR23)
>
> #define DDRMON_CH0_COUNT_NUM 0x28
> #define DDRMON_CH0_DFI_ACCESS_NUM 0x2c
> @@ -74,16 +78,20 @@ static void rockchip_dfi_start_hardware_counter(struct
> devfreq_event_dev *edev)
> void __iomem *dfi_regs = dfi->regs;
>
> /* clear DDRMON_CTRL setting */
> - writel_relaxed(CLR_DDRMON_CTRL, dfi_regs + DDRMON_CTRL);
> + writel_relaxed(HIWORD_UPDATE(0, DDRMON_CTRL_TIMER_CNT_EN |
> DDRMON_CTRL_SOFTWARE_EN |
> + DDRMON_CTRL_HARDWARE_EN), dfi_regs + DDRMON_CTRL);
>
> /* set ddr type to dfi */
> if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR3)
> - writel_relaxed(LPDDR3_EN, dfi_regs + DDRMON_CTRL);
> + writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR23,
> DDRMON_CTRL_DDR_TYPE_MASK),
> + dfi_regs + DDRMON_CTRL);
> else if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR4)
> - writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL);
> + writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR4,
> DDRMON_CTRL_DDR_TYPE_MASK),
> + dfi_regs + DDRMON_CTRL);
>
> /* enable count, use software mode */
> - writel_relaxed(SOFTWARE_EN, dfi_regs + DDRMON_CTRL);
> + writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_SOFTWARE_EN,
> DDRMON_CTRL_SOFTWARE_EN),
> + dfi_regs + DDRMON_CTRL);
> }
>
> static void rockchip_dfi_stop_hardware_counter(struct devfreq_event_dev
> *edev) @@ -91,7 +99,8 @@ static void
> rockchip_dfi_stop_hardware_counter(struct devfreq_event_dev *edev)
> struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);
> void __iomem *dfi_regs = dfi->regs;
>
> - writel_relaxed(SOFTWARE_DIS, dfi_regs + DDRMON_CTRL);
> + writel_relaxed(HIWORD_UPDATE(0, DDRMON_CTRL_SOFTWARE_EN),
> + dfi_regs + DDRMON_CTRL);
> }
>
> static void rockchip_dfi_read_counters(struct devfreq_event_dev *edev,
> struct dmc_count *count)
> --
> 2.39.2
Applied it. Thanks
Best Regards,
Chanwoo Choi
> -----Original Message-----
> From: Sascha Hauer <[email protected]>
> Sent: Wednesday, October 18, 2023 3:17 PM
> To: [email protected]
> Cc: [email protected]; [email protected];
> [email protected]; Heiko Stuebner <[email protected]>; Chanwoo Choi
> <[email protected]>; Kyungmin Park <[email protected]>; MyungJoo
> Ham <[email protected]>; Will Deacon <[email protected]>; Mark
> Rutland <[email protected]>; [email protected]; Michael Riesch
> <[email protected]>; Robin Murphy <[email protected]>;
> Vincent Legoll <[email protected]>; Rob Herring
> <[email protected]>; Krzysztof Kozlowski
> <[email protected]>; Conor Dooley <[email protected]>;
> [email protected]; Sebastian Reichel
> <[email protected]>; Sascha Hauer <[email protected]>
> Subject: [PATCH v8 10/26] PM / devfreq: rockchip-dfi: Add RK3568 support
>
> This adds RK3568 support to the DFI driver. Only iniitialization differs
> from the currently supported RK3399.
>
> Signed-off-by: Sascha Hauer <[email protected]>
> ---
>
> Notes:
> Changes since v7:
> - Add comment to explain << 3
>
> drivers/devfreq/event/rockchip-dfi.c | 27 +++++++++++++++++++++++++++
> include/soc/rockchip/rk3568_grf.h | 12 ++++++++++++
> 2 files changed, 39 insertions(+)
> create mode 100644 include/soc/rockchip/rk3568_grf.h
>
> diff --git a/drivers/devfreq/event/rockchip-dfi.c
> b/drivers/devfreq/event/rockchip-dfi.c
> index 12f9096879235..571d72d1abd1c 100644
> --- a/drivers/devfreq/event/rockchip-dfi.c
> +++ b/drivers/devfreq/event/rockchip-dfi.c
> @@ -23,6 +23,7 @@
>
> #include <soc/rockchip/rockchip_grf.h>
> #include <soc/rockchip/rk3399_grf.h>
> +#include <soc/rockchip/rk3568_grf.h>
>
> #define DMC_MAX_CHANNELS 2
>
> @@ -211,10 +212,36 @@ static int rk3399_dfi_init(struct rockchip_dfi *dfi)
> return 0;
> };
>
> +static int rk3568_dfi_init(struct rockchip_dfi *dfi) {
> + struct regmap *regmap_pmu = dfi->regmap_pmu;
> + u32 reg2, reg3;
> +
> + regmap_read(regmap_pmu, RK3568_PMUGRF_OS_REG2, ®2);
> + regmap_read(regmap_pmu, RK3568_PMUGRF_OS_REG3, ®3);
> +
> + /* lower 3 bits of the DDR type */
> + dfi->ddr_type = FIELD_GET(RK3568_PMUGRF_OS_REG2_DRAMTYPE_INFO,
> reg2);
> +
> + /*
> + * For version three and higher the upper two bits of the DDR type
> are
> + * in RK3568_PMUGRF_OS_REG3
> + */
> + if (FIELD_GET(RK3568_PMUGRF_OS_REG3_SYSREG_VERSION, reg3) >= 0x3)
> + dfi->ddr_type |=
> FIELD_GET(RK3568_PMUGRF_OS_REG3_DRAMTYPE_INFO_V3,
> +reg3) << 3;
> +
> + dfi->channel_mask = BIT(0);
> + dfi->max_channels = 1;
> +
> + return 0;
> +};
> +
> static const struct of_device_id rockchip_dfi_id_match[] = {
> { .compatible = "rockchip,rk3399-dfi", .data = rk3399_dfi_init },
> + { .compatible = "rockchip,rk3568-dfi", .data = rk3568_dfi_init },
> { },
> };
> +
> MODULE_DEVICE_TABLE(of, rockchip_dfi_id_match);
>
> static int rockchip_dfi_probe(struct platform_device *pdev) diff --git
> a/include/soc/rockchip/rk3568_grf.h b/include/soc/rockchip/rk3568_grf.h
> new file mode 100644
> index 0000000000000..575584e9d8834
> --- /dev/null
> +++ b/include/soc/rockchip/rk3568_grf.h
> @@ -0,0 +1,12 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __SOC_RK3568_GRF_H
> +#define __SOC_RK3568_GRF_H
> +
> +#define RK3568_PMUGRF_OS_REG2 0x208
> +#define RK3568_PMUGRF_OS_REG2_DRAMTYPE_INFO GENMASK(15, 13)
> +
> +#define RK3568_PMUGRF_OS_REG3 0x20c
> +#define RK3568_PMUGRF_OS_REG3_DRAMTYPE_INFO_V3 GENMASK(13,
12)
> +#define RK3568_PMUGRF_OS_REG3_SYSREG_VERSION GENMASK(31, 28)
> +
> +#endif /* __SOC_RK3568_GRF_H */
> --
> 2.39.2
Applied it. Thanks
Best Regards,
Chanwoo Choi
> -----Original Message-----
> From: Sascha Hauer <[email protected]>
> Sent: Wednesday, October 18, 2023 3:17 PM
> To: [email protected]
> Cc: [email protected]; [email protected];
> [email protected]; Heiko Stuebner <[email protected]>; Chanwoo Choi
> <[email protected]>; Kyungmin Park <[email protected]>; MyungJoo
> Ham <[email protected]>; Will Deacon <[email protected]>; Mark
> Rutland <[email protected]>; [email protected]; Michael Riesch
> <[email protected]>; Robin Murphy <[email protected]>;
> Vincent Legoll <[email protected]>; Rob Herring
> <[email protected]>; Krzysztof Kozlowski
> <[email protected]>; Conor Dooley <[email protected]>;
> [email protected]; Sebastian Reichel
> <[email protected]>; Sascha Hauer <[email protected]>;
> Jonathan Cameron <[email protected]>; Chanwoo Choi
> <[email protected]>
> Subject: [PATCH v8 11/26] PM / devfreq: rockchip-dfi: Handle LPDDR2
> correctly
>
> According to the downstream driver the DDRMON_CTRL_LPDDR23 bit must be set
> for both LPDDR2 and LPDDR3. Add the missing LPDDR2 case and while at it
> turn the if/else if/else into switch/case which makes it easier to read.
>
> Reviewed-by: Jonathan Cameron <[email protected]>
> Reviewed-by: Sebastian Reichel <[email protected]>
> Acked-by: Chanwoo Choi <[email protected]>
> Signed-off-by: Sascha Hauer <[email protected]>
> ---
> drivers/devfreq/event/rockchip-dfi.c | 11 +++++++++--
> 1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/devfreq/event/rockchip-dfi.c
> b/drivers/devfreq/event/rockchip-dfi.c
> index 571d72d1abd1c..8ce0191552ef1 100644
> --- a/drivers/devfreq/event/rockchip-dfi.c
> +++ b/drivers/devfreq/event/rockchip-dfi.c
> @@ -83,12 +83,19 @@ static void rockchip_dfi_start_hardware_counter(struct
> devfreq_event_dev *edev)
> DDRMON_CTRL_HARDWARE_EN), dfi_regs + DDRMON_CTRL);
>
> /* set ddr type to dfi */
> - if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR3)
> + switch (dfi->ddr_type) {
> + case ROCKCHIP_DDRTYPE_LPDDR2:
> + case ROCKCHIP_DDRTYPE_LPDDR3:
> writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR23,
> DDRMON_CTRL_DDR_TYPE_MASK),
> dfi_regs + DDRMON_CTRL);
> - else if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR4)
> + break;
> + case ROCKCHIP_DDRTYPE_LPDDR4:
> writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR4,
> DDRMON_CTRL_DDR_TYPE_MASK),
> dfi_regs + DDRMON_CTRL);
> + break;
> + default:
> + break;
> + }
>
> /* enable count, use software mode */
> writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_SOFTWARE_EN,
> DDRMON_CTRL_SOFTWARE_EN),
> --
> 2.39.2
Applied it. Thanks
Best Regards,
Chanwoo Choi
> -----Original Message-----
> From: Sascha Hauer <[email protected]>
> Sent: Wednesday, October 18, 2023 3:17 PM
> To: [email protected]
> Cc: [email protected]; [email protected];
> [email protected]; Heiko Stuebner <[email protected]>; Chanwoo Choi
> <[email protected]>; Kyungmin Park <[email protected]>; MyungJoo
> Ham <[email protected]>; Will Deacon <[email protected]>; Mark
> Rutland <[email protected]>; [email protected]; Michael Riesch
> <[email protected]>; Robin Murphy <[email protected]>;
> Vincent Legoll <[email protected]>; Rob Herring
> <[email protected]>; Krzysztof Kozlowski
> <[email protected]>; Conor Dooley <[email protected]>;
> [email protected]; Sebastian Reichel
> <[email protected]>; Sascha Hauer <[email protected]>;
> Jonathan Cameron <[email protected]>; Chanwoo Choi
> <[email protected]>
> Subject: [PATCH v8 13/26] PM / devfreq: rockchip-dfi: Pass private data
> struct to internal functions
>
> The internal functions do not need the struct devfreq_event_dev *, so pass
> them the struct rockchip_dfi *. This is a preparation for adding perf
> support later which doesn't have a struct devfreq_event_dev *.
>
> Reviewed-by: Jonathan Cameron <[email protected]>
> Reviewed-by: Sebastian Reichel <[email protected]>
> Acked-by: Chanwoo Choi <[email protected]>
> Signed-off-by: Sascha Hauer <[email protected]>
> ---
> drivers/devfreq/event/rockchip-dfi.c | 15 ++++++---------
> 1 file changed, 6 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/devfreq/event/rockchip-dfi.c
> b/drivers/devfreq/event/rockchip-dfi.c
> index bdf421b248df9..d56a33d03db4c 100644
> --- a/drivers/devfreq/event/rockchip-dfi.c
> +++ b/drivers/devfreq/event/rockchip-dfi.c
> @@ -73,9 +73,8 @@ struct rockchip_dfi {
> unsigned int max_channels;
> };
>
> -static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev
> *edev)
> +static void rockchip_dfi_start_hardware_counter(struct rockchip_dfi
> +*dfi)
> {
> - struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);
> void __iomem *dfi_regs = dfi->regs;
>
> /* clear DDRMON_CTRL setting */
> @@ -103,18 +102,16 @@ static void
> rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
> dfi_regs + DDRMON_CTRL);
> }
>
> -static void rockchip_dfi_stop_hardware_counter(struct devfreq_event_dev
> *edev)
> +static void rockchip_dfi_stop_hardware_counter(struct rockchip_dfi
> +*dfi)
> {
> - struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);
> void __iomem *dfi_regs = dfi->regs;
>
> writel_relaxed(HIWORD_UPDATE(0, DDRMON_CTRL_SOFTWARE_EN),
> dfi_regs + DDRMON_CTRL);
> }
>
> -static void rockchip_dfi_read_counters(struct devfreq_event_dev *edev,
> struct dmc_count *count)
> +static void rockchip_dfi_read_counters(struct rockchip_dfi *dfi, struct
> +dmc_count *count)
> {
> - struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);
> u32 i;
> void __iomem *dfi_regs = dfi->regs;
>
> @@ -132,7 +129,7 @@ static int rockchip_dfi_disable(struct
> devfreq_event_dev *edev) {
> struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);
>
> - rockchip_dfi_stop_hardware_counter(edev);
> + rockchip_dfi_stop_hardware_counter(dfi);
> clk_disable_unprepare(dfi->clk);
>
> return 0;
> @@ -149,7 +146,7 @@ static int rockchip_dfi_enable(struct
> devfreq_event_dev *edev)
> return ret;
> }
>
> - rockchip_dfi_start_hardware_counter(edev);
> + rockchip_dfi_start_hardware_counter(dfi);
> return 0;
> }
>
> @@ -167,7 +164,7 @@ static int rockchip_dfi_get_event(struct
> devfreq_event_dev *edev,
> u32 access = 0, total = 0;
> int i;
>
> - rockchip_dfi_read_counters(edev, &count);
> + rockchip_dfi_read_counters(dfi, &count);
>
> /* We can only report one channel, so find the busiest one */
> for (i = 0; i < dfi->max_channels; i++) {
> --
> 2.39.2
Applied it. Thanks
Best Regards,
Chanwoo Choi
> -----Original Message-----
> From: Sascha Hauer <[email protected]>
> Sent: Thursday, October 19, 2023 3:48 PM
> To: [email protected]
> Cc: [email protected]; [email protected];
> [email protected]; Heiko Stuebner <[email protected]>; Chanwoo Choi
> <[email protected]>; Kyungmin Park <[email protected]>; MyungJoo
> Ham <[email protected]>; Will Deacon <[email protected]>; Mark
> Rutland <[email protected]>; [email protected]; Michael Riesch
> <[email protected]>; Robin Murphy <[email protected]>;
> Vincent Legoll <[email protected]>; Rob Herring
> <[email protected]>; Krzysztof Kozlowski
> <[email protected]>; Conor Dooley <[email protected]>;
> [email protected]; Sebastian Reichel
> <[email protected]>; Sascha Hauer <[email protected]>;
> Chanwoo Choi <[email protected]>
> Subject: [PATCH] PM / devfreq: rockchip-dfi: Add perf support
>
> The DFI is a unit which is suitable for measuring DDR utilization, but so
> far it could only be used as an event driver for the DDR frequency scaling
> driver. This adds perf support to the DFI driver.
>
> Usage with the 'perf' tool can look like:
>
> perf stat -a -e rockchip_ddr/cycles/,\
> rockchip_ddr/read-bytes/,\
> rockchip_ddr/write-bytes/,\
> rockchip_ddr/bytes/ sleep 1
>
> Performance counter stats for 'system wide':
>
> 1582524826 rockchip_ddr/cycles/
> 1802.25 MB rockchip_ddr/read-bytes/
> 1793.72 MB rockchip_ddr/write-bytes/
> 3595.90 MB rockchip_ddr/bytes/
>
> 1.014369709 seconds time elapsed
>
> perf support has been tested on a RK3568 and a RK3399, the latter with
> dual channel DDR.
>
> Reviewed-by: Sebastian Reichel <[email protected]>
> Acked-by: Chanwoo Choi <[email protected]>
> Signed-off-by: Sascha Hauer <[email protected]>
> ---
>
> Notes:
> Changes since v8:
> - Move rockchip_ddr_perf_counters_add() inside #ifdef
> CONFIG_PERF_EVENTS
> to avoid unused function warning with CONFIG_PERF_EVENTS disabled
>
> Changes since v7:
> - rename variable 'c' to 'count'
>
> Changes since v5:
> - Add missing initialization of &dfi->last_perf_count
>
> Changes since v4:
>
> - use __stringify to ensure event type definitions and event numbers
> in sysfs are consistent
> - only use 64bit values in structs holding counters
> - support monitoring individual DDR channels
> - fix return value in rockchip_ddr_perf_event_init(): -EOPNOTSUPP ->
-
> EINVAL
> - check for invalid event->attr.config values
> - start hrtimer to trigger in one second, not immediately
> - use devm_add_action_or_reset()
> - add suppress_bind_attrs
> - enable DDRMON during probe when perf is enabled
> - use a seqlock to protect perf reading the counters from the hrtimer
> callback modifying them
>
> drivers/devfreq/event/rockchip-dfi.c | 440 ++++++++++++++++++++++++++-
> include/soc/rockchip/rk3399_grf.h | 2 +
> include/soc/rockchip/rk3568_grf.h | 1 +
> 3 files changed, 438 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/devfreq/event/rockchip-dfi.c
> b/drivers/devfreq/event/rockchip-dfi.c
> index 3d5c6d737ccd9..a7d7b61518fec 100644
> --- a/drivers/devfreq/event/rockchip-dfi.c
> +++ b/drivers/devfreq/event/rockchip-dfi.c
> @@ -16,10 +16,12 @@
> #include <linux/regmap.h>
> #include <linux/slab.h>
> #include <linux/list.h>
> +#include <linux/seqlock.h>
> #include <linux/of.h>
> #include <linux/of_device.h>
> #include <linux/bitfield.h>
> #include <linux/bits.h>
> +#include <linux/perf_event.h>
>
> #include <soc/rockchip/rockchip_grf.h>
> #include <soc/rockchip/rk3399_grf.h>
> @@ -41,19 +43,39 @@
> DDRMON_CTRL_LPDDR4 | \
> DDRMON_CTRL_LPDDR23)
>
> +#define DDRMON_CH0_WR_NUM 0x20
> +#define DDRMON_CH0_RD_NUM 0x24
> #define DDRMON_CH0_COUNT_NUM 0x28
> #define DDRMON_CH0_DFI_ACCESS_NUM 0x2c
> #define DDRMON_CH1_COUNT_NUM 0x3c
> #define DDRMON_CH1_DFI_ACCESS_NUM 0x40
>
> +#define PERF_EVENT_CYCLES 0x0
> +#define PERF_EVENT_READ_BYTES 0x1
> +#define PERF_EVENT_WRITE_BYTES 0x2
> +#define PERF_EVENT_READ_BYTES0 0x3
> +#define PERF_EVENT_WRITE_BYTES0 0x4
> +#define PERF_EVENT_READ_BYTES1 0x5
> +#define PERF_EVENT_WRITE_BYTES1 0x6
> +#define PERF_EVENT_READ_BYTES2 0x7
> +#define PERF_EVENT_WRITE_BYTES2 0x8
> +#define PERF_EVENT_READ_BYTES3 0x9
> +#define PERF_EVENT_WRITE_BYTES3 0xa
> +#define PERF_EVENT_BYTES 0xb
> +#define PERF_ACCESS_TYPE_MAX 0xc
> +
> /**
> * struct dmc_count_channel - structure to hold counter values from the
> DDR controller
> * @access: Number of read and write accesses
> * @clock_cycles: DDR clock cycles
> + * @read_access: number of read accesses
> + * @write_acccess: number of write accesses
Need to change it to 'write_access' from 'write_acccess'.
When I merge it, I fix it by myself.
And,
Applied it with "Acked-by: Heiko Stuebner <[email protected]>"
according to https://lore.kernel.org/all/27832786.gRfpFWEtPU@diego/.
If you have other opinion, please let me know.
Best Regards,
Chanwoo Choi
> -----Original Message-----
> From: Sascha Hauer <[email protected]>
> Sent: Wednesday, October 18, 2023 3:17 PM
> To: [email protected]
> Cc: [email protected]; [email protected];
> [email protected]; Heiko Stuebner <[email protected]>; Chanwoo Choi
> <[email protected]>; Kyungmin Park <[email protected]>; MyungJoo
> Ham <[email protected]>; Will Deacon <[email protected]>; Mark
> Rutland <[email protected]>; [email protected]; Michael Riesch
> <[email protected]>; Robin Murphy <[email protected]>;
> Vincent Legoll <[email protected]>; Rob Herring
> <[email protected]>; Krzysztof Kozlowski
> <[email protected]>; Conor Dooley <[email protected]>;
> [email protected]; Sebastian Reichel
> <[email protected]>; Sascha Hauer <[email protected]>;
> Rob Herring <[email protected]>; Chanwoo Choi <[email protected]>
> Subject: [PATCH v8 20/26] dt-bindings: devfreq: event: convert Rockchip
> DFI binding to yaml
>
> Convert the Rockchip DFI binding to yaml.
>
> Reviewed-by: Rob Herring <[email protected]>
> Reviewed-by: Sebastian Reichel <[email protected]>
> Acked-by: Chanwoo Choi <[email protected]>
> Signed-off-by: Sascha Hauer <[email protected]>
> ---
>
> Notes:
> Changes since v4:
> - Revert to state of v3 (changes were lost in v4)
>
> .../bindings/devfreq/event/rockchip,dfi.yaml | 61 +++++++++++++++++++
> .../bindings/devfreq/event/rockchip-dfi.txt | 18 ------
> .../rockchip,rk3399-dmc.yaml | 2 +-
> 3 files changed, 62 insertions(+), 19 deletions(-) create mode 100644
> Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml
> delete mode 100644
> Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt
>
> diff --git
> a/Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml
> b/Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml
> new file mode 100644
> index 0000000000000..7a82f6ae0701e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml
> @@ -0,0 +1,61 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> +---
> +$id:
> +https://protect2.fireeye.com/v1/url?k=33df13d2-525406e4-33de989d-000bab
> +ff9b5d-4b7a223f95f3c587&q=1&e=ef8cc89e-5dd5-4fbc-9f53-24c072471908&u=ht
> +tp%3A%2F%2Fdevicetree.org%2Fschemas%2Fdevfreq%2Fevent%2Frockchip%2Cdfi.
> +yaml%23
> +$schema:
> +https://protect2.fireeye.com/v1/url?k=01ded479-6055c14f-01df5f36-000bab
> +ff9b5d-e828a5719f87a6ff&q=1&e=ef8cc89e-5dd5-4fbc-9f53-24c072471908&u=ht
> +tp%3A%2F%2Fdevicetree.org%2Fmeta-schemas%2Fcore.yaml%23
> +
> +title: Rockchip DFI
> +
> +maintainers:
> + - Sascha Hauer <[email protected]>
> +
> +properties:
> + compatible:
> + enum:
> + - rockchip,rk3399-dfi
> +
> + clocks:
> + maxItems: 1
> +
> + clock-names:
> + items:
> + - const: pclk_ddr_mon
> +
> + interrupts:
> + maxItems: 1
> +
> + reg:
> + maxItems: 1
> +
> + rockchip,pmu:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description:
> + Phandle to the syscon managing the "PMU general register files".
> +
> +required:
> + - compatible
> + - clocks
> + - clock-names
> + - interrupts
> + - reg
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/clock/rk3308-cru.h>
> +
> + bus {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + dfi: dfi@ff630000 {
> + compatible = "rockchip,rk3399-dfi";
> + reg = <0x00 0xff630000 0x00 0x4000>;
> + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>;
> + rockchip,pmu = <&pmugrf>;
> + clocks = <&cru PCLK_DDR_MON>;
> + clock-names = "pclk_ddr_mon";
> + };
> + };
> diff --git a/Documentation/devicetree/bindings/devfreq/event/rockchip-
> dfi.txt b/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt
> deleted file mode 100644
> index 148191b0fc158..0000000000000
> --- a/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt
> +++ /dev/null
> @@ -1,18 +0,0 @@
> -
> -* Rockchip rk3399 DFI device
> -
> -Required properties:
> -- compatible: Must be "rockchip,rk3399-dfi".
> -- reg: physical base address of each DFI and length of memory mapped
> region
> -- rockchip,pmu: phandle to the syscon managing the "pmu general register
> files"
> -- clocks: phandles for clock specified in "clock-names" property
> -- clock-names : the name of clock used by the DFI, must be
"pclk_ddr_mon";
> -
> -Example:
> - dfi: dfi@ff630000 {
> - compatible = "rockchip,rk3399-dfi";
> - reg = <0x00 0xff630000 0x00 0x4000>;
> - rockchip,pmu = <&pmugrf>;
> - clocks = <&cru PCLK_DDR_MON>;
> - clock-names = "pclk_ddr_mon";
> - };
> diff --git a/Documentation/devicetree/bindings/memory-
> controllers/rockchip,rk3399-dmc.yaml
> b/Documentation/devicetree/bindings/memory-controllers/rockchip,rk3399-
> dmc.yaml
> index 4e4af3cfc0fe4..1f58ee99be280 100644
> --- a/Documentation/devicetree/bindings/memory-
> controllers/rockchip,rk3399-dmc.yaml
> +++ b/Documentation/devicetree/bindings/memory-controllers/rockchip,rk33
> +++ 99-dmc.yaml
> @@ -18,7 +18,7 @@ properties:
> $ref: /schemas/types.yaml#/definitions/phandle
> description:
> Node to get DDR loading. Refer to
> - Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt.
> + Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml.
>
> clocks:
> maxItems: 1
> --
> 2.39.2
Applied it. Thanks
Best Regards,
Chanwoo Choi
> -----Original Message-----
> From: Chanwoo Choi <[email protected]>
> Sent: Thursday, October 19, 2023 12:12 AM
> To: Sascha Hauer <[email protected]>; linux-
> [email protected]
> Cc: [email protected]; [email protected];
> [email protected]; Heiko Stuebner <[email protected]>; Kyungmin Park
> <[email protected]>; MyungJoo Ham <[email protected]>; Will
> Deacon <[email protected]>; Mark Rutland <[email protected]>;
> [email protected]; Michael Riesch <[email protected]>;
> Robin Murphy <[email protected]>; Vincent Legoll
> <[email protected]>; Rob Herring <[email protected]>; Krzysztof
> Kozlowski <[email protected]>; Conor Dooley
> <[email protected]>; [email protected]; Sebastian Reichel
> <[email protected]>; Jonathan Cameron
> <[email protected]>
> Subject: Re: [PATCH v8 19/26] PM / devfreq: rockchip-dfi: add support for
> RK3588
>
> On 23. 10. 18. 15:17, Sascha Hauer wrote:
> > Add support for the RK3588 to the driver. The RK3588 has four DDR
> > channels with a register stride of 0x4000 between the channel
> > registers, also it has a DDRMON_CTRL register per channel.
> >
> > Reviewed-by: Jonathan Cameron <[email protected]>
> > Reviewed-by: Sebastian Reichel <[email protected]>
> > Signed-off-by: Sascha Hauer <[email protected]>
> > ---
> > drivers/devfreq/event/rockchip-dfi.c | 36 +++++++++++++++++++++++++++-
> > include/soc/rockchip/rk3588_grf.h | 18 ++++++++++++++
> > 2 files changed, 53 insertions(+), 1 deletion(-) create mode 100644
> > include/soc/rockchip/rk3588_grf.h
> >
> > diff --git a/drivers/devfreq/event/rockchip-dfi.c
> > b/drivers/devfreq/event/rockchip-dfi.c
> > index bf38829a2a4af..794f36e7eebd1 100644
> > --- a/drivers/devfreq/event/rockchip-dfi.c
> > +++ b/drivers/devfreq/event/rockchip-dfi.c
> > @@ -26,8 +26,9 @@
> > #include <soc/rockchip/rockchip_grf.h> #include
> > <soc/rockchip/rk3399_grf.h> #include <soc/rockchip/rk3568_grf.h>
> > +#include <soc/rockchip/rk3588_grf.h>
> >
> > -#define DMC_MAX_CHANNELS 2
> > +#define DMC_MAX_CHANNELS 4
> >
> > #define HIWORD_UPDATE(val, mask) ((val) | (mask) << 16)
> >
> > @@ -723,9 +724,42 @@ static int rk3568_dfi_init(struct rockchip_dfi *dfi)
> > return 0;
> > };
> >
> > +static int rk3588_dfi_init(struct rockchip_dfi *dfi) {
> > + struct regmap *regmap_pmu = dfi->regmap_pmu;
> > + u32 reg2, reg3, reg4;
> > +
> > + regmap_read(regmap_pmu, RK3588_PMUGRF_OS_REG2, ®2);
> > + regmap_read(regmap_pmu, RK3588_PMUGRF_OS_REG3, ®3);
> > + regmap_read(regmap_pmu, RK3588_PMUGRF_OS_REG4, ®4);
> > +
> > + /* lower 3 bits of the DDR type */
> > + dfi->ddr_type = FIELD_GET(RK3588_PMUGRF_OS_REG2_DRAMTYPE_INFO,
> > +reg2);
> > +
> > + /*
> > + * For version three and higher the upper two bits of the DDR type
> are
> > + * in RK3588_PMUGRF_OS_REG3
> > + */
> > + if (FIELD_GET(RK3588_PMUGRF_OS_REG3_SYSREG_VERSION, reg3) >= 0x3)
> > + dfi->ddr_type |=
> FIELD_GET(RK3588_PMUGRF_OS_REG3_DRAMTYPE_INFO_V3,
> > +reg3) << 3;
> > +
> > + dfi->buswidth[0] = FIELD_GET(RK3588_PMUGRF_OS_REG2_BW_CH0, reg2) ==
> 0 ? 4 : 2;
> > + dfi->buswidth[1] = FIELD_GET(RK3588_PMUGRF_OS_REG2_BW_CH1, reg2) ==
> 0 ? 4 : 2;
> > + dfi->buswidth[2] = FIELD_GET(RK3568_PMUGRF_OS_REG2_BW_CH0, reg4) ==
> 0 ? 4 : 2;
> > + dfi->buswidth[3] = FIELD_GET(RK3588_PMUGRF_OS_REG2_BW_CH1, reg4) ==
> 0 ? 4 : 2;
> > + dfi->channel_mask = FIELD_GET(RK3588_PMUGRF_OS_REG2_CH_INFO, reg2)
> |
> > + FIELD_GET(RK3588_PMUGRF_OS_REG2_CH_INFO, reg4) << 2;
> > + dfi->max_channels = 4;
> > +
> > + dfi->ddrmon_stride = 0x4000;
> > +
> > + return 0;
> > +};
> > +
> > static const struct of_device_id rockchip_dfi_id_match[] = {
> > { .compatible = "rockchip,rk3399-dfi", .data = rk3399_dfi_init },
> > { .compatible = "rockchip,rk3568-dfi", .data = rk3568_dfi_init },
> > + { .compatible = "rockchip,rk3588-dfi", .data = rk3588_dfi_init },
> > { },
> > };
> >
> > diff --git a/include/soc/rockchip/rk3588_grf.h
> > b/include/soc/rockchip/rk3588_grf.h
> > new file mode 100644
> > index 0000000000000..630b35a550640
> > --- /dev/null
> > +++ b/include/soc/rockchip/rk3588_grf.h
> > @@ -0,0 +1,18 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __SOC_RK3588_GRF_H
> > +#define __SOC_RK3588_GRF_H
> > +
> > +#define RK3588_PMUGRF_OS_REG2 0x208
> > +#define RK3588_PMUGRF_OS_REG2_DRAMTYPE_INFO GENMASK(15, 13)
> > +#define RK3588_PMUGRF_OS_REG2_BW_CH0 GENMASK(3, 2)
> > +#define RK3588_PMUGRF_OS_REG2_BW_CH1 GENMASK(19, 18)
> > +#define RK3588_PMUGRF_OS_REG2_CH_INFO GENMASK(29, 28)
> > +
> > +#define RK3588_PMUGRF_OS_REG3 0x20c
> > +#define RK3588_PMUGRF_OS_REG3_DRAMTYPE_INFO_V3 GENMASK(13, 12)
> > +#define RK3588_PMUGRF_OS_REG3_SYSREG_VERSION GENMASK(31, 28)
> > +
> > +#define RK3588_PMUGRF_OS_REG4 0x210
> > +#define RK3588_PMUGRF_OS_REG5 0x214
> > +
> > +#endif /* __SOC_RK3588_GRF_H */
>
> Acked-by: Chanwoo Choi <[email protected]>
>
> --
> Best Regards,
> Samsung Electronics
> Chanwoo Choi
Applied it. Thanks
Best Regards,
Chanwoo Choi
> -----Original Message-----
> From: Chanwoo Choi <[email protected]>
> Sent: Thursday, October 19, 2023 12:12 AM
> To: Sascha Hauer <[email protected]>; linux-
> [email protected]
> Cc: [email protected]; [email protected];
> [email protected]; Heiko Stuebner <[email protected]>; Kyungmin Park
> <[email protected]>; MyungJoo Ham <[email protected]>; Will
> Deacon <[email protected]>; Mark Rutland <[email protected]>;
> [email protected]; Michael Riesch <[email protected]>;
> Robin Murphy <[email protected]>; Vincent Legoll
> <[email protected]>; Rob Herring <[email protected]>; Krzysztof
> Kozlowski <[email protected]>; Conor Dooley
> <[email protected]>; [email protected]; Sebastian Reichel
> <[email protected]>; Jonathan Cameron
> <[email protected]>
> Subject: Re: [PATCH v8 19/26] PM / devfreq: rockchip-dfi: add support for
> RK3588
>
> On 23. 10. 18. 15:17, Sascha Hauer wrote:
> > Add support for the RK3588 to the driver. The RK3588 has four DDR
> > channels with a register stride of 0x4000 between the channel
> > registers, also it has a DDRMON_CTRL register per channel.
> >
> > Reviewed-by: Jonathan Cameron <[email protected]>
> > Reviewed-by: Sebastian Reichel <[email protected]>
> > Signed-off-by: Sascha Hauer <[email protected]>
> > ---
> > drivers/devfreq/event/rockchip-dfi.c | 36 +++++++++++++++++++++++++++-
> > include/soc/rockchip/rk3588_grf.h | 18 ++++++++++++++
> > 2 files changed, 53 insertions(+), 1 deletion(-) create mode 100644
> > include/soc/rockchip/rk3588_grf.h
> >
> > diff --git a/drivers/devfreq/event/rockchip-dfi.c
> > b/drivers/devfreq/event/rockchip-dfi.c
> > index bf38829a2a4af..794f36e7eebd1 100644
> > --- a/drivers/devfreq/event/rockchip-dfi.c
> > +++ b/drivers/devfreq/event/rockchip-dfi.c
> > @@ -26,8 +26,9 @@
> > #include <soc/rockchip/rockchip_grf.h> #include
> > <soc/rockchip/rk3399_grf.h> #include <soc/rockchip/rk3568_grf.h>
> > +#include <soc/rockchip/rk3588_grf.h>
> >
> > -#define DMC_MAX_CHANNELS 2
> > +#define DMC_MAX_CHANNELS 4
> >
> > #define HIWORD_UPDATE(val, mask) ((val) | (mask) << 16)
> >
> > @@ -723,9 +724,42 @@ static int rk3568_dfi_init(struct rockchip_dfi *dfi)
> > return 0;
> > };
> >
> > +static int rk3588_dfi_init(struct rockchip_dfi *dfi) {
> > + struct regmap *regmap_pmu = dfi->regmap_pmu;
> > + u32 reg2, reg3, reg4;
> > +
> > + regmap_read(regmap_pmu, RK3588_PMUGRF_OS_REG2, ®2);
> > + regmap_read(regmap_pmu, RK3588_PMUGRF_OS_REG3, ®3);
> > + regmap_read(regmap_pmu, RK3588_PMUGRF_OS_REG4, ®4);
> > +
> > + /* lower 3 bits of the DDR type */
> > + dfi->ddr_type = FIELD_GET(RK3588_PMUGRF_OS_REG2_DRAMTYPE_INFO,
> > +reg2);
> > +
> > + /*
> > + * For version three and higher the upper two bits of the DDR type
> are
> > + * in RK3588_PMUGRF_OS_REG3
> > + */
> > + if (FIELD_GET(RK3588_PMUGRF_OS_REG3_SYSREG_VERSION, reg3) >= 0x3)
> > + dfi->ddr_type |=
> FIELD_GET(RK3588_PMUGRF_OS_REG3_DRAMTYPE_INFO_V3,
> > +reg3) << 3;
> > +
> > + dfi->buswidth[0] = FIELD_GET(RK3588_PMUGRF_OS_REG2_BW_CH0, reg2) ==
> 0 ? 4 : 2;
> > + dfi->buswidth[1] = FIELD_GET(RK3588_PMUGRF_OS_REG2_BW_CH1, reg2) ==
> 0 ? 4 : 2;
> > + dfi->buswidth[2] = FIELD_GET(RK3568_PMUGRF_OS_REG2_BW_CH0, reg4) ==
> 0 ? 4 : 2;
> > + dfi->buswidth[3] = FIELD_GET(RK3588_PMUGRF_OS_REG2_BW_CH1, reg4) ==
> 0 ? 4 : 2;
> > + dfi->channel_mask = FIELD_GET(RK3588_PMUGRF_OS_REG2_CH_INFO, reg2)
> |
> > + FIELD_GET(RK3588_PMUGRF_OS_REG2_CH_INFO, reg4) << 2;
> > + dfi->max_channels = 4;
> > +
> > + dfi->ddrmon_stride = 0x4000;
> > +
> > + return 0;
> > +};
> > +
> > static const struct of_device_id rockchip_dfi_id_match[] = {
> > { .compatible = "rockchip,rk3399-dfi", .data = rk3399_dfi_init },
> > { .compatible = "rockchip,rk3568-dfi", .data = rk3568_dfi_init },
> > + { .compatible = "rockchip,rk3588-dfi", .data = rk3588_dfi_init },
> > { },
> > };
> >
> > diff --git a/include/soc/rockchip/rk3588_grf.h
> > b/include/soc/rockchip/rk3588_grf.h
> > new file mode 100644
> > index 0000000000000..630b35a550640
> > --- /dev/null
> > +++ b/include/soc/rockchip/rk3588_grf.h
> > @@ -0,0 +1,18 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */ #ifndef __SOC_RK3588_GRF_H
> > +#define __SOC_RK3588_GRF_H
> > +
> > +#define RK3588_PMUGRF_OS_REG2 0x208
> > +#define RK3588_PMUGRF_OS_REG2_DRAMTYPE_INFO GENMASK(15, 13)
> > +#define RK3588_PMUGRF_OS_REG2_BW_CH0 GENMASK(3, 2)
> > +#define RK3588_PMUGRF_OS_REG2_BW_CH1 GENMASK(19, 18)
> > +#define RK3588_PMUGRF_OS_REG2_CH_INFO GENMASK(29, 28)
> > +
> > +#define RK3588_PMUGRF_OS_REG3 0x20c
> > +#define RK3588_PMUGRF_OS_REG3_DRAMTYPE_INFO_V3 GENMASK(13, 12)
> > +#define RK3588_PMUGRF_OS_REG3_SYSREG_VERSION GENMASK(31, 28)
> > +
> > +#define RK3588_PMUGRF_OS_REG4 0x210
> > +#define RK3588_PMUGRF_OS_REG5 0x214
> > +
> > +#endif /* __SOC_RK3588_GRF_H */
>
> Acked-by: Chanwoo Choi <[email protected]>
>
> --
> Best Regards,
> Samsung Electronics
> Chanwoo Choi
Applied it. Thanks
Best Regards,
Chanwoo Choi
On Wed, 18 Oct 2023 08:16:48 +0200, Sascha Hauer wrote:
> This series integrates the recent review feedback from Chanwoo Choi to
> v7.
>
> Chanwoo, I am sending the full patchset again for people to try this
> series. You said that you applied 1-5 already, so please start picking
> from 6/26.
>
> [...]
Applied, thanks!
[24/26] arm64: dts: rockchip: rk3399: Enable DFI
commit: f57ef11ec63c17201b27569fbfb58801c227137d
[25/26] arm64: dts: rockchip: rk356x: Add DFI
commit: 085be8875ca8a087e3cc102893f384894962c87e
[26/26] arm64: dts: rockchip: rk3588s: Add DFI
commit: 5a6976b1040a2f99ab84eddbfa7cd072ac5d10fc
Best regards,
--
Heiko Stuebner <[email protected]>