On Tue, 2006-03-07 at 19:00 +0000, Linux Kernel Mailing List wrote:
> commit 72f2afb8a6858edd9335cd158eb21053a0c2c39a
> tree 1cc6884bf4e48822423d23d68d7b2699cd2e68fd
> parent d11d9b2dd2c43dd99a491df8a83ae28401db0044
> author Michael Chan <[email protected]> Tue, 07 Mar 2006 11:28:35 -0800
> committer David S. Miller <[email protected]> Tue, 07 Mar 2006 11:28:35 -0800
>
> [TG3]: Add DMA address workaround
>
> Add DMA workaround for chips that do not support full 64-bit DMA
> addresses.
>
> 5714, 5715, and 5780 chips only support DMA addresses less than 40
> bits. On 64-bit systems with IOMMU, set the dma_mask to 40-bit so
> that pci_map_xxx() calls will map the DMA address below 40 bits if
> necessary. On 64-bit systems without IOMMU, set the dma_mask to
> 64-bit and check for DMA addresses exceeding the limit in
> tg3_start_xmit().
>
> 5788 only supports 32-bit DMA so need to set the mask appropriately
> also.
I suppose that means I need to update the ppc64 iommu code to actually
honor the DMA mask when allocating ;) That will be easy for "dumb"
iommu's like the G5 but might be a bit more tricky with pSeries.
Anton, Paul, we have no control on the DMA ranges allocated to each phb
in the system, do we know if they go beyond 32 bits ? (And if yes,
beyond 40 bits)
Ben.
On Wed, 2006-03-08 at 10:21 +1100, Benjamin Herrenschmidt wrote:
>
> I suppose that means I need to update the ppc64 iommu code to actually
> honor the DMA mask when allocating ;) That will be easy for "dumb"
> iommu's like the G5 but might be a bit more tricky with pSeries.
>
> Anton, Paul, we have no control on the DMA ranges allocated to each phb
> in the system, do we know if they go beyond 32 bits ? (And if yes,
> beyond 40 bits)
>
So how does powerpc handle 32-bit PCI devices that don't support dual
address cycles? Such devices will set the dma_mask to 32-bit. Shouldn't
40-bit be handled in a similar way?
On Tue, 2006-03-07 at 14:18 -0800, Michael Chan wrote:
> So how does powerpc handle 32-bit PCI devices that don't support dual
> address cycles? Such devices will set the dma_mask to 32-bit. Shouldn't
> 40-bit be handled in a similar way?
I've double checked that our current DMA code always stays below 32
bits. I was more wondering about some not-yet there stuff but it looks
like we are safe on that side too.
One thing i've been looking into doing with the iommu code is to make it
capable of respecting the DMA mask precisely (by constraining the
allocator to any arbitrary mask, not just 32 vs. 64 bits) to make it
more useful for bcm44xx and 43xx... but that's a different story.
Ben.