Rohit Seth wrote:
> Hi Nick,
>
> -----Original Message-----
> From: Nick Piggin [mailto:[email protected]]
> Sent: Friday, April 27, 2007 11:03 PM
> To: Hugh Dickins
> Cc: [email protected]; Mike Stroyan; Andrew Morton; Luck, Tony;
> [email protected]; [email protected]
> Subject: Re: Fw: [PATCH] ia64: race flushing icache in do_no_page path
>
> Hugh Dickins wrote:
>
>>On Sat, 28 Apr 2007, Nick Piggin wrote:
>>
>>
>>>OIC, you need a virtual address to evict the icache, so you can't
>>>flush at flush_dcache time? Or does ia64 have an instruction to flush
>>>the whole icache? (it would be worth testing, to see how much
>>>performance suffers).
>>
>>
>>I'm puzzled by that remark: the ia64 flush_icache_range always has a
>>virtual address, it uses the kernel virtual address; it takes no
>>interest in whether there's a user virtual address.
>
>
>>I _think_ what it is doing is actually flushing dcache lines dirtied
>>via the kernel virtual address (yes, I think flush_icache
>>in lazy_mmu_prot_update is actually just flushing the dcache, but
>>I could be wrong? [*]).
>
>
> It is invalidating any entries (containing same physical address) in both I
> and D caches. Any dirty lines in D cache are written back to memory before
> getting invalidated (ofcourse).
OK. (should it be issuing both fc and fc.i to be robust in case a
new implementation doesn't flush the dcache with fc.i?)
>>There are supposedly no icache lines at that point[**]:
>
>
> For this bug to trigger there has to be a (stale) entry in icache containing
> the old contents of a page that just got updated by kernel as explicit
> copying of data (DMAs are coherent on ia64, meaning if a device were to
> write to memory then architecture guarnatees that both I and D caches are
> invalidated).
So if we have a dirty dcache line for a given physical address,
it will _always_ be the case that a subsequent icache load will
find that dirty data?
... thanks for bearing with me ;)
--
SUSE Labs, Novell Inc.
On Tue, 2007-05-01 at 21:47 +1000, Nick Piggin wrote:
> Rohit Seth wrote:
> >
> >
> > It is invalidating any entries (containing same physical address) in both I
> > and D caches. Any dirty lines in D cache are written back to memory before
> > getting invalidated (ofcourse).
>
> OK. (should it be issuing both fc and fc.i to be robust in case a
> new implementation doesn't flush the dcache with fc.i?)
>
For the Itanium case specifically, you only want to invalidate a stale
icache line. Once that is done, next time icache will pick the correct
updated contents.
>
> >>There are supposedly no icache lines at that point[**]:
> >
> >
> > For this bug to trigger there has to be a (stale) entry in icache containing
> > the old contents of a page that just got updated by kernel as explicit
> > copying of data (DMAs are coherent on ia64, meaning if a device were to
> > write to memory then architecture guarnatees that both I and D caches are
> > invalidated).
>
> So if we have a dirty dcache line for a given physical address,
> it will _always_ be the case that a subsequent icache load will
> find that dirty data?
yes for ia64.
-rohit