2009-07-01 12:20:20

by Jaswinder Singh Rajput

Subject: [PATCH -tip RESEND] x86: msr-index.h remove double declaration of MSR_P6_EVNTSEL0 and MSR_P6_EVNTSEL1

MSR_P6_EVNTSEL0 and MSR_P6_EVNTSEL1 is already declared in msr-index.h.

Signed-off-by: Jaswinder Singh Rajput <[email protected]>
---
arch/x86/include/asm/msr-index.h | 4 ----
1 files changed, 0 insertions(+), 4 deletions(-)

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 4d58d04..35ec37a 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -239,10 +239,6 @@
#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << 38)
#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << 39)

-/* Intel Model 6 */
-#define MSR_P6_EVNTSEL0 0x00000186
-#define MSR_P6_EVNTSEL1 0x00000187
-
/* P4/Xeon+ specific */
#define MSR_IA32_MCG_EAX 0x00000180
#define MSR_IA32_MCG_EBX 0x00000181
--
1.6.0.6

2009-07-01 14:01:19

by Jaswinder Singh Rajput

Subject: [tip:x86/urgent] x86: Remove double declaration of MSR_P6_EVNTSEL0 and MSR_P6_EVNTSEL1

Commit-ID: 44973998a111dfda09b952aa0f27cad326a97793
Gitweb: http://git.kernel.org/tip/44973998a111dfda09b952aa0f27cad326a97793
Author: Jaswinder Singh Rajput <[email protected]>
AuthorDate: Wed, 1 Jul 2009 17:49:38 +0530
Committer: Ingo Molnar <[email protected]>
CommitDate: Wed, 1 Jul 2009 15:23:43 +0200

x86: Remove double declaration of MSR_P6_EVNTSEL0 and MSR_P6_EVNTSEL1

MSR_P6_EVNTSEL0 and MSR_P6_EVNTSEL1 is already declared in msr-index.h.

Signed-off-by: Jaswinder Singh Rajput <[email protected]>
LKML-Reference: <[email protected]>
Signed-off-by: Ingo Molnar <[email protected]>


---
arch/x86/include/asm/msr-index.h | 4 ----
1 files changed, 0 insertions(+), 4 deletions(-)

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 1692fb5..6be7fc2 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -246,10 +246,6 @@
#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << 38)
#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << 39)

-/* Intel Model 6 */
-#define MSR_P6_EVNTSEL0 0x00000186
-#define MSR_P6_EVNTSEL1 0x00000187
-
/* P4/Xeon+ specific */
#define MSR_IA32_MCG_EAX 0x00000180
#define MSR_IA32_MCG_EBX 0x00000181