Hi,
I've respun this patch series to move the DEBUG_LL 32-bit helpers into
debug-macro.S like mach-davinci does and include the basic clk stuff so
that we can build with drivers that want CLK support.
This patch series takes us to a login console over serial on both PC3X2
and PC3X3 devices on the PC7302 board booted with NOR flash. I plan on
adding support for the next generation of soc, PM, cpufreq etc at a
later date once these patches are merged but figured it would be good to
start with a nice stable base.
Any feedback would be very much appreciated!
Thanks,
Jamie Iles (5):
picoxcell: support for Picochip picoXcell SoC
picoxcell: support for the common system timers
picoxcell: common SoC peripheral support
picoxcell: basic clk infrastructure
picoxcell: support for the PC7302 development board
arch/arm/Kconfig | 14 ++
arch/arm/Makefile | 1 +
arch/arm/mach-picoxcell/Kconfig | 13 ++
arch/arm/mach-picoxcell/Makefile | 5 +
arch/arm/mach-picoxcell/Makefile.boot | 3 +
arch/arm/mach-picoxcell/axi2cfg.c | 36 ++++
arch/arm/mach-picoxcell/board_pc7302.c | 109 ++++++++++
arch/arm/mach-picoxcell/clk.c | 83 ++++++++
arch/arm/mach-picoxcell/devices.c | 122 +++++++++++
arch/arm/mach-picoxcell/include/mach/clkdev.h | 70 ++++++
arch/arm/mach-picoxcell/include/mach/debug-macro.S | 39 ++++
arch/arm/mach-picoxcell/include/mach/entry-macro.S | 19 ++
arch/arm/mach-picoxcell/include/mach/hardware.h | 29 +++
arch/arm/mach-picoxcell/include/mach/io.h | 38 ++++
arch/arm/mach-picoxcell/include/mach/irqs.h | 89 ++++++++
arch/arm/mach-picoxcell/include/mach/memory.h | 27 +++
.../include/mach/picoxcell/axi2cfg.h | 122 +++++++++++
.../mach-picoxcell/include/mach/picoxcell/gpio.h | 48 +++++
.../include/mach/picoxcell/picoxcell.h | 62 ++++++
.../mach-picoxcell/include/mach/picoxcell/timer.h | 37 ++++
.../mach-picoxcell/include/mach/picoxcell/wdog.h | 43 ++++
arch/arm/mach-picoxcell/include/mach/platform.h | 27 +++
arch/arm/mach-picoxcell/include/mach/system.h | 51 +++++
arch/arm/mach-picoxcell/include/mach/timex.h | 26 +++
arch/arm/mach-picoxcell/include/mach/uncompress.h | 60 ++++++
arch/arm/mach-picoxcell/include/mach/vmalloc.h | 18 ++
arch/arm/mach-picoxcell/io.c | 49 +++++
arch/arm/mach-picoxcell/picoxcell_core.c | 107 ++++++++++
arch/arm/mach-picoxcell/picoxcell_core.h | 25 +++
arch/arm/mach-picoxcell/soc.h | 32 +++
arch/arm/mach-picoxcell/time.c | 222 ++++++++++++++++++++
31 files changed, 1626 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-picoxcell/Kconfig
create mode 100644 arch/arm/mach-picoxcell/Makefile
create mode 100644 arch/arm/mach-picoxcell/Makefile.boot
create mode 100644 arch/arm/mach-picoxcell/axi2cfg.c
create mode 100644 arch/arm/mach-picoxcell/board_pc7302.c
create mode 100644 arch/arm/mach-picoxcell/clk.c
create mode 100644 arch/arm/mach-picoxcell/devices.c
create mode 100644 arch/arm/mach-picoxcell/include/mach/clkdev.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/debug-macro.S
create mode 100644 arch/arm/mach-picoxcell/include/mach/entry-macro.S
create mode 100644 arch/arm/mach-picoxcell/include/mach/hardware.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/io.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/irqs.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/memory.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/picoxcell/axi2cfg.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/picoxcell/gpio.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/picoxcell/picoxcell.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/picoxcell/timer.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/picoxcell/wdog.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/platform.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/system.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/timex.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/uncompress.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/vmalloc.h
create mode 100644 arch/arm/mach-picoxcell/io.c
create mode 100644 arch/arm/mach-picoxcell/picoxcell_core.c
create mode 100644 arch/arm/mach-picoxcell/picoxcell_core.h
create mode 100644 arch/arm/mach-picoxcell/soc.h
create mode 100644 arch/arm/mach-picoxcell/time.c
--
1.7.4
The picoXcell devices have 4 timers capable of generating interrupts
when they reach a predefined value and restarting and a freerunning RTC.
Use one of the interrupt capable timers as the clockevent_device and the
RTC for the clocksource and sched_clock().
v2:
- use clocksource_register_hz() and
clockevents_calc_mult_shift() rather than specifying .mult and
.shift.
v3:
- Incorporate feedback from RMK.
- Don't emulate oneshot mode in the timers, let the generic
clockevents layer do it.
- Provide a better sched_clock() based on plat-nomadik's.
- Convert to __raw_ io accessors.
v4:
- Use the fixed_sched_clock helpers for sched_clock()
implementation as provided by RMK and remove redunant use of
__init.
Signed-off-by: Jamie Iles <[email protected]>
---
arch/arm/mach-picoxcell/Makefile | 3 +-
arch/arm/mach-picoxcell/picoxcell_core.c | 1 +
arch/arm/mach-picoxcell/picoxcell_core.h | 3 +
arch/arm/mach-picoxcell/time.c | 222 ++++++++++++++++++++++++++++++
4 files changed, 228 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/mach-picoxcell/time.c
diff --git a/arch/arm/mach-picoxcell/Makefile b/arch/arm/mach-picoxcell/Makefile
index 6afe388..493ec0e 100644
--- a/arch/arm/mach-picoxcell/Makefile
+++ b/arch/arm/mach-picoxcell/Makefile
@@ -1 +1,2 @@
-obj-y := picoxcell_core.o io.o axi2cfg.o
+obj-y := picoxcell_core.o io.o axi2cfg.o \
+ time.o
diff --git a/arch/arm/mach-picoxcell/picoxcell_core.c b/arch/arm/mach-picoxcell/picoxcell_core.c
index a0db3fd..a54d981 100644
--- a/arch/arm/mach-picoxcell/picoxcell_core.c
+++ b/arch/arm/mach-picoxcell/picoxcell_core.c
@@ -97,6 +97,7 @@ static void report_chipinfo(void)
void __init picoxcell_init_early(void)
{
axi2cfg_init();
+ picoxcell_sched_clock_init();
}
void __init picoxcell_core_init(void)
diff --git a/arch/arm/mach-picoxcell/picoxcell_core.h b/arch/arm/mach-picoxcell/picoxcell_core.h
index 299c512..50cf842 100644
--- a/arch/arm/mach-picoxcell/picoxcell_core.h
+++ b/arch/arm/mach-picoxcell/picoxcell_core.h
@@ -13,10 +13,13 @@
#define __ASM_ARCH_PICOXCELL_CORE_H__
struct picoxcell_soc;
+struct sys_timer;
extern void picoxcell_init_early(void);
extern void picoxcell_core_init(void);
extern void picoxcell_init_irq(void);
extern void picoxcell_map_io(void);
+extern struct sys_timer picoxcell_sys_timer;
+extern void picoxcell_sched_clock_init(void);
#endif /* __ASM_ARCH_PICOXCELL_CORE_H__ */
diff --git a/arch/arm/mach-picoxcell/time.c b/arch/arm/mach-picoxcell/time.c
new file mode 100644
index 0000000..66fe86d
--- /dev/null
+++ b/arch/arm/mach-picoxcell/time.c
@@ -0,0 +1,222 @@
+/*
+ * Copyright (c) 2010 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * All enquiries to [email protected]
+ */
+#include <linux/clockchips.h>
+#include <linux/clocksource.h>
+#include <linux/cnt32_to_63.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+
+#include <asm/mach/time.h>
+#include <asm/sched_clock.h>
+
+#include <mach/hardware.h>
+
+#include "picoxcell_core.h"
+#include "soc.h"
+
+enum timer_id {
+ TIMER_ID_CLOCKEVENT,
+ TIMER_ID_CLOCKSOURCE,
+ NR_TIMERS,
+};
+
+struct timer_instance {
+ void __iomem *base;
+ struct irqaction irqaction;
+};
+
+/*
+ * We expect to have 2 timers - a freerunning one for the clock source and a
+ * periodic/oneshot one for the clock_event_device.
+ */
+static struct timer_instance timers[NR_TIMERS];
+
+static void timer_set_mode(enum clock_event_mode mode,
+ struct clock_event_device *clk)
+{
+ struct timer_instance *timer = &timers[TIMER_ID_CLOCKEVENT];
+ unsigned long load_count = DIV_ROUND_UP(CLOCK_TICK_RATE, HZ);
+
+ switch (mode) {
+ case CLOCK_EVT_MODE_PERIODIC:
+ /*
+ * By default, use the kernel tick rate. The reload value can
+ * be changed with the timer_set_next_event() function.
+ */
+ __raw_writel(load_count,
+ timer->base + TIMER_LOAD_COUNT_REG_OFFSET);
+ __raw_writel(TIMER_ENABLE | TIMER_MODE,
+ timer->base + TIMER_CONTROL_REG_OFFSET);
+ break;
+
+ case CLOCK_EVT_MODE_ONESHOT:
+ case CLOCK_EVT_MODE_UNUSED:
+ case CLOCK_EVT_MODE_SHUTDOWN:
+ default:
+ __raw_writel(0, timer->base + TIMER_CONTROL_REG_OFFSET);
+ break;
+ }
+}
+
+static int timer_set_next_event(unsigned long evt,
+ struct clock_event_device *clk)
+{
+ struct timer_instance *timer = &timers[TIMER_ID_CLOCKEVENT];
+
+ /* Disable the timer, write the new event then enable it. */
+ __raw_writel(0, timer->base + TIMER_CONTROL_REG_OFFSET);
+ __raw_writel(evt, timer->base + TIMER_LOAD_COUNT_REG_OFFSET);
+ __raw_writel(TIMER_ENABLE | TIMER_MODE,
+ timer->base + TIMER_CONTROL_REG_OFFSET);
+
+ return 0;
+}
+
+static struct clock_event_device clockevent_picoxcell = {
+ .features = CLOCK_EVT_FEAT_PERIODIC |
+ CLOCK_EVT_FEAT_ONESHOT,
+ .set_next_event = timer_set_next_event,
+ .set_mode = timer_set_mode,
+};
+
+static irqreturn_t timer_interrupt(int irq, void *dev_id)
+{
+ struct timer_instance *timer = &timers[TIMER_ID_CLOCKEVENT];
+
+ /* Clear the interrupt. */
+ __raw_readl(timer->base + TIMER_EOI_REG_OFFSET);
+
+ clockevent_picoxcell.event_handler(&clockevent_picoxcell);
+
+ return IRQ_HANDLED;
+}
+
+#define PICOXCELL_MIN_RANGE 4
+
+static void picoxcell_clockevent_init(struct picoxcell_soc *soc)
+{
+ struct timer_instance *inst = &timers[TIMER_ID_CLOCKEVENT];
+ const struct picoxcell_timer *timer = NULL;
+ int i;
+
+ for (i = 0; i < soc->nr_timers; ++i)
+ if (soc->timers[i].type == TIMER_TYPE_TIMER) {
+ timer = &soc->timers[i];
+ break;
+ }
+
+ BUG_ON(!timer);
+
+ /* Configure the interrupt for this timer. */
+ inst->irqaction.name = timer->name;
+ inst->irqaction.handler = timer_interrupt;
+ inst->irqaction.flags = IRQF_DISABLED | IRQF_TIMER;
+ inst->base = ioremap(timer->base, TIMER_SPACING);
+
+ clockevent_picoxcell.name = timer->name;
+ clockevents_calc_mult_shift(&clockevent_picoxcell, CLOCK_TICK_RATE,
+ PICOXCELL_MIN_RANGE);
+ clockevent_picoxcell.max_delta_ns =
+ clockevent_delta2ns(0xfffffffe, &clockevent_picoxcell);
+ clockevent_picoxcell.min_delta_ns = 50000;
+ clockevent_picoxcell.cpumask = cpumask_of(0);
+
+ /* Start with the timer disabled and the interrupt enabled. */
+ __raw_writel(0, inst->base + TIMER_CONTROL_REG_OFFSET);
+ setup_irq(timer->irq, &inst->irqaction);
+
+ clockevents_register_device(&clockevent_picoxcell);
+}
+
+static cycle_t picoxcell_rtc_get_cycles(struct clocksource *cs)
+{
+ struct timer_instance *inst = &timers[TIMER_ID_CLOCKSOURCE];
+
+ return __raw_readl(inst->base + RTCLK_CCV_REG_OFFSET);
+}
+
+static struct clocksource clocksource_picoxcell = {
+ .name = "rtc",
+ .rating = 300,
+ .read = picoxcell_rtc_get_cycles,
+ .mask = CLOCKSOURCE_MASK(32),
+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+static void picoxcell_clocksource_init(struct picoxcell_soc *soc)
+{
+ const struct picoxcell_timer *timer = NULL;
+ int i;
+
+ for (i = 0; i < soc->nr_timers; ++i)
+ if (soc->timers[i].type == TIMER_TYPE_RTC) {
+ timer = &soc->timers[i];
+ break;
+ }
+
+ BUG_ON(!timer);
+
+ timers[TIMER_ID_CLOCKSOURCE].base = ioremap(timer->base, SZ_4K);
+
+ /* The RTC is always running. We don't need to do any initialization. */
+ clocksource_picoxcell.read = picoxcell_rtc_get_cycles;
+ clocksource_register_hz(&clocksource_picoxcell, CLOCK_TICK_RATE);
+}
+
+static void __init picoxcell_timer_init(void)
+{
+ struct picoxcell_soc *soc = picoxcell_get_soc();
+
+ picoxcell_clocksource_init(soc);
+ picoxcell_clockevent_init(soc);
+}
+
+struct sys_timer picoxcell_sys_timer = {
+ .init = picoxcell_timer_init,
+};
+
+/*
+ * picoxcell's sched_clock implementation. It has a resolution of 5ns
+ * (200MHz).
+ */
+static DEFINE_CLOCK_DATA(cd);
+
+/*
+ * Constants generated by:
+ * clocks_calc_mult_shift(m, s, 200000000, NSEC_PER_SEC, 0);
+ */
+#define SC_MULT 2684354560LU
+#define SC_SHIFT 29
+
+unsigned long long notrace sched_clock(void)
+{
+ u32 cyc = __raw_readl(IO_ADDRESS(PICOXCELL_RTCLK_BASE) +
+ RTCLK_CCV_REG_OFFSET);
+ return cyc_to_fixed_sched_clock(&cd, cyc, (u32)~0, SC_MULT, SC_SHIFT);
+}
+
+static void notrace picoxcell_update_sched_clock(void)
+{
+ u32 cyc = __raw_readl(IO_ADDRESS(PICOXCELL_RTCLK_BASE) +
+ RTCLK_CCV_REG_OFFSET);
+ update_sched_clock(&cd, cyc, (u32)~0);
+}
+
+void __init picoxcell_sched_clock_init(void)
+{
+ /*
+ * Reset the RTC. We don't know how long the RTC has been running for
+ * in the bootloader.
+ */
+ __raw_writel(0, IO_ADDRESS(PICOXCELL_RTCLK_BASE +
+ RTCLK_SET_REG_OFFSET));
+ init_fixed_sched_clock(&cd, picoxcell_update_sched_clock, 32,
+ CLOCK_TICK_RATE, SC_MULT, SC_SHIFT);
+}
--
1.7.4
The different picoXcell device variants have different numbers of clocks
and different capabilities (PC3X2 doesn't have any gateable or
controllable clocks). Add the infrastructure necessary for device
variants to provide their own clock implementation.
Signed-off-by: Jamie Iles <[email protected]>
---
arch/arm/Kconfig | 1 +
arch/arm/mach-picoxcell/Makefile | 3 +-
arch/arm/mach-picoxcell/clk.c | 83 +++++++++++++++++++++++++
arch/arm/mach-picoxcell/include/mach/clkdev.h | 70 +++++++++++++++++++++
arch/arm/mach-picoxcell/picoxcell_core.c | 1 +
5 files changed, 157 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/mach-picoxcell/clk.c
create mode 100644 arch/arm/mach-picoxcell/include/mach/clkdev.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 75ff454..7d67e68 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -612,6 +612,7 @@ config ARCH_PICOXCELL
select HAVE_SCHED_CLOCK
select CPU_V6K
select HAVE_TCM
+ select CLKDEV_LOOKUP
help
This enables support for systems based on the Picochip picoXcell
family of Femtocell devices.
diff --git a/arch/arm/mach-picoxcell/Makefile b/arch/arm/mach-picoxcell/Makefile
index 3cace37..f6fc8de 100644
--- a/arch/arm/mach-picoxcell/Makefile
+++ b/arch/arm/mach-picoxcell/Makefile
@@ -1,3 +1,4 @@
obj-y := picoxcell_core.o io.o axi2cfg.o \
time.o \
- devices.o
+ devices.o \
+ clk.o
diff --git a/arch/arm/mach-picoxcell/clk.c b/arch/arm/mach-picoxcell/clk.c
new file mode 100644
index 0000000..b32e478
--- /dev/null
+++ b/arch/arm/mach-picoxcell/clk.c
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2010 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * All enquiries to [email protected]
+ */
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/module.h>
+#include <linux/seq_file.h>
+#include <linux/spinlock.h>
+
+#include <mach/clkdev.h>
+
+static DEFINE_SPINLOCK(clk_lock);
+static LIST_HEAD(picoxcell_clks);
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+ return clk->get_rate ? clk->get_rate(clk) : clk->rate;
+}
+EXPORT_SYMBOL(clk_get_rate);
+
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+ return clk->round_rate ? clk->round_rate(clk, rate) : -EOPNOTSUPP;
+}
+EXPORT_SYMBOL(clk_round_rate);
+
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+ return clk->set_rate ? clk->set_rate(clk, rate) : 0;
+}
+EXPORT_SYMBOL(clk_set_rate);
+
+int __clk_enable(struct clk *clk)
+{
+ if (++clk->enable_count > 0) {
+ if (clk->enable)
+ clk->enable(clk);
+ }
+
+ return 0;
+}
+
+int clk_enable(struct clk *clk)
+{
+ unsigned long flags;
+ int ret;
+
+ spin_lock_irqsave(&clk_lock, flags);
+ ret = __clk_enable(clk);
+ spin_unlock_irqrestore(&clk_lock, flags);
+
+ return ret;
+}
+EXPORT_SYMBOL(clk_enable);
+
+void __clk_disable(struct clk *clk)
+{
+ if (--clk->enable_count <= 0) {
+ if (clk->disable)
+ clk->disable(clk);
+ }
+}
+
+void clk_disable(struct clk *clk)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&clk_lock, flags);
+ __clk_disable(clk);
+ spin_unlock_irqrestore(&clk_lock, flags);
+}
+EXPORT_SYMBOL(clk_disable);
+
+void picoxcell_clk_add(struct clk *clk)
+{
+ list_add_tail(&clk->head, &picoxcell_clks);
+}
diff --git a/arch/arm/mach-picoxcell/include/mach/clkdev.h b/arch/arm/mach-picoxcell/include/mach/clkdev.h
new file mode 100644
index 0000000..93c6058
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/clkdev.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2010 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * All enquiries to [email protected]
+ */
+#ifndef __PICOXCELL_CLKDEV_H__
+#define __PICOXCELL_CLKDEV_H__
+
+#include <linux/clkdev.h>
+
+struct clk {
+ const char *name;
+ struct list_head head;
+ int rate;
+ unsigned min, max, step; /* min, max and frequency steps for
+ variable rate clocks in KHz. */
+ int enable_count;
+ int clk_num;
+ void (*enable)(struct clk *clk);
+ void (*disable)(struct clk *clk);
+ int (*is_enabled)(struct clk *clk);
+ long (*round_rate)(struct clk *clk, unsigned long rate);
+ int (*set_rate)(struct clk *clk, unsigned long rate);
+ int (*get_rate)(struct clk *clk);
+};
+
+static inline int __clk_get(struct clk *clk)
+{
+ return 1;
+}
+
+static inline void __clk_put(struct clk *clk)
+{
+}
+
+extern void picoxcell_clk_add(struct clk *clk);
+extern int __clk_enable(struct clk *clk);
+extern void __clk_disable(struct clk *clk);
+
+/*
+ * Declare a new clock with a given rate and ID. All clocks are enabled by
+ * default.
+ */
+#define FIXED_CLK(__name, __rate, __id) \
+ static struct clk __name ## _clk = { \
+ .name = #__name, \
+ .rate = __rate, \
+ .clk_num = __id, \
+ .enable_count = 1, \
+ }
+
+#define VARIABLE_CLK(__name, __id, __min, __max, __step) \
+ static struct clk __name ## _clk = { \
+ .name = #__name, \
+ .clk_num = __id, \
+ .enable_count = 1, \
+ .rate = -1, \
+ .min = __min, \
+ .max = __max, \
+ .step = __step, \
+ }
+
+#define CLK_LOOKUP(__dev_id, __con_id, __clk) \
+ { .dev_id = __dev_id, .con_id = __con_id, .clk = __clk }
+
+#endif /* __PICOXCELL_CLKDEV_H__ */
diff --git a/arch/arm/mach-picoxcell/picoxcell_core.c b/arch/arm/mach-picoxcell/picoxcell_core.c
index a54d981..3716d03 100644
--- a/arch/arm/mach-picoxcell/picoxcell_core.c
+++ b/arch/arm/mach-picoxcell/picoxcell_core.c
@@ -14,6 +14,7 @@
#include <asm/hardware/vic.h>
#include <asm/mach-types.h>
+#include <mach/clkdev.h>
#include <mach/hardware.h>
#include "picoxcell_core.h"
--
1.7.4
The PC7302 development board is capable of taking both PC3X2 and PC3X3
devices and features NOR flash, NAND flash, SPI NOR flash a serial
console, 100Mb Ethernet and a number of picoArray peripherals.
This patch provides initial support for running on the PC7302 board.
v4:
- reduce to the bare minimum for NOR flash booting.
v3:
- remove redundant __init declarations.
v2:
- multiplex the NAND CLE pin by pad name.
- convert to __raw_ io accessors.
Signed-off-by: Jamie Iles <[email protected]>
---
arch/arm/mach-picoxcell/Kconfig | 11 +++
arch/arm/mach-picoxcell/Makefile | 1 +
arch/arm/mach-picoxcell/board_pc7302.c | 109 ++++++++++++++++++++++++++++++++
3 files changed, 121 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-picoxcell/board_pc7302.c
diff --git a/arch/arm/mach-picoxcell/Kconfig b/arch/arm/mach-picoxcell/Kconfig
index 7b74a45..9e08542 100644
--- a/arch/arm/mach-picoxcell/Kconfig
+++ b/arch/arm/mach-picoxcell/Kconfig
@@ -1,2 +1,13 @@
if ARCH_PICOXCELL
+
+comment "Picochip picoXcell board selection"
+
+config BOARD_PC7302
+ bool "Support PC7302 Board"
+ default y
+ help
+ Include support for the picoChip PC7302 platform. This platform is
+ can take any of the PC3X2 or PC3X3 devices and includes SPI NOR
+ flash, parallel NOR flash and NAND flash.
+
endif
diff --git a/arch/arm/mach-picoxcell/Makefile b/arch/arm/mach-picoxcell/Makefile
index f6fc8de..69a9e6b 100644
--- a/arch/arm/mach-picoxcell/Makefile
+++ b/arch/arm/mach-picoxcell/Makefile
@@ -2,3 +2,4 @@ obj-y := picoxcell_core.o io.o axi2cfg.o \
time.o \
devices.o \
clk.o
+obj-$(CONFIG_BOARD_PC7302) += board_pc7302.o
diff --git a/arch/arm/mach-picoxcell/board_pc7302.c b/arch/arm/mach-picoxcell/board_pc7302.c
new file mode 100644
index 0000000..6d2b5e0
--- /dev/null
+++ b/arch/arm/mach-picoxcell/board_pc7302.c
@@ -0,0 +1,109 @@
+/*
+ * linux/arch/arm/mach-picoxcell/board_pc7302.c
+ *
+ * Copyright (c) 2010 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * All enquiries to [email protected]
+ */
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <linux/spi/flash.h>
+
+#include <mach/hardware.h>
+#include <asm/leds.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+#include "picoxcell_core.h"
+
+static long pc7302_panic_blink(int state)
+{
+ __raw_writel(state ? 0xFF : 0, IO_ADDRESS(PICOXCELL_GPIO_BASE +
+ GPIO_SW_PORT_C_DR_REG_OFFSET));
+ return 0;
+}
+
+static void pc7302_panic_init(void)
+{
+ /*
+ * We have a BOOT_ERROR pin on PC7302. Reuse that for signalling when
+ * the kernel panics. There is only 1 bit wired up to port C but it
+ * won't hurt to configure all of them.
+ */
+ __raw_writel(0xF, IO_ADDRESS(PICOXCELL_GPIO_BASE +
+ GPIO_SW_PORT_C_DDR_REG_OFFSET));
+ __raw_writel(0x0, IO_ADDRESS(PICOXCELL_GPIO_BASE +
+ GPIO_SW_PORT_C_CTL_REG_OFFSET));
+
+ panic_blink = pc7302_panic_blink;
+}
+
+static struct mtd_partition pc7302_nor_partitions[] = {
+ {
+ .name = "Boot",
+ .size = SZ_128K,
+ .offset = 0,
+ },
+ {
+ .name = "Boot Environment",
+ .size = SZ_128K,
+ .offset = MTDPART_OFS_APPEND,
+ },
+ {
+ .name = "Kernel",
+ .size = SZ_4M,
+ .offset = MTDPART_OFS_APPEND,
+ },
+ {
+ .name = "Application",
+ .size = MTDPART_SIZ_FULL,
+ .offset = MTDPART_OFS_APPEND,
+ },
+};
+
+static struct physmap_flash_data pc7302_nor_flash_data = {
+ .width = 1,
+ .parts = pc7302_nor_partitions,
+ .nr_parts = ARRAY_SIZE(pc7302_nor_partitions)
+};
+
+static struct resource pc7302_nor_resource = {
+ .start = PICOXCELL_FLASH_BASE,
+ .end = PICOXCELL_FLASH_BASE + SZ_128M - 1,
+ .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device pc7302_nor = {
+ .name = "physmap-flash",
+ .id = -1,
+ .dev.platform_data = &pc7302_nor_flash_data,
+ .resource = &pc7302_nor_resource,
+ .num_resources = 1,
+};
+
+static void pc7302_init_nor(void)
+{
+ platform_device_register(&pc7302_nor);
+}
+
+static void __init pc7302_init(void)
+{
+ picoxcell_core_init();
+ pc7302_init_nor();
+ pc7302_panic_init();
+}
+
+MACHINE_START(PC7302, "PC7302")
+ .map_io = picoxcell_map_io,
+ .init_irq = picoxcell_init_irq,
+ .init_early = picoxcell_init_early,
+ .timer = &picoxcell_sys_timer,
+ .init_machine = pc7302_init,
+MACHINE_END
--
1.7.4
Add the devices common to all picoXcell variants (UART and PMU). Other
peripherals such as DMA, SPI, fuses and EMAC will be added later
with driver support.
v3:
- move device registration to an arch_initcall
- mark common_devices with __initdata
v2: - split the UARTs into two separate platform devices and use
PLAT8250_* as the IDs
Signed-off-by: Jamie Iles <[email protected]>
---
arch/arm/mach-picoxcell/Makefile | 3 +-
arch/arm/mach-picoxcell/devices.c | 122 +++++++++++++++++++++++++++++++++++++
2 files changed, 124 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/mach-picoxcell/devices.c
diff --git a/arch/arm/mach-picoxcell/Makefile b/arch/arm/mach-picoxcell/Makefile
index 493ec0e..3cace37 100644
--- a/arch/arm/mach-picoxcell/Makefile
+++ b/arch/arm/mach-picoxcell/Makefile
@@ -1,2 +1,3 @@
obj-y := picoxcell_core.o io.o axi2cfg.o \
- time.o
+ time.o \
+ devices.o
diff --git a/arch/arm/mach-picoxcell/devices.c b/arch/arm/mach-picoxcell/devices.c
new file mode 100644
index 0000000..884ecb5
--- /dev/null
+++ b/arch/arm/mach-picoxcell/devices.c
@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) 2010 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * All enquiries to [email protected]
+ */
+#include <linux/serial_8250.h>
+#include <linux/serial_reg.h>
+#include <linux/platform_device.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <mach/hardware.h>
+#include <mach/irqs.h>
+
+#include <asm/pmu.h>
+
+#include "picoxcell_core.h"
+#include "soc.h"
+
+#define UART_USR_REG_OFFSET 0x7C
+static struct plat_serial8250_port serial1_platform_data[] = {
+ {
+ .membase = IO_ADDRESS(PICOXCELL_UART1_BASE),
+ .mapbase = PICOXCELL_UART1_BASE,
+ .irq = IRQ_UART1,
+ .flags = UPF_BOOT_AUTOCONF,
+ .iotype = UPIO_DWAPB32,
+ .regshift = 2,
+ .uartclk = PICOXCELL_BASE_BAUD,
+ .private_data = (void *)(PHYS_TO_IO(PICOXCELL_UART1_BASE +
+ UART_USR_REG_OFFSET)),
+ },
+ {},
+};
+
+static struct resource serial1_resources[] = {
+ {
+ .start = PICOXCELL_UART1_BASE,
+ .end = PICOXCELL_UART1_BASE + 0xFFFF,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = IRQ_UART1,
+ .end = IRQ_UART2,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device serial1_device = {
+ .name = "serial8250",
+ .id = PLAT8250_DEV_PLATFORM1,
+ .dev.platform_data = serial1_platform_data,
+ .resource = serial1_resources,
+ .num_resources = ARRAY_SIZE(serial1_resources),
+};
+
+static struct plat_serial8250_port serial2_platform_data[] = {
+ {
+ .membase = IO_ADDRESS(PICOXCELL_UART2_BASE),
+ .mapbase = PICOXCELL_UART2_BASE,
+ .irq = IRQ_UART2,
+ .flags = UPF_BOOT_AUTOCONF,
+ .iotype = UPIO_DWAPB32,
+ .regshift = 2,
+ .uartclk = PICOXCELL_BASE_BAUD,
+ .private_data = (void *)(PHYS_TO_IO(PICOXCELL_UART2_BASE +
+ UART_USR_REG_OFFSET)),
+ },
+ {},
+};
+
+static struct resource serial2_resources[] = {
+ {
+ .start = PICOXCELL_UART2_BASE,
+ .end = PICOXCELL_UART2_BASE + 0xFFFF,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = IRQ_UART2,
+ .end = IRQ_UART2,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device serial2_device = {
+ .name = "serial8250",
+ .id = PLAT8250_DEV_PLATFORM2,
+ .dev.platform_data = serial2_platform_data,
+ .resource = serial2_resources,
+ .num_resources = ARRAY_SIZE(serial2_resources),
+};
+
+static struct resource pmu_resource = {
+ .start = IRQ_NPMUIRQ,
+ .end = IRQ_NPMUIRQ,
+ .flags = IORESOURCE_IRQ,
+};
+
+static struct platform_device pmu_device = {
+ .name = "arm-pmu",
+ .id = ARM_PMU_DEVICE_CPU,
+ .num_resources = 1,
+ .resource = &pmu_resource,
+};
+
+static struct platform_device *common_devices[] __initdata = {
+ &serial1_device,
+ &serial2_device,
+ &pmu_device,
+};
+
+static int __init picoxcell_add_devices(void)
+{
+ platform_add_devices(common_devices, ARRAY_SIZE(common_devices));
+
+ return 0;
+}
+arch_initcall(picoxcell_add_devices);
--
1.7.4
picoXcell is a family of femtocell SoC devices from Picochip [1] with an
ARM subsystem. The devices have an ARM1176JZ-S core and a DSP processor
array. Currently there are two sub families - PC3X2 and PC3X3. The
latter includes extra power and performance control along with extra
peripherals.
This initial patch adds the hardware definitions and a framework for
adding device variants.
v2:
- Define VMALLOC_END as a fixed address rather than relative to
PAGE_OFFSET
- Reduce the number of static IO mappings
- Put the picoXcell entry in the correct place in
arch/arm/Kconfig
v3:
- Incorporate feedback from RMK
- Refactor static IO mappings into io.c and include arch
specific ioremap and iounmap to reuse static mappings.
- Tell Linux about the TCMs and the onchip SRAM.
- Switch to __raw_ io accessors where possible. Note the AXI2CFG
requires a strongly ordered protocol so retains ordered
accessors.
v4:
- Remove redundant __init declarations and add a cpu_relax() to
the AXI2CFG read polling
- Allow soc variants to register variant specific devices
v5:
- Remove all of the sysdev and AXI2Cfg configuration stuff to
reduce it to the bare minimum to boot on all devices.
v6:
- Move the 32-bit UART accesses for DEBUG_LL into the machine
debug-macros.S and remove the hardcoded addresses.
1. http://www.picochip.com
Signed-off-by: Jamie Iles <[email protected]>
---
arch/arm/Kconfig | 13 ++
arch/arm/Makefile | 1 +
arch/arm/mach-picoxcell/Kconfig | 2 +
arch/arm/mach-picoxcell/Makefile | 1 +
arch/arm/mach-picoxcell/Makefile.boot | 3 +
arch/arm/mach-picoxcell/axi2cfg.c | 36 ++++++
arch/arm/mach-picoxcell/include/mach/debug-macro.S | 39 ++++++
arch/arm/mach-picoxcell/include/mach/entry-macro.S | 19 +++
arch/arm/mach-picoxcell/include/mach/hardware.h | 29 +++++
arch/arm/mach-picoxcell/include/mach/io.h | 38 ++++++
arch/arm/mach-picoxcell/include/mach/irqs.h | 89 ++++++++++++++
arch/arm/mach-picoxcell/include/mach/memory.h | 27 +++++
.../include/mach/picoxcell/axi2cfg.h | 122 ++++++++++++++++++++
.../mach-picoxcell/include/mach/picoxcell/gpio.h | 48 ++++++++
.../include/mach/picoxcell/picoxcell.h | 62 ++++++++++
.../mach-picoxcell/include/mach/picoxcell/timer.h | 37 ++++++
.../mach-picoxcell/include/mach/picoxcell/wdog.h | 43 +++++++
arch/arm/mach-picoxcell/include/mach/platform.h | 27 +++++
arch/arm/mach-picoxcell/include/mach/system.h | 51 ++++++++
arch/arm/mach-picoxcell/include/mach/timex.h | 26 ++++
arch/arm/mach-picoxcell/include/mach/uncompress.h | 60 ++++++++++
arch/arm/mach-picoxcell/include/mach/vmalloc.h | 18 +++
arch/arm/mach-picoxcell/io.c | 49 ++++++++
arch/arm/mach-picoxcell/picoxcell_core.c | 105 +++++++++++++++++
arch/arm/mach-picoxcell/picoxcell_core.h | 22 ++++
arch/arm/mach-picoxcell/soc.h | 32 +++++
26 files changed, 999 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-picoxcell/Kconfig
create mode 100644 arch/arm/mach-picoxcell/Makefile
create mode 100644 arch/arm/mach-picoxcell/Makefile.boot
create mode 100644 arch/arm/mach-picoxcell/axi2cfg.c
create mode 100644 arch/arm/mach-picoxcell/include/mach/debug-macro.S
create mode 100644 arch/arm/mach-picoxcell/include/mach/entry-macro.S
create mode 100644 arch/arm/mach-picoxcell/include/mach/hardware.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/io.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/irqs.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/memory.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/picoxcell/axi2cfg.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/picoxcell/gpio.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/picoxcell/picoxcell.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/picoxcell/timer.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/picoxcell/wdog.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/platform.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/system.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/timex.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/uncompress.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/vmalloc.h
create mode 100644 arch/arm/mach-picoxcell/io.c
create mode 100644 arch/arm/mach-picoxcell/picoxcell_core.c
create mode 100644 arch/arm/mach-picoxcell/picoxcell_core.h
create mode 100644 arch/arm/mach-picoxcell/soc.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 30d8a63..75ff454 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -605,6 +605,17 @@ config ARCH_PNX4008
help
This enables support for Philips PNX4008 mobile platform.
+config ARCH_PICOXCELL
+ bool "Picochip picoXcell"
+ select ARM_VIC
+ select GENERIC_CLOCKEVENTS
+ select HAVE_SCHED_CLOCK
+ select CPU_V6K
+ select HAVE_TCM
+ help
+ This enables support for systems based on the Picochip picoXcell
+ family of Femtocell devices.
+
config ARCH_PXA
bool "PXA2xx/PXA3xx-based"
depends on MMU
@@ -955,6 +966,8 @@ source "arch/arm/mach-omap2/Kconfig"
source "arch/arm/mach-orion5x/Kconfig"
+source "arch/arm/mach-picoxcell/Kconfig"
+
source "arch/arm/mach-pxa/Kconfig"
source "arch/arm/plat-pxa/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index d6e6206..864f00d 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -166,6 +166,7 @@ machine-$(CONFIG_ARCH_OMAP2) := omap2
machine-$(CONFIG_ARCH_OMAP3) := omap2
machine-$(CONFIG_ARCH_OMAP4) := omap2
machine-$(CONFIG_ARCH_ORION5X) := orion5x
+machine-$(CONFIG_ARCH_PICOXCELL) := picoxcell
machine-$(CONFIG_ARCH_PNX4008) := pnx4008
machine-$(CONFIG_ARCH_PXA) := pxa
machine-$(CONFIG_ARCH_REALVIEW) := realview
diff --git a/arch/arm/mach-picoxcell/Kconfig b/arch/arm/mach-picoxcell/Kconfig
new file mode 100644
index 0000000..7b74a45
--- /dev/null
+++ b/arch/arm/mach-picoxcell/Kconfig
@@ -0,0 +1,2 @@
+if ARCH_PICOXCELL
+endif
diff --git a/arch/arm/mach-picoxcell/Makefile b/arch/arm/mach-picoxcell/Makefile
new file mode 100644
index 0000000..6afe388
--- /dev/null
+++ b/arch/arm/mach-picoxcell/Makefile
@@ -0,0 +1 @@
+obj-y := picoxcell_core.o io.o axi2cfg.o
diff --git a/arch/arm/mach-picoxcell/Makefile.boot b/arch/arm/mach-picoxcell/Makefile.boot
new file mode 100644
index 0000000..67039c3
--- /dev/null
+++ b/arch/arm/mach-picoxcell/Makefile.boot
@@ -0,0 +1,3 @@
+ zreladdr-y := 0x00008000
+params_phys-y := 0x00000100
+initrd_phys-y := 0x00800000
diff --git a/arch/arm/mach-picoxcell/axi2cfg.c b/arch/arm/mach-picoxcell/axi2cfg.c
new file mode 100644
index 0000000..6bb4014
--- /dev/null
+++ b/arch/arm/mach-picoxcell/axi2cfg.c
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2010 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * All enquiries to [email protected]
+ *
+ * This file implements functions for using the axi2cfg to configure and debug
+ * picoArray systems providing configuration bus access over the axi2cfg.
+ */
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/spinlock.h>
+
+#include <mach/hardware.h>
+
+static void __iomem *axi2cfg;
+
+unsigned long axi2cfg_readl(unsigned long offs)
+{
+ return readl(axi2cfg + offs);
+}
+
+void axi2cfg_writel(unsigned long val, unsigned long offs)
+{
+ writel(val, axi2cfg + offs);
+}
+
+void __init axi2cfg_init(void)
+{
+ axi2cfg = ioremap(PICOXCELL_AXI2CFG_BASE, 0x300);
+ BUG_ON(!axi2cfg);
+}
diff --git a/arch/arm/mach-picoxcell/include/mach/debug-macro.S b/arch/arm/mach-picoxcell/include/mach/debug-macro.S
new file mode 100644
index 0000000..da41fb4
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/debug-macro.S
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2010 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Derived from arch/arm/mach-davinci/include/mach/debug-macro.S to use 32-bit
+ * accesses to the 8250.
+ */
+#include <linux/serial_reg.h>
+#include <mach/hardware.h>
+#include <mach/io.h>
+
+#define UART_SHIFT 2
+
+ .macro addruart, rp, rv
+ ldr \rv, =PHYS_TO_IO(PICOXCELL_UART1_BASE)
+ ldr \rp, =PICOXCELL_UART1_BASE
+ .endm
+
+ .macro senduart,rd,rx
+ str \rd, [\rx, #UART_TX << UART_SHIFT]
+ .endm
+
+ .macro busyuart,rd,rx
+1002: ldr \rd, [\rx, #UART_LSR << UART_SHIFT]
+ and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
+ teq \rd, #UART_LSR_TEMT | UART_LSR_THRE
+ bne 1002b
+ .endm
+
+ .macro waituart,rd,rx
+#ifdef FLOW_CONTROL
+1001: ldr \rd, [\rx, #UART_MSR << UART_SHIFT]
+ tst \rd, #UART_MSR_CTS
+ beq 1001b
+#endif
+ .endm
diff --git a/arch/arm/mach-picoxcell/include/mach/entry-macro.S b/arch/arm/mach-picoxcell/include/mach/entry-macro.S
new file mode 100644
index 0000000..4dcda96
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/entry-macro.S
@@ -0,0 +1,19 @@
+/*
+ * entry-macro.S
+ *
+ * Copyright (c) 2010 Picochip Ltd., Jamie Iles
+ *
+ * Low-level IRQ helper macros for picoXcell platforms
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <mach/hardware.h>
+#include <mach/io.h>
+#include <mach/irqs.h>
+
+#define VA_VIC0 IO_ADDRESS(PICOXCELL_VIC0_BASE)
+#define VA_VIC1 IO_ADDRESS(PICOXCELL_VIC1_BASE)
+
+#include <asm/entry-macro-vic2.S>
diff --git a/arch/arm/mach-picoxcell/include/mach/hardware.h b/arch/arm/mach-picoxcell/include/mach/hardware.h
new file mode 100644
index 0000000..7c203d3
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/hardware.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2010 Picochip Ltd., Jamie Iles
+ *
+ * This file contains the hardware definitions of the picoXcell SoC devices.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <mach/picoxcell/axi2cfg.h>
+#include <mach/picoxcell/gpio.h>
+#include <mach/picoxcell/picoxcell.h>
+#include <mach/picoxcell/timer.h>
+#include <mach/picoxcell/wdog.h>
+
+#endif
diff --git a/arch/arm/mach-picoxcell/include/mach/io.h b/arch/arm/mach-picoxcell/include/mach/io.h
new file mode 100644
index 0000000..d8f2d76
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/io.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2010 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define PHYS_TO_IO(x) (((x) & 0x00ffffff) | 0xfe000000)
+
+#ifdef __ASSEMBLY__
+# define IO_ADDRESS(x) PHYS_TO_IO((x))
+#else /* __ASSEMBLY__ */
+# define IO_ADDRESS(x) (void __iomem __force *)(PHYS_TO_IO((x)))
+# define IO_SPACE_LIMIT 0xffffffff
+# define __io(a) __typesafe_io(a)
+# define __mem_pci(a) (a)
+# define __arch_ioremap picoxcell_ioremap
+# define __arch_iounmap picoxcell_iounmap
+
+void __iomem *picoxcell_ioremap(unsigned long phys, size_t size,
+ unsigned int type);
+void picoxcell_iounmap(volatile void __iomem *addr);
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ASM_ARM_ARCH_IO_H */
diff --git a/arch/arm/mach-picoxcell/include/mach/irqs.h b/arch/arm/mach-picoxcell/include/mach/irqs.h
new file mode 100644
index 0000000..0fe84ff
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/irqs.h
@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2010 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __IRQS_H__
+#define __IRQS_H__
+
+/* VIC0 IRQ Indexes */
+#define IRQ_VIC0_BASE 32
+#define IRQ_EMAC (31 + IRQ_VIC0_BASE)
+#define IRQ_NPMUIRQ (30 + IRQ_VIC0_BASE)
+#define IRQ_NDMAEXTERRIRQ (29 + IRQ_VIC0_BASE)
+#define IRQ_NDMASIRQ (28 + IRQ_VIC0_BASE)
+#define IRQ_NDMAIRQ (27 + IRQ_VIC0_BASE)
+#define IRQ_DMAC2 (26 + IRQ_VIC0_BASE)
+#define IRQ_DMAC1 (25 + IRQ_VIC0_BASE)
+#define IRQ_IPSEC (24 + IRQ_VIC0_BASE)
+#define IRQ_SRTP (23 + IRQ_VIC0_BASE)
+#define IRQ_AES (22 + IRQ_VIC0_BASE)
+#define IRQ_AXI2PICO8 (21 + IRQ_VIC0_BASE)
+#define IRQ_AXI2PICO7 (20 + IRQ_VIC0_BASE)
+#define IRQ_AXI2PICO6 (19 + IRQ_VIC0_BASE)
+#define IRQ_AXI2PICO5 (18 + IRQ_VIC0_BASE)
+#define IRQ_AXI2PICO4 (17 + IRQ_VIC0_BASE)
+#define IRQ_AXI2PICO3 (16 + IRQ_VIC0_BASE)
+#define IRQ_AXI2PICO2 (15 + IRQ_VIC0_BASE)
+#define IRQ_AXI2PICO1 (14 + IRQ_VIC0_BASE)
+#define IRQ_AXI2PICO0 (13 + IRQ_VIC0_BASE)
+#define IRQ_AXI2CFG (12 + IRQ_VIC0_BASE)
+#define IRQ_WDG (11 + IRQ_VIC0_BASE)
+#define IRQ_SSI (10 + IRQ_VIC0_BASE)
+#define IRQ_AXI_RD_ERR (9 + IRQ_VIC0_BASE)
+#define IRQ_AXI_WR_ERR (8 + IRQ_VIC0_BASE)
+#define IRQ_TIMER3 (7 + IRQ_VIC0_BASE)
+#define IRQ_TIMER2 (6 + IRQ_VIC0_BASE)
+#define IRQ_TIMER1 (5 + IRQ_VIC0_BASE)
+#define IRQ_TIMER0 (4 + IRQ_VIC0_BASE)
+#define IRQ_COMMTX (3 + IRQ_VIC0_BASE)
+#define IRQ_COMMRX (2 + IRQ_VIC0_BASE)
+#define IRQ_SWI (1 + IRQ_VIC0_BASE)
+
+/* VIC1 IRQ Indexes */
+#define IRQ_VIC1_BASE 0
+#define IRQ_UART1 (10 + IRQ_VIC1_BASE)
+#define IRQ_UART2 (9 + IRQ_VIC1_BASE)
+#define IRQ_RTC (8 + IRQ_VIC1_BASE)
+#define __IRQ_GPIO7 (7 + IRQ_VIC1_BASE)
+#define __IRQ_GPIO6 (6 + IRQ_VIC1_BASE)
+#define __IRQ_GPIO5 (5 + IRQ_VIC1_BASE)
+#define __IRQ_GPIO4 (4 + IRQ_VIC1_BASE)
+#define __IRQ_GPIO3 (3 + IRQ_VIC1_BASE)
+#define __IRQ_GPIO2 (2 + IRQ_VIC1_BASE)
+#define __IRQ_GPIO1 (1 + IRQ_VIC1_BASE)
+#define __IRQ_GPIO0 (0 + IRQ_VIC1_BASE)
+
+/*
+ * Virtual GPIO interrupts.
+ *
+ * We want to enable/disable interrupts for the GPIO pins through the GPIO
+ * block itself. To do this we install a chained handler. If a user requests
+ * one of the __IRQ_GPIOn interrupts then the GPIO block won't get configured.
+ * We provide these interrupts below as virtual ones that will configure the
+ * GPIO block and enable the source in the VIC.
+ */
+#define IRQ_GPIO7 71
+#define IRQ_GPIO6 70
+#define IRQ_GPIO5 69
+#define IRQ_GPIO4 68
+#define IRQ_GPIO3 67
+#define IRQ_GPIO2 66
+#define IRQ_GPIO1 65
+#define IRQ_GPIO0 64
+
+#define NR_IRQS 72
+
+#endif /* __IRQS_H__ */
diff --git a/arch/arm/mach-picoxcell/include/mach/memory.h b/arch/arm/mach-picoxcell/include/mach/memory.h
new file mode 100644
index 0000000..c0f6077
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/memory.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2010 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+/*
+ * Physical DRAM offset.
+ */
+#define PLAT_PHYS_OFFSET UL(0x00000000)
+
+#endif
+
diff --git a/arch/arm/mach-picoxcell/include/mach/picoxcell/axi2cfg.h b/arch/arm/mach-picoxcell/include/mach/picoxcell/axi2cfg.h
new file mode 100644
index 0000000..94c9800
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/picoxcell/axi2cfg.h
@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) 2010 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef PICOXCELL_AXI2CFG_H
+#define PICOXCELL_AXI2CFG_H
+
+#define AXI2CFG_SYSCFG_REG_OFFSET 0x0000
+#define AXI2CFG_JTAG_ISC_REG_OFFSET 0x0004
+#define AXI2CFG_IRQ_REG_OFFSET 0x0008
+#define AXI2CFG_PURGE_CFG_PORT_REG_OFFSET 0x000C
+#define AXI2CFG_DMA_CFG_REG_OFFSET 0x0010
+#define AXI2CFG_DEVICE_ID_REG_OFFSET 0x0014
+#define AXI2CFG_REVISION_ID_REG_OFFSET 0x0018
+#define AXI2CFG_AXI_ERR_ENABLE_REG_OFFSET 0x001C
+#define AXI2CFG_AXI_ERR_CLEAR_REG_OFFSET 0x0020
+#define AXI2CFG_AXI_ERR_MASK_REG_OFFSET 0x0024
+#define AXI2CFG_AXI_ERR_TEST_REG_OFFSET 0x0028
+#define AXI2CFG_AXI_ERR_RAW_REG_OFFSET 0x002C
+#define AXI2CFG_AXI_ERR_STATE_REG_OFFSET 0x0030
+#define AXI2CFG_CLOCK_GATING_REG_OFFSET 0x0048
+#define AXI2CFG_CONFIG_WRITE_REG_OFFSET 0x0100
+#define AXI2CFG_CONFIG_READ_REG_OFFSET 0x0200
+#define AXI2CFG_DMAC1_CONFIG_REG_OFFSET 0x0300
+
+#define AXI2CFG_SYSCFG_PA_RST_IDX 30
+#define AXI2CFG_SYSCFG_SD_ARM_GPIO_SEL_SZ 8
+#define AXI2CFG_SYSCFG_SD_ARM_GPIO_SEL_HI 23
+#define AXI2CFG_SYSCFG_SD_ARM_GPIO_SEL_LO 16
+#define AXI2CFG_SYSCFG_RW_EBI_CLK_DISABLE_IDX 15
+#define AXI2CFG_SYSCFG_RW_EXCVEC_EN_IDX 14
+#define AXI2CFG_SYSCFG_RW_RMII_EN_IDX 13
+#define AXI2CFG_SYSCFG_RW_REVMII_EN_IDX 12
+#define AXI2CFG_SYSCFG_SSI_EBI_SEL_SZ 4
+#define AXI2CFG_SYSCFG_SSI_EBI_SEL_HI 11
+#define AXI2CFG_SYSCFG_SSI_EBI_SEL_LO 8
+#define AXI2CFG_SYSCFG_FREQ_SYNTH_MUX_IDX 7
+#define AXI2CFG_SYSCFG_MASK_AXI_ERR_IDX 6
+#define AXI2CFG_SYSCFG_RW_REMAP_IDX 5
+#define AXI2CFG_SYSCFG_WDG_PAUSE_IDX 4
+#define AXI2CFG_SYSCFG_CP15DISABLE_IDX 3
+#define AXI2CFG_SYSCFG_DMAC1_CH7_IDX 2
+#define AXI2CFG_SYSCFG_BOOT_MODE_SZ 2
+#define AXI2CFG_SYSCFG_BOOT_MODE_HI 1
+#define AXI2CFG_SYSCFG_BOOT_MODE_LO 0
+
+#define AXI2CFG_SYSCFG_PA_RST_MASK \
+ (1 << AXI2CFG_SYSCFG_PA_RST_IDX)
+#define AXI2CFG_SYSCFG_SD_ARM_GPIO_MASK \
+ (((1 << AXI2CFG_SYSCFG_SD_ARM_GPIO_SEL_SZ) - 1) << \
+ AXI2CFG_SYSCFG_SD_ARM_GPIO_SEL_LO)
+#define AXI2CFG_SYSCFG_RW_EXCVEC_EN_MASK \
+ (1 << AXI2CFG_SYSCFG_RW_EXCVEC_EN_IDX)
+#define AXI2CFG_SYSCFG_RW_RMII_EN_MASK \
+ (1 << AXI2CFG_SYSCFG_RW_RMII_EN_IDX)
+#define AXI2CFG_SYSCFG_RW_REVMII_EN_MASK \
+ (1 << AXI2CFG_SYSCFG_RW_REVMII_EN_IDX)
+#define AXI2CFG_SYSCFG_SSI_EBI_SEL_MASK \
+ (((1 << AXI2CFG_SYSCFG_SSI_EBI_SEL_SZ) - 1) << \
+ AXI2CFG_SYSCFG_SSI_EBI_SEL_LO)
+#define AXI2CFG_SYSCFG_FREQ_SYNTH_MUX_MASK \
+ (1 << AXI2CFG_SYSCFG_FREQ_SYNTH_MUX_IDX)
+#define AXI2CFG_SYSCFG_MASK_AXI_ERR_MASK \
+ (1 << AXI2CFG_SYSCFG_MASK_AXI_ERR_IDX)
+#define AXI2CFG_SYSCFG_RW_REMAP_MASK \
+ (1 << AXI2CFG_SYSCFG_RW_REMAP_IDX)
+#define AXI2CFG_SYSCFG_WDG_PAUSE_MASK \
+ (1 << AXI2CFG_SYSCFG_WDG_PAUSE_IDX)
+#define AXI2CFG_SYSCFG_CP15DISABLE_MASK \
+ (1 << AXI2CFG_SYSCFG_CP15DISABLE_IDX)
+#define AXI2CFG_SYSCFG_DMAC1_CH7_MASK \
+ (1 << AXI2CFG_SYSCFG_DMAC1_CH7_IDX)
+#define AXI2CFG_SYSCFG_BOOT_MODE_MASK \
+ (((1 << AXI2CFG_SYSCFG_BOOT_MODE_SZ) - 1) << \
+ AXI2CFG_SYSCFG_BOOT_MODE_LO)
+
+#define AXI2CFG_AXI_RD_ERR_MASK 0x00000FFF
+#define AXI2CFG_AXI_WR_ERR_MASK 0x00FFF000
+#define AXI2CFG_AXI_ERR_MASK_NONE 0
+#define AXI2CFG_AXI_ERR_ENABLE_ALL 0x00FFFFFF
+
+#ifndef __ASSEMBLY__
+
+/*
+ * axi2cfg_init - initialize the AXI2CFG hardware.
+ */
+extern void axi2cfg_init(void);
+
+/*
+ * axi2cfg_readl - read a register in the axi2cfg.
+ *
+ * Returns the value of the register.
+ *
+ * @offs: the byte offset to read from.
+ */
+extern unsigned long axi2cfg_readl(unsigned long offs);
+
+/*
+ * axi2cfg_writel - write an axi2cfg AXI domain register.
+ *
+ * @val: the value to write.
+ * @offs: the byte offset to write to.
+ */
+extern void axi2cfg_writel(unsigned long val, unsigned long offs);
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* PICOXCELL_AXI2CFG_H */
diff --git a/arch/arm/mach-picoxcell/include/mach/picoxcell/gpio.h b/arch/arm/mach-picoxcell/include/mach/picoxcell/gpio.h
new file mode 100644
index 0000000..f526271
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/picoxcell/gpio.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2010 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef PICOXCELL_GPIO_H
+#define PICOXCELL_GPIO_H
+
+#define GPIO_SW_PORT_A_DR_REG_OFFSET 0x00
+#define GPIO_SW_PORT_A_DDR_REG_OFFSET 0x04
+#define GPIO_SW_PORT_A_CTL_REG_OFFSET 0x08
+#define GPIO_SW_PORT_B_DR_REG_OFFSET 0x0C
+#define GPIO_SW_PORT_B_DDR_REG_OFFSET 0x10
+#define GPIO_SW_PORT_B_CTL_REG_OFFSET 0x14
+#define GPIO_SW_PORT_C_DR_REG_OFFSET 0x18
+#define GPIO_SW_PORT_C_DDR_REG_OFFSET 0x1C
+#define GPIO_SW_PORT_C_CTL_REG_OFFSET 0x20
+#define GPIO_SW_PORT_D_DR_REG_OFFSET 0x24
+#define GPIO_SW_PORT_D_DDR_REG_OFFSET 0x28
+#define GPIO_SW_PORT_D_CTL_REG_OFFSET 0x2C
+
+#define GPIO_INT_EN_REG_OFFSET 0x30
+#define GPIO_INT_MASK_REG_OFFSET 0x34
+#define GPIO_INT_TYPE_LEVEL_REG_OFFSET 0x38
+#define GPIO_INT_POLARITY_REG_OFFSET 0x3c
+
+#define GPIO_INT_STATUS_REG_OFFSET 0x40
+
+#define GPIO_PORT_A_EOI_REG_OFFSET 0x4c
+#define GPIO_EXT_PORT_A_REG_OFFSET 0x50
+#define GPIO_EXT_PORT_B_REG_OFFSET 0x54
+#define GPIO_EXT_PORT_C_REG_OFFSET 0x58
+#define GPIO_EXT_PORT_D_REG_OFFSET 0x5C
+
+#endif /* PICOXCELL_GPIO_H */
diff --git a/arch/arm/mach-picoxcell/include/mach/picoxcell/picoxcell.h b/arch/arm/mach-picoxcell/include/mach/picoxcell/picoxcell.h
new file mode 100644
index 0000000..9691ec0
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/picoxcell/picoxcell.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2010 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __PICOXCELL_H__
+#define __PICOXCELL_H__
+
+#define BOOT_ROM_BASE 0xFFFF0000
+#define BOOT_ROM_SIZE 0x400
+#define AXI2PICO_BUFFERS_BASE 0xC0000000
+#define AXI2PICO_BUFFERS_SIZE 0x00010000
+#define PICOXCELL_PERIPH_BASE 0x80000000
+#define PICOXCELL_PERIPH_LENGTH 0x00400000
+#define PICOXCELL_MEMIF_BASE 0x80000000
+#define PICOXCELL_EBI_BASE 0x80010000
+#define PICOXCELL_EMAC_BASE 0x80030000
+#define PICOXCELL_DMAC1_BASE 0x80040000
+#define PICOXCELL_DMAC2_BASE 0x80050000
+#define PICOXCELL_VIC0_BASE 0x80060000
+#define PICOXCELL_VIC1_BASE 0x80064000
+#define PICOXCELL_TZIC_BASE 0x80068000
+#define PICOXCELL_TZPC_BASE 0x80070000
+#define PICOXCELL_FUSE_BASE 0x80080000
+#define PICOXCELL_SSI_BASE 0x80090000
+#define PICOXCELL_AXI2CFG_BASE 0x800A0000
+#define PICOXCELL_IPSEC_BASE 0x80100000
+#define PICOXCELL_SRTP_BASE 0x80140000
+#define PICOXCELL_CIPHER_BASE 0x80180000
+#define PICOXCELL_RTCLK_BASE 0x80200000
+#define PICOXCELL_TIMER_BASE 0x80210000
+#define PICOXCELL_GPIO_BASE 0x80220000
+#define PICOXCELL_UART1_BASE 0x80230000
+#define PICOXCELL_UART2_BASE 0x80240000
+#define PICOXCELL_WDOG_BASE 0x80250000
+#define PC3X3_RNG_BASE 0x800B0000
+#define PC3X3_TIMER2_BASE 0x80260000
+#define PC3X3_OTP_BASE 0xFFFF8000
+
+#define EBI_CS0_BASE 0x40000000
+#define EBI_CS1_BASE 0x48000000
+#define EBI_CS2_BASE 0x50000000
+#define EBI_CS3_BASE 0x58000000
+
+#define SRAM_BASE 0x20000000
+#define SRAM_START 0x20000000
+#define SRAM_SIZE 0x00020000
+#define SRAM_VIRT 0xFE400000
+
+#endif /* __PICOXCELL_H__ */
diff --git a/arch/arm/mach-picoxcell/include/mach/picoxcell/timer.h b/arch/arm/mach-picoxcell/include/mach/picoxcell/timer.h
new file mode 100644
index 0000000..8d67c42
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/picoxcell/timer.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2010 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef PICOXCELL_TIMER_H
+#define PICOXCELL_TIMER_H
+
+/* The spacing between individual timers. */
+#define TIMER_SPACING 0x14
+
+#define TIMER_LOAD_COUNT_REG_OFFSET 0x00
+#define TIMER_CONTROL_REG_OFFSET 0x08
+#define TIMER_EOI_REG_OFFSET 0x0c
+
+#define TIMERS_EOI_REG_OFFSET 0xa4
+
+#define TIMER_ENABLE 0x00000001
+#define TIMER_MODE 0x00000002
+#define TIMER_INTERRUPT_MASK 0x00000004
+
+#define RTCLK_CCV_REG_OFFSET 0x00
+#define RTCLK_SET_REG_OFFSET 0x08
+
+#endif /* PICOXCELL_TIMER_H */
diff --git a/arch/arm/mach-picoxcell/include/mach/picoxcell/wdog.h b/arch/arm/mach-picoxcell/include/mach/picoxcell/wdog.h
new file mode 100644
index 0000000..727780c
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/picoxcell/wdog.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2010 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef PICOXCELL_WDOG_H
+#define PICOXCELL_WDOG_H
+
+#define WDOG_CONTROL_REG_OFFSET 0x00
+#define WDOG_TIMEOUT_RANGE_REG_OFFSET 0x04
+#define WDOG_CURRENT_COUNT_REG_OFFSET 0x08
+#define WDOG_COUNTER_RESTART_REG_OFFSET 0x0c
+#define WDOG_INT_STATUS_REG_OFFSET 0x10
+#define WDOG_CLEAR_REG_OFFSET 0x14
+
+#define WDOG_CONTROL_REG_RESET 0x00000016
+#define WDOG_TIMEOUT_RANGE_REG_RESET 0x0000000c
+#define WDOG_CURRENT_COUNT_REG_RESET 0x0fffffff
+#define WDOG_COUNTER_RESTART_REG_RESET 0x00000000
+#define WDOG_INT_STATUS_REG_RESET 0x00000000
+#define WDOG_CLEAR_REG_RESET 0x00000000
+
+#define WDOGCONTROLREGWDT_ENIDX 0
+#define WDOGCONTROLREGRMODIDX 1
+#define WDOGCONTROLREGRPLIDX 2
+
+#define WDOG_CONTROL_REG_WDT_EN_MASK (1 << WDOGCONTROLREGWDT_ENIDX)
+#define WDOG_CONTROL_REG_RMOD_MASK (1 << WDOGCONTROLREGRMODIDX)
+#define WDOG_CONTROL_REG_RPL_MASK (0x7 << WDOGCONTROLREGRPLIDX)
+
+#endif /* PICOXCELL_WDOG_H */
diff --git a/arch/arm/mach-picoxcell/include/mach/platform.h b/arch/arm/mach-picoxcell/include/mach/platform.h
new file mode 100644
index 0000000..97697c0
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/platform.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2010 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __ARCH_PICOXCELL_PLATFORM_H
+#define __ARCH_PICOXCELL_PLATFORM_H
+
+/* Physical address of the Flash in the ARM sub-system memory map */
+#define PICOXCELL_FLASH_BASE 0x40000000
+
+/* The clock frequency for the UARTs */
+#define PICOXCELL_BASE_BAUD 3686400 /* 3.6864 MHz */
+
+#endif /* __ARCH_PICOXCELL_PLATFORM_H */
diff --git a/arch/arm/mach-picoxcell/include/mach/system.h b/arch/arm/mach-picoxcell/include/mach/system.h
new file mode 100644
index 0000000..b74cb7b
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/system.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2010 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+#include <mach/io.h>
+#include <mach/picoxcell/picoxcell.h>
+#include <mach/picoxcell/wdog.h>
+
+static inline void arch_idle(void)
+{
+ /*
+ * This should do all the clock switching
+ * and wait for interrupt tricks
+ */
+ cpu_do_idle();
+}
+
+static inline void arch_reset(int mode, const char *cmd)
+{
+ /*
+ * Set the watchdog to expire as soon as possible and reset the
+ * system.
+ */
+ __raw_writel(WDOG_CONTROL_REG_WDT_EN_MASK,
+ IO_ADDRESS(PICOXCELL_WDOG_BASE + WDOG_CONTROL_REG_OFFSET));
+ __raw_writel(0, IO_ADDRESS(PICOXCELL_WDOG_BASE +
+ WDOG_TIMEOUT_RANGE_REG_OFFSET));
+
+ /* Give it chance to reset. */
+ mdelay(500);
+
+ pr_crit("watchdog reset failed - entering infinite loop\n");
+}
+
+#endif /* __ASM_ARCH_SYSTEM_H */
diff --git a/arch/arm/mach-picoxcell/include/mach/timex.h b/arch/arm/mach-picoxcell/include/mach/timex.h
new file mode 100644
index 0000000..bf0fee6
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/timex.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2010 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __TIMEX_H__
+#define __TIMEX_H__
+
+#include <mach/platform.h>
+
+#define CLOCK_TICK_RATE 200000000 /* 200MHz */
+
+#endif /* __TIMEX_H__ */
+
diff --git a/arch/arm/mach-picoxcell/include/mach/uncompress.h b/arch/arm/mach-picoxcell/include/mach/uncompress.h
new file mode 100644
index 0000000..3b6c4a5a
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/uncompress.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2010 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#include <linux/io.h>
+#include <linux/serial_reg.h>
+
+#include <asm/processor.h>
+
+#include <mach/hardware.h>
+
+#define UART_SHIFT 2
+
+static inline void putc(int c)
+{
+ void __iomem *uart = (void __iomem *)(PICOXCELL_UART1_BASE);
+
+ while (!(__raw_readl(uart + (UART_LSR << UART_SHIFT)) & UART_LSR_THRE))
+ barrier();
+ __raw_writel(c & 0xFF, uart + (UART_TX << UART_SHIFT));
+}
+
+static inline void flush(void)
+{
+}
+
+static inline void arch_decomp_setup(void)
+{
+ void __iomem *uart = (void __iomem *)(PICOXCELL_UART1_BASE);
+
+ /* Reset and enable the FIFO's. */
+ __raw_writel(UART_FCR_ENABLE_FIFO, uart + (UART_FCR << UART_SHIFT));
+
+ /* Wait for the FIFO's to be enabled. */
+ while (!(__raw_readl(uart + (UART_FCR << UART_SHIFT)) &
+ UART_FCR_TRIGGER_14))
+ cpu_relax();
+ /* Enable divisor access, set length to 8 bits. */
+ __raw_writel(UART_LCR_DLAB | UART_LCR_WLEN8,
+ uart + (UART_LCR << UART_SHIFT));
+ /* Set for 115200 baud. */
+ __raw_writel(0x2, uart + (UART_DLL << UART_SHIFT));
+ __raw_writel(0x0, uart + (UART_DLM << UART_SHIFT));
+ __raw_writel(UART_LCR_WLEN8, uart + (UART_LCR << UART_SHIFT));
+}
+
+#define arch_decomp_wdog()
diff --git a/arch/arm/mach-picoxcell/include/mach/vmalloc.h b/arch/arm/mach-picoxcell/include/mach/vmalloc.h
new file mode 100644
index 0000000..09a7f75
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/vmalloc.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2010 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#define VMALLOC_END 0xFE000000UL
diff --git a/arch/arm/mach-picoxcell/io.c b/arch/arm/mach-picoxcell/io.c
new file mode 100644
index 0000000..5c61dbe
--- /dev/null
+++ b/arch/arm/mach-picoxcell/io.c
@@ -0,0 +1,49 @@
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+
+#include <asm/mach/map.h>
+
+#include <mach/hardware.h>
+
+static struct map_desc __initdata picoxcell_io_desc[] = {
+ {
+ .virtual = PHYS_TO_IO(PICOXCELL_PERIPH_BASE),
+ .pfn = __phys_to_pfn(PICOXCELL_PERIPH_BASE),
+ .length = PICOXCELL_PERIPH_LENGTH,
+ .type = MT_DEVICE,
+ },
+ {
+ .virtual = SRAM_VIRT,
+ .pfn = __phys_to_pfn(SRAM_BASE),
+ .length = SRAM_SIZE,
+ .type = MT_MEMORY,
+ },
+};
+
+void __init picoxcell_map_io(void)
+{
+ iotable_init(picoxcell_io_desc, ARRAY_SIZE(picoxcell_io_desc));
+}
+
+/*
+ * Intercept ioremap() requests for addresses in our fixed mapping regions.
+ */
+void __iomem *picoxcell_ioremap(unsigned long p, size_t size, unsigned int type)
+{
+ if (p >= PICOXCELL_PERIPH_BASE &&
+ p < PICOXCELL_PERIPH_BASE + PICOXCELL_PERIPH_LENGTH)
+ return IO_ADDRESS(p);
+
+ return __arm_ioremap_caller(p, size, type, __builtin_return_address(0));
+}
+EXPORT_SYMBOL(picoxcell_ioremap);
+
+void picoxcell_iounmap(volatile void __iomem *addr)
+{
+ unsigned long virt = (unsigned long)addr;
+
+ if (virt >= VMALLOC_START && virt < VMALLOC_END)
+ __iounmap(addr);
+}
+EXPORT_SYMBOL(picoxcell_iounmap);
diff --git a/arch/arm/mach-picoxcell/picoxcell_core.c b/arch/arm/mach-picoxcell/picoxcell_core.c
new file mode 100644
index 0000000..a0db3fd
--- /dev/null
+++ b/arch/arm/mach-picoxcell/picoxcell_core.c
@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2010 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * All enquiries to [email protected]
+ */
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+
+#include <asm/hardware/vic.h>
+#include <asm/mach-types.h>
+
+#include <mach/hardware.h>
+
+#include "picoxcell_core.h"
+#include "soc.h"
+
+static const struct picoxcell_timer picoxcell_timers[] = {
+ {
+ .name = "timer0",
+ .type = TIMER_TYPE_TIMER,
+ .base = PICOXCELL_TIMER_BASE + 0 * TIMER_SPACING,
+ .irq = IRQ_TIMER0,
+ },
+ {
+ .name = "timer1",
+ .type = TIMER_TYPE_TIMER,
+ .base = PICOXCELL_TIMER_BASE + 1 * TIMER_SPACING,
+ .irq = IRQ_TIMER1,
+ },
+ {
+ .name = "rtc",
+ .type = TIMER_TYPE_RTC,
+ .base = PICOXCELL_RTCLK_BASE,
+ .irq = IRQ_RTC,
+ },
+};
+
+static struct picoxcell_soc generic_soc = {
+ .timers = picoxcell_timers,
+ .nr_timers = ARRAY_SIZE(picoxcell_timers),
+};
+
+struct picoxcell_soc *picoxcell_get_soc(void)
+{
+ return &generic_soc;
+}
+
+void __init picoxcell_init_irq(void)
+{
+ u32 vic0_resume_sources =
+ (1 << (IRQ_AXI2PICO8 & 31)) |
+ (1 << (IRQ_EMAC & 31)) |
+ (1 << (IRQ_WDG & 31));
+
+ vic_init(IO_ADDRESS(PICOXCELL_VIC0_BASE), 32, 0xFFFFFFFE,
+ vic0_resume_sources);
+ vic_init(IO_ADDRESS(PICOXCELL_VIC1_BASE), 0, 0x7FF, 0);
+}
+
+static const char *picoxcell_get_partname(void)
+{
+ unsigned long dev_id = axi2cfg_readl(AXI2CFG_DEVICE_ID_REG_OFFSET);
+ const char *part = "<unknown>";
+
+ if (dev_id == 0x8003)
+ part = "pc302";
+ else if (dev_id == 0x8007)
+ part = "pc312";
+ else if (dev_id == 0x20)
+ part = "pc313";
+ else if (dev_id == 0x21)
+ part = "pc323";
+ else if (dev_id == 0x22)
+ part = "pc333";
+
+ return part;
+}
+
+static inline unsigned long picoxcell_get_revision(void)
+{
+ return axi2cfg_readl(AXI2CFG_REVISION_ID_REG_OFFSET);
+}
+
+static void report_chipinfo(void)
+{
+ const char *part = picoxcell_get_partname();
+ unsigned long revision = picoxcell_get_revision();
+
+ pr_info("Picochip picoXcell device: %s revision %lu\n", part, revision);
+}
+
+void __init picoxcell_init_early(void)
+{
+ axi2cfg_init();
+}
+
+void __init picoxcell_core_init(void)
+{
+ report_chipinfo();
+}
diff --git a/arch/arm/mach-picoxcell/picoxcell_core.h b/arch/arm/mach-picoxcell/picoxcell_core.h
new file mode 100644
index 0000000..299c512
--- /dev/null
+++ b/arch/arm/mach-picoxcell/picoxcell_core.h
@@ -0,0 +1,22 @@
+/*
+ * linux/arch/arm/mach-picoxcell/picoxcell_core.h
+ *
+ * Copyright (c) 2010 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * All enquiries to [email protected]
+ */
+#ifndef __ASM_ARCH_PICOXCELL_CORE_H__
+#define __ASM_ARCH_PICOXCELL_CORE_H__
+
+struct picoxcell_soc;
+
+extern void picoxcell_init_early(void);
+extern void picoxcell_core_init(void);
+extern void picoxcell_init_irq(void);
+extern void picoxcell_map_io(void);
+
+#endif /* __ASM_ARCH_PICOXCELL_CORE_H__ */
diff --git a/arch/arm/mach-picoxcell/soc.h b/arch/arm/mach-picoxcell/soc.h
new file mode 100644
index 0000000..1422216
--- /dev/null
+++ b/arch/arm/mach-picoxcell/soc.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2010 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * All enquiries to [email protected]
+ */
+#ifndef __PICOXCELL_SOC_H__
+#define __PICOXCELL_SOC_H__
+
+enum timer_type {
+ TIMER_TYPE_RTC,
+ TIMER_TYPE_TIMER,
+};
+
+struct picoxcell_timer {
+ const char *name;
+ enum timer_type type;
+ unsigned long base;
+ int irq;
+};
+
+struct picoxcell_soc {
+ const struct picoxcell_timer *timers;
+ int nr_timers;
+};
+
+extern struct picoxcell_soc *picoxcell_get_soc(void);
+
+#endif /* __PICOXCELL_SOC_H__ */
--
1.7.4
Hi Russell,
On Tue, Mar 08, 2011 at 03:06:52PM +0000, Jamie Iles wrote:
> I've respun this patch series to move the DEBUG_LL 32-bit helpers into
> debug-macro.S like mach-davinci does and include the basic clk stuff so
> that we can build with drivers that want CLK support.
>
> This patch series takes us to a login console over serial on both PC3X2
> and PC3X3 devices on the PC7302 board booted with NOR flash. I plan on
> adding support for the next generation of soc, PM, cpufreq etc at a
> later date once these patches are merged but figured it would be good to
> start with a nice stable base.
>
> Any feedback would be very much appreciated!
>
> Thanks,
>
> Jamie Iles (5):
>
> picoxcell: support for Picochip picoXcell SoC
> picoxcell: support for the common system timers
> picoxcell: common SoC peripheral support
> picoxcell: basic clk infrastructure
> picoxcell: support for the PC7302 development board
I was wondering if there was anything I could do to help move this
series along a bit. Whilst I haven't had much direct feedback to these
patches I have tried to take on board any feedback to other machine
patches where relevant.
How about adding a tree to linux-next?
Jamie