The first patch add generic functionnality to w1_io for Resume Command [A5h]
lots of slaves support. I found it useful for multi-commands/reset workflows
with the same slave on a multi-slave bus.
This DS2408 w1 slave driver is not complete for all the
features of the chip, but its sufficient if you use it as
a simple IO expander. Enjoy!
The ds1wm had Kconfig dependencies towards ARM && HAVE_CLK. I took them
out since I was using the ds1wm on an x86_64 platform (ds1wm in a FPGA through
pcie) and found them irrelevant.
The clock freq/divisors at the top of ds1wm.c did not have the MSB set to 1.
This bit is CLK_EN which turns the whole prescaler and dividers on. The driver
never mentionned this bit either, so I just included this bit right in the table
entries. I also took the liberty to add a couple of entries to the table. The
spec doesn't explicitely mentions these possibilities but the description and
examination of the core shows the prescalers & dividers can be used for more
than the table explicitely shows. The table I enlarged still doesn't cover all
possibilities, but it's a good start.
I also made a few tweaks to a couple of the read and write algorithms which
made sense while I had my head very deep in the ds1wm documentation. We stressed
it a lot with 10+ slaves on the bus, many ds2408, ds2431 and ds2433 at the same
time doing extensive interaction. It proved quite stable in our production
environment.
This adds multi-slave support of the w1 bus for the
ds1wm Synthesizable 1-Wire Bus Master.
Also many fixes and tweaks based on the rev3 of the datasheet
http://datasheets.maxim-ic.com/en/ds/DS1WM.pdf
Signed-off-by: Jean-François Dagenais <[email protected]>
---
:100644 100644 80b3b12... e3739df... M drivers/w1/masters/Kconfig
:100644 100644 6b85e7f... 949d38f... M drivers/w1/masters/ds1wm.c
drivers/w1/masters/Kconfig | 2 +-
drivers/w1/masters/ds1wm.c | 321 ++++++++++++++++++++++++++++++--------------
2 files changed, 220 insertions(+), 103 deletions(-)
diff --git a/drivers/w1/masters/Kconfig b/drivers/w1/masters/Kconfig
index 80b3b12..e3739df 100644
--- a/drivers/w1/masters/Kconfig
+++ b/drivers/w1/masters/Kconfig
@@ -42,7 +42,7 @@ config W1_MASTER_MXC
config W1_MASTER_DS1WM
tristate "Maxim DS1WM 1-wire busmaster"
- depends on W1 && ARM && HAVE_CLK
+ depends on W1
help
Say Y here to enable the DS1WM 1-wire driver, such as that
in HP iPAQ devices like h5xxx, h2200, and ASIC3-based like
diff --git a/drivers/w1/masters/ds1wm.c b/drivers/w1/masters/ds1wm.c
index 6b85e7f..949d38f 100644
--- a/drivers/w1/masters/ds1wm.c
+++ b/drivers/w1/masters/ds1wm.c
@@ -33,6 +33,7 @@
#define DS1WM_INT 0x02 /* R/W interrupt status */
#define DS1WM_INT_EN 0x03 /* R/W interrupt enable */
#define DS1WM_CLKDIV 0x04 /* R/W 5 bits of divisor and pre-scale */
+#define DS1WM_CNTRL 0x05 /* R/W master control register (not used yet) */
#define DS1WM_CMD_1W_RESET (1 << 0) /* force reset on 1-wire bus */
#define DS1WM_CMD_SRA (1 << 1) /* enable Search ROM accelerator mode */
@@ -56,6 +57,7 @@
#define DS1WM_INTEN_ERSRF (1 << 5) /* enable rx shift register full int */
#define DS1WM_INTEN_DQO (1 << 6) /* enable direct bus driving ops */
+#define DS1WM_INTEN_NOT_IAS (~DS1WM_INTEN_IAS) /* all but INTR active state */
#define DS1WM_TIMEOUT (HZ * 5)
@@ -63,41 +65,50 @@ static struct {
unsigned long freq;
unsigned long divisor;
} freq[] = {
- { 4000000, 0x8 },
- { 5000000, 0x2 },
- { 6000000, 0x5 },
- { 7000000, 0x3 },
- { 8000000, 0xc },
- { 10000000, 0x6 },
- { 12000000, 0x9 },
- { 14000000, 0x7 },
- { 16000000, 0x10 },
- { 20000000, 0xa },
- { 24000000, 0xd },
- { 28000000, 0xb },
- { 32000000, 0x14 },
- { 40000000, 0xe },
- { 48000000, 0x11 },
- { 56000000, 0xf },
- { 64000000, 0x18 },
- { 80000000, 0x12 },
- { 96000000, 0x15 },
- { 112000000, 0x13 },
- { 128000000, 0x1c },
+ { 1000000, 0x80 },
+ { 2000000, 0x84 },
+ { 3000000, 0x81 },
+ { 4000000, 0x88 },
+ { 5000000, 0x82 },
+ { 6000000, 0x85 },
+ { 7000000, 0x83 },
+ { 8000000, 0x8c },
+ { 10000000, 0x86 },
+ { 12000000, 0x89 },
+ { 14000000, 0x87 },
+ { 16000000, 0x90 },
+ { 20000000, 0x8a },
+ { 24000000, 0x8d },
+ { 28000000, 0x8b },
+ { 32000000, 0x94 },
+ { 40000000, 0x8e },
+ { 48000000, 0x91 },
+ { 56000000, 0x8f },
+ { 64000000, 0x98 },
+ { 80000000, 0x92 },
+ { 96000000, 0x95 },
+ { 112000000, 0x93 },
+ { 128000000, 0x9c },
+/* you can continue this table, consult the OPERATION - CLOCK DIVISOR
+ section of the ds1wm spec sheet. */
};
struct ds1wm_data {
- void __iomem *map;
- int bus_shift; /* # of shifts to calc register offsets */
+ void __iomem *map;
+ int bus_shift; /* # of shifts to calc register offsets */
struct platform_device *pdev;
- struct mfd_cell *cell;
- int irq;
- int active_high;
- int slave_present;
- void *reset_complete;
- void *read_complete;
- void *write_complete;
- u8 read_byte; /* last byte received */
+ struct mfd_cell *cell;
+ int irq;
+ int slave_present;
+ void *reset_complete;
+ void *read_complete;
+ void *write_complete;
+ int read_error;
+ /* last byte received */
+ u8 read_byte;
+ /* byte to write that makes all intr disabled, */
+ /* considering active_state (IAS) (optimization) */
+ u8 int_en_reg_none;
};
static inline void ds1wm_write_register(struct ds1wm_data *ds1wm_data, u32 reg,
@@ -115,23 +126,39 @@ static inline u8 ds1wm_read_register(struct ds1wm_data *ds1wm_data, u32 reg)
static irqreturn_t ds1wm_isr(int isr, void *data)
{
struct ds1wm_data *ds1wm_data = data;
- u8 intr = ds1wm_read_register(ds1wm_data, DS1WM_INT);
+ u8 intr;
+ u8 inten = ds1wm_read_register(ds1wm_data, DS1WM_INT_EN);
+ /* if no bits are set in int enable register (except the IAS)
+ than go no further, reading the regs below has side effects */
+ if (!(inten & DS1WM_INTEN_NOT_IAS))
+ return IRQ_NONE;
- ds1wm_data->slave_present = (intr & DS1WM_INT_PDR) ? 0 : 1;
+ ds1wm_write_register(ds1wm_data,
+ DS1WM_INT_EN, ds1wm_data->int_en_reg_none);
- if ((intr & DS1WM_INT_PD) && ds1wm_data->reset_complete)
- complete(ds1wm_data->reset_complete);
+ /* this read action clears the INTR and certain flags in ds1wm */
+ intr = ds1wm_read_register(ds1wm_data, DS1WM_INT);
- if ((intr & DS1WM_INT_TSRE) && ds1wm_data->write_complete)
- complete(ds1wm_data->write_complete);
+ ds1wm_data->slave_present = (intr & DS1WM_INT_PDR) ? 0 : 1;
+ if ((intr & DS1WM_INT_TSRE) && ds1wm_data->write_complete) {
+ inten &= ~DS1WM_INTEN_ETMT;
+ complete(ds1wm_data->write_complete);
+ }
if (intr & DS1WM_INT_RBF) {
+ /* this read clears the RBF flag */
ds1wm_data->read_byte = ds1wm_read_register(ds1wm_data,
- DS1WM_DATA);
+ DS1WM_DATA);
+ inten &= ~DS1WM_INTEN_ERBF;
if (ds1wm_data->read_complete)
complete(ds1wm_data->read_complete);
}
+ if ((intr & DS1WM_INT_PD) && ds1wm_data->reset_complete) {
+ inten &= ~DS1WM_INTEN_EPD;
+ complete(ds1wm_data->reset_complete);
+ }
+ ds1wm_write_register(ds1wm_data, DS1WM_INT_EN, inten);
return IRQ_HANDLED;
}
@@ -142,33 +169,19 @@ static int ds1wm_reset(struct ds1wm_data *ds1wm_data)
ds1wm_data->reset_complete = &reset_done;
+ /* enable Presence detect only */
ds1wm_write_register(ds1wm_data, DS1WM_INT_EN, DS1WM_INTEN_EPD |
- (ds1wm_data->active_high ? DS1WM_INTEN_IAS : 0));
+ ds1wm_data->int_en_reg_none);
ds1wm_write_register(ds1wm_data, DS1WM_CMD, DS1WM_CMD_1W_RESET);
timeleft = wait_for_completion_timeout(&reset_done, DS1WM_TIMEOUT);
ds1wm_data->reset_complete = NULL;
if (!timeleft) {
- dev_err(&ds1wm_data->pdev->dev, "reset failed\n");
+ dev_err(&ds1wm_data->pdev->dev, "reset failed, timed out\n");
return 1;
}
- /* Wait for the end of the reset. According to the specs, the time
- * from when the interrupt is asserted to the end of the reset is:
- * tRSTH - tPDH - tPDL - tPDI
- * 625 us - 60 us - 240 us - 100 ns = 324.9 us
- *
- * We'll wait a bit longer just to be sure.
- * Was udelay(500), but if it is going to busywait the cpu that long,
- * might as well come back later.
- */
- msleep(1);
-
- ds1wm_write_register(ds1wm_data, DS1WM_INT_EN,
- DS1WM_INTEN_ERBF | DS1WM_INTEN_ETMT | DS1WM_INTEN_EPD |
- (ds1wm_data->active_high ? DS1WM_INTEN_IAS : 0));
-
if (!ds1wm_data->slave_present) {
dev_dbg(&ds1wm_data->pdev->dev, "reset: no devices found\n");
return 1;
@@ -179,26 +192,47 @@ static int ds1wm_reset(struct ds1wm_data *ds1wm_data)
static int ds1wm_write(struct ds1wm_data *ds1wm_data, u8 data)
{
+ unsigned long timeleft;
DECLARE_COMPLETION_ONSTACK(write_done);
ds1wm_data->write_complete = &write_done;
+ ds1wm_write_register(ds1wm_data, DS1WM_INT_EN,
+ ds1wm_data->int_en_reg_none | DS1WM_INTEN_ETMT);
+
ds1wm_write_register(ds1wm_data, DS1WM_DATA, data);
- wait_for_completion_timeout(&write_done, DS1WM_TIMEOUT);
+ timeleft = wait_for_completion_timeout(&write_done, DS1WM_TIMEOUT);
+
ds1wm_data->write_complete = NULL;
+ if (!timeleft) {
+ dev_err(&ds1wm_data->pdev->dev, "write failed, timed out\n");
+ return -ETIMEDOUT;
+ }
return 0;
}
-static int ds1wm_read(struct ds1wm_data *ds1wm_data, unsigned char write_data)
+static u8 ds1wm_read(struct ds1wm_data *ds1wm_data, unsigned char write_data)
{
+ unsigned long timeleft;
+ u8 intEnable = DS1WM_INTEN_ERBF | ds1wm_data->int_en_reg_none;
DECLARE_COMPLETION_ONSTACK(read_done);
+
+ ds1wm_read_register(ds1wm_data, DS1WM_DATA);
+
ds1wm_data->read_complete = &read_done;
+ ds1wm_write_register(ds1wm_data, DS1WM_INT_EN, intEnable);
- ds1wm_write(ds1wm_data, write_data);
- wait_for_completion_timeout(&read_done, DS1WM_TIMEOUT);
- ds1wm_data->read_complete = NULL;
+ ds1wm_write_register(ds1wm_data, DS1WM_DATA, write_data);
+ timeleft = wait_for_completion_timeout(&read_done, DS1WM_TIMEOUT);
+ ds1wm_data->read_complete = NULL;
+ if (!timeleft) {
+ dev_err(&ds1wm_data->pdev->dev, "read failed, timed out\n");
+ ds1wm_data->read_error = -ETIMEDOUT;
+ return 0xFF;
+ }
+ ds1wm_data->read_error = 0;
return ds1wm_data->read_byte;
}
@@ -206,8 +240,8 @@ static int ds1wm_find_divisor(int gclk)
{
int i;
- for (i = 0; i < ARRAY_SIZE(freq); i++)
- if (gclk <= freq[i].freq)
+ for (i = ARRAY_SIZE(freq)-1; i >= 0; --i)
+ if (gclk >= freq[i].freq)
return freq[i].divisor;
return 0;
@@ -222,6 +256,8 @@ static void ds1wm_up(struct ds1wm_data *ds1wm_data)
ds1wm_data->cell->enable(ds1wm_data->pdev);
divisor = ds1wm_find_divisor(plat->clock_rate);
+ dev_dbg(&ds1wm_data->pdev->dev,
+ "found divisor 0x%x for clock %d\n", divisor, plat->clock_rate);
if (divisor == 0) {
dev_err(&ds1wm_data->pdev->dev,
"no suitable divisor for %dHz clock\n",
@@ -242,7 +278,7 @@ static void ds1wm_down(struct ds1wm_data *ds1wm_data)
/* Disable interrupts. */
ds1wm_write_register(ds1wm_data, DS1WM_INT_EN,
- ds1wm_data->active_high ? DS1WM_INTEN_IAS : 0);
+ ds1wm_data->int_en_reg_none);
if (ds1wm_data->cell->disable)
ds1wm_data->cell->disable(ds1wm_data->pdev);
@@ -279,41 +315,121 @@ static void ds1wm_search(void *data, struct w1_master *master_dev,
{
struct ds1wm_data *ds1wm_data = data;
int i;
- unsigned long long rom_id;
-
- /* XXX We need to iterate for multiple devices per the DS1WM docs.
- * See http://www.maxim-ic.com/appnotes.cfm/appnote_number/120. */
- if (ds1wm_reset(ds1wm_data))
- return;
-
- ds1wm_write(ds1wm_data, search_type);
- ds1wm_write_register(ds1wm_data, DS1WM_CMD, DS1WM_CMD_SRA);
-
- for (rom_id = 0, i = 0; i < 16; i++) {
-
- unsigned char resp, r, d;
-
- resp = ds1wm_read(ds1wm_data, 0x00);
-
- r = ((resp & 0x02) >> 1) |
- ((resp & 0x08) >> 2) |
- ((resp & 0x20) >> 3) |
- ((resp & 0x80) >> 4);
-
- d = ((resp & 0x01) >> 0) |
- ((resp & 0x04) >> 1) |
- ((resp & 0x10) >> 2) |
- ((resp & 0x40) >> 3);
-
- rom_id |= (unsigned long long) r << (i * 4);
-
- }
- dev_dbg(&ds1wm_data->pdev->dev, "found 0x%08llX\n", rom_id);
-
- ds1wm_write_register(ds1wm_data, DS1WM_CMD, ~DS1WM_CMD_SRA);
- ds1wm_reset(ds1wm_data);
-
- slave_found(master_dev, rom_id);
+ int ms_discrep_bit = -1;
+ u64 r = 0; /* holds the progress of the search */
+ u64 r_prime, d;
+ unsigned slaves_found = 0;
+ unsigned int pass = 0;
+
+ dev_dbg(&ds1wm_data->pdev->dev, "search begin\n");
+ while (true) {
+ ++pass;
+ if (pass > 100) {
+ dev_dbg(&ds1wm_data->pdev->dev,
+ "too many attempts (100), search aborted\n");
+ return;
+ }
+
+ if (ds1wm_reset(ds1wm_data)) {
+ dev_dbg(&ds1wm_data->pdev->dev,
+ "pass: %d reset error (or no slaves)\n", pass);
+ break;
+ }
+
+ dev_dbg(&ds1wm_data->pdev->dev,
+ "pass: %d r : %0#18llx writing SEARCH_ROM\n", pass, r);
+ ds1wm_write(ds1wm_data, search_type);
+ dev_dbg(&ds1wm_data->pdev->dev,
+ "pass: %d entering ASM\n", pass);
+ ds1wm_write_register(ds1wm_data, DS1WM_CMD, DS1WM_CMD_SRA);
+ dev_dbg(&ds1wm_data->pdev->dev,
+ "pass: %d begining nibble loop\n", pass);
+
+ r_prime = 0;
+ d = 0;
+ /* we work one nibble at a time */
+ /* each nibble is interleaved to form a byte */
+ for (i = 0; i < 16; i++) {
+
+ unsigned char resp, _r, _r_prime, _d;
+
+ _r = (r >> (4*i)) & 0xf;
+ _r = ((_r & 0x1) << 1) |
+ ((_r & 0x2) << 2) |
+ ((_r & 0x4) << 3) |
+ ((_r & 0x8) << 4);
+
+ /* writes _r, then reads back: */
+ resp = ds1wm_read(ds1wm_data, _r);
+
+ if (ds1wm_data->read_error) {
+ dev_err(&ds1wm_data->pdev->dev,
+ "pass: %d nibble: %d read error\n", pass, i);
+ break;
+ }
+
+ _r_prime = ((resp & 0x02) >> 1) |
+ ((resp & 0x08) >> 2) |
+ ((resp & 0x20) >> 3) |
+ ((resp & 0x80) >> 4);
+
+ _d = ((resp & 0x01) >> 0) |
+ ((resp & 0x04) >> 1) |
+ ((resp & 0x10) >> 2) |
+ ((resp & 0x40) >> 3);
+
+ r_prime |= (unsigned long long) _r_prime << (i * 4);
+ d |= (unsigned long long) _d << (i * 4);
+
+ }
+ if (ds1wm_data->read_error) {
+ dev_err(&ds1wm_data->pdev->dev,
+ "pass: %d read error, retrying\n", pass);
+ break;
+ }
+ dev_dbg(&ds1wm_data->pdev->dev,
+ "pass: %d r\': %0#18llx d:%0#18llx\n",
+ pass, r_prime, d);
+ dev_dbg(&ds1wm_data->pdev->dev,
+ "pass: %d nibble loop complete, exiting ASM\n", pass);
+ ds1wm_write_register(ds1wm_data, DS1WM_CMD, ~DS1WM_CMD_SRA);
+ dev_dbg(&ds1wm_data->pdev->dev,
+ "pass: %d resetting bus\n", pass);
+ ds1wm_reset(ds1wm_data);
+ if ((r_prime & ((u64)1 << 63)) && (d & ((u64)1 << 63))) {
+ dev_err(&ds1wm_data->pdev->dev,
+ "pass: %d bus error, retrying\n", pass);
+ continue; /* start over */
+ }
+
+
+ dev_dbg(&ds1wm_data->pdev->dev,
+ "pass: %d found %0#18llx\n", pass, r_prime);
+ slave_found(master_dev, r_prime);
+ ++slaves_found;
+ dev_dbg(&ds1wm_data->pdev->dev,
+ "pass: %d complete, preparing next pass\n", pass);
+
+ /* any discrepency found which we already choose the
+ '1' branch is now is now irrelevant we reveal the
+ next branch with this: */
+ d &= ~r;
+ /* find last bit set, i.e. the most signif. bit set */
+ ms_discrep_bit = fls64(d) - 1;
+ dev_dbg(&ds1wm_data->pdev->dev,
+ "pass: %d new d:%0#18llx MS discrep bit:%d\n",
+ pass, d, ms_discrep_bit);
+
+ /* prev_ms_discrep_bit = ms_discrep_bit;
+ prepare for next ROM search: */
+ if (ms_discrep_bit == -1)
+ break;
+
+ r = (r & ~(~0ull << (ms_discrep_bit))) | 1 << ms_discrep_bit;
+ } /* end while true */
+ dev_dbg(&ds1wm_data->pdev->dev,
+ "pass: %d total: %d search done ms d bit pos: %d\n", pass,
+ slaves_found, ms_discrep_bit);
}
/* --------------------------------------------------------------------- */
@@ -370,15 +486,15 @@ static int ds1wm_probe(struct platform_device *pdev)
goto err1;
}
ds1wm_data->irq = res->start;
- ds1wm_data->active_high = plat->active_high;
+ ds1wm_data->int_en_reg_none = (plat->active_high ? DS1WM_INTEN_IAS : 0);
if (res->flags & IORESOURCE_IRQ_HIGHEDGE)
set_irq_type(ds1wm_data->irq, IRQ_TYPE_EDGE_RISING);
if (res->flags & IORESOURCE_IRQ_LOWEDGE)
set_irq_type(ds1wm_data->irq, IRQ_TYPE_EDGE_FALLING);
- ret = request_irq(ds1wm_data->irq, ds1wm_isr, IRQF_DISABLED,
- "ds1wm", ds1wm_data);
+ ret = request_irq(ds1wm_data->irq, ds1wm_isr,
+ IRQF_DISABLED | IRQF_SHARED, "ds1wm", ds1wm_data);
if (ret)
goto err1;
@@ -465,5 +581,6 @@ module_exit(ds1wm_exit);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Szabolcs Gyurko <[email protected]>, "
- "Matt Reimer <[email protected]>");
+ "Matt Reimer <[email protected]>,"
+ "Jean-Francois Dagenais <[email protected]>");
MODULE_DESCRIPTION("DS1WM w1 busmaster driver");
--
1.7.4.1
This DS2408 w1 slave driver is not complete for all the
features of the chip, but its sufficient if you use it as
a simple IO expander.
Signed-off-by: Jean-François Dagenais <[email protected]>
---
:100644 100644 f0c9096... cd1b724... M drivers/w1/slaves/Kconfig
:100644 100644 3c76350... 75e3913... M drivers/w1/slaves/Makefile
:000000 100644 0000000... 3547e80... A drivers/w1/slaves/w1_ds2408.c
:100644 100644 f3b636d... 7513759... M drivers/w1/w1_family.h
drivers/w1/slaves/Kconfig | 7 +
drivers/w1/slaves/Makefile | 1 +
drivers/w1/slaves/w1_ds2408.c | 402 +++++++++++++++++++++++++++++++++++++++++
drivers/w1/w1_family.h | 1 +
4 files changed, 411 insertions(+), 0 deletions(-)
diff --git a/drivers/w1/slaves/Kconfig b/drivers/w1/slaves/Kconfig
index f0c9096..cd1b724 100644
--- a/drivers/w1/slaves/Kconfig
+++ b/drivers/w1/slaves/Kconfig
@@ -16,6 +16,13 @@ config W1_SLAVE_SMEM
Say Y here if you want to connect 1-wire
simple 64bit memory rom(ds2401/ds2411/ds1990*) to your wire.
+config W1_SLAVE_DS2408
+ tristate "8-Channel Addressable Switch (IO Expander) 0x29 family support (DS2408)"
+ help
+ Say Y here if you want to use a 1-wire
+
+ DS2408 8-Channel Addressable Switch device support
+
config W1_SLAVE_DS2423
tristate "Counter 1-wire device (DS2423)"
select CRC16
diff --git a/drivers/w1/slaves/Makefile b/drivers/w1/slaves/Makefile
index 3c76350..75e3913 100644
--- a/drivers/w1/slaves/Makefile
+++ b/drivers/w1/slaves/Makefile
@@ -4,6 +4,7 @@
obj-$(CONFIG_W1_SLAVE_THERM) += w1_therm.o
obj-$(CONFIG_W1_SLAVE_SMEM) += w1_smem.o
+obj-$(CONFIG_W1_SLAVE_DS2408) += w1_ds2408.o
obj-$(CONFIG_W1_SLAVE_DS2423) += w1_ds2423.o
obj-$(CONFIG_W1_SLAVE_DS2431) += w1_ds2431.o
obj-$(CONFIG_W1_SLAVE_DS2433) += w1_ds2433.o
diff --git a/drivers/w1/slaves/w1_ds2408.c b/drivers/w1/slaves/w1_ds2408.c
new file mode 100644
index 0000000..3547e80
--- /dev/null
+++ b/drivers/w1/slaves/w1_ds2408.c
@@ -0,0 +1,402 @@
+/*
+ * w1_ds2408.c - w1 family 29 (DS2408) driver
+ *
+ * Copyright (c) 2010 Jean-Francois Dagenais <[email protected]>
+ *
+ * This source code is licensed under the GNU General Public License,
+ * Version 2. See the file COPYING for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/device.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+
+#include "../w1.h"
+#include "../w1_int.h"
+#include "../w1_family.h"
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Jean-Francois Dagenais <[email protected]>");
+MODULE_DESCRIPTION("w1 family 29 driver for DS2408 8 Pin IO");
+
+
+#define W1_F29_RETRIES 3
+
+#define W1_F29_REG_LOGIG_STATE 0x88 /* R */
+#define W1_F29_REG_OUTPUT_LATCH_STATE 0x89 /* R */
+#define W1_F29_REG_ACTIVITY_LATCH_STATE 0x8A /* R */
+#define W1_F29_REG_COND_SEARCH_SELECT_MASK 0x8B /* RW */
+#define W1_F29_REG_COND_SEARCH_POL_SELECT 0x8C /* RW */
+#define W1_F29_REG_CONTROL_AND_STATUS 0x8D /* RW */
+
+#define W1_F29_FUNC_READ_PIO_REGS 0xF0
+#define W1_F29_FUNC_CHANN_ACCESS_READ 0xF5
+#define W1_F29_FUNC_CHANN_ACCESS_WRITE 0x5A
+/* also used to write the control/status reg (0x8D): */
+#define W1_F29_FUNC_WRITE_COND_SEARCH_REG 0xCC
+#define W1_F29_FUNC_RESET_ACTIVITY_LATCHES 0xC3
+
+#define W1_F29_SUCCESS_CONFIRM_BYTE 0xAA
+
+static int _read_reg(struct w1_slave *sl, u8 address, unsigned char* buf)
+{
+ u8 wrbuf[3];
+ dev_dbg(&sl->dev,
+ "Reading with slave: %p, reg addr: %0#4x, buff addr: %p",
+ sl, (unsigned int)address, buf);
+
+ if (!buf)
+ return -EINVAL;
+
+ mutex_lock(&sl->master->mutex);
+ dev_dbg(&sl->dev, "mutex locked");
+
+ if (w1_reset_select_slave(sl)) {
+ mutex_unlock(&sl->master->mutex);
+ return -EIO;
+ }
+
+ wrbuf[0] = W1_F29_FUNC_READ_PIO_REGS;
+ wrbuf[1] = address;
+ wrbuf[2] = 0;
+ w1_write_block(sl->master, wrbuf, 3);
+ *buf = w1_read_8(sl->master);
+
+ mutex_unlock(&sl->master->mutex);
+ dev_dbg(&sl->dev, "mutex unlocked");
+ return 1;
+}
+
+static ssize_t w1_f29_read_state(
+ struct file *filp, struct kobject *kobj,
+ struct bin_attribute *bin_attr,
+ char *buf, loff_t off, size_t count)
+{
+ dev_dbg(&kobj_to_w1_slave(kobj)->dev,
+ "Reading %s kobj: %p, off: %0#10x, count: %lu, buff addr: %p",
+ bin_attr->attr.name, kobj, (unsigned int)off, count, buf);
+ if (count != 1 || off != 0)
+ return -EFAULT;
+ return _read_reg(kobj_to_w1_slave(kobj), W1_F29_REG_LOGIG_STATE, buf);
+}
+
+static ssize_t w1_f29_read_output(
+ struct file *filp, struct kobject *kobj,
+ struct bin_attribute *bin_attr,
+ char *buf, loff_t off, size_t count)
+{
+ dev_dbg(&kobj_to_w1_slave(kobj)->dev,
+ "Reading %s kobj: %p, off: %0#10x, count: %lu, buff addr: %p",
+ bin_attr->attr.name, kobj, (unsigned int)off, count, buf);
+ if (count != 1 || off != 0)
+ return -EFAULT;
+ return _read_reg(kobj_to_w1_slave(kobj),
+ W1_F29_REG_OUTPUT_LATCH_STATE, buf);
+}
+
+static ssize_t w1_f29_read_activity(
+ struct file *filp, struct kobject *kobj,
+ struct bin_attribute *bin_attr,
+ char *buf, loff_t off, size_t count)
+{
+ dev_dbg(&kobj_to_w1_slave(kobj)->dev,
+ "Reading %s kobj: %p, off: %0#10x, count: %lu, buff addr: %p",
+ bin_attr->attr.name, kobj, (unsigned int)off, count, buf);
+ if (count != 1 || off != 0)
+ return -EFAULT;
+ return _read_reg(kobj_to_w1_slave(kobj),
+ W1_F29_REG_ACTIVITY_LATCH_STATE, buf);
+}
+
+static ssize_t w1_f29_read_cond_search_mask(
+ struct file *filp, struct kobject *kobj,
+ struct bin_attribute *bin_attr,
+ char *buf, loff_t off, size_t count)
+{
+ dev_dbg(&kobj_to_w1_slave(kobj)->dev,
+ "Reading %s kobj: %p, off: %0#10x, count: %lu, buff addr: %p",
+ bin_attr->attr.name, kobj, (unsigned int)off, count, buf);
+ if (count != 1 || off != 0)
+ return -EFAULT;
+ return _read_reg(kobj_to_w1_slave(kobj),
+ W1_F29_REG_COND_SEARCH_SELECT_MASK, buf);
+}
+
+static ssize_t w1_f29_read_cond_search_polarity(
+ struct file *filp, struct kobject *kobj,
+ struct bin_attribute *bin_attr,
+ char *buf, loff_t off, size_t count)
+{
+ if (count != 1 || off != 0)
+ return -EFAULT;
+ return _read_reg(kobj_to_w1_slave(kobj),
+ W1_F29_REG_COND_SEARCH_POL_SELECT, buf);
+}
+
+static ssize_t w1_f29_read_status_control(
+ struct file *filp, struct kobject *kobj,
+ struct bin_attribute *bin_attr,
+ char *buf, loff_t off, size_t count)
+{
+ if (count != 1 || off != 0)
+ return -EFAULT;
+ return _read_reg(kobj_to_w1_slave(kobj),
+ W1_F29_REG_CONTROL_AND_STATUS, buf);
+}
+
+
+
+
+static ssize_t w1_f29_write_output(
+ struct file *filp, struct kobject *kobj,
+ struct bin_attribute *bin_attr,
+ char *buf, loff_t off, size_t count)
+{
+ struct w1_slave *sl = kobj_to_w1_slave(kobj);
+ u8 w1_buf[3];
+ u8 readBack;
+ unsigned int retries = W1_F29_RETRIES;
+
+ if (count != 1 || off != 0)
+ return -EFAULT;
+
+ dev_dbg(&sl->dev, "locking mutex for write_output");
+ mutex_lock(&sl->master->mutex);
+ dev_dbg(&sl->dev, "mutex locked");
+
+ if (w1_reset_select_slave(sl))
+ goto error;
+
+ while (retries--) {
+ w1_buf[0] = W1_F29_FUNC_CHANN_ACCESS_WRITE;
+ w1_buf[1] = *buf;
+ w1_buf[2] = ~(*buf);
+ w1_write_block(sl->master, w1_buf, 3);
+
+ readBack = w1_read_8(sl->master);
+ /* here the master could read another byte which
+ would be the PIO reg (the actual pin logic state)
+ since in this driver we don't know which pins are
+ in and outs, there's no value to read the state and
+ compare. with (*buf) so end this command abruptly: */
+ if (w1_reset_resume_command(sl->master))
+ goto error;
+
+ if (readBack != 0xAA) {
+ /* try again, the slave is ready for a command */
+ continue;
+ }
+
+ /* go read back the output latches */
+ /* (the direct effect of the write above) */
+ w1_buf[0] = W1_F29_FUNC_READ_PIO_REGS;
+ w1_buf[1] = W1_F29_REG_OUTPUT_LATCH_STATE;
+ w1_buf[2] = 0;
+ w1_write_block(sl->master, w1_buf, 3);
+ /* read the result of the READ_PIO_REGS command */
+ if (w1_read_8(sl->master) == *buf) {
+ /* success! */
+ mutex_unlock(&sl->master->mutex);
+ dev_dbg(&sl->dev,
+ "mutex unlocked, retries:%d", retries);
+ return 1;
+ }
+ }
+error:
+ mutex_unlock(&sl->master->mutex);
+ dev_dbg(&sl->dev, "mutex unlocked in error, retries:%d", retries);
+
+ return -EIO;
+}
+
+
+/**
+ * Writing to the activity file resets the activity latches.
+ */
+static ssize_t w1_f29_write_activity(
+ struct file *filp, struct kobject *kobj,
+ struct bin_attribute *bin_attr,
+ char *buf, loff_t off, size_t count)
+{
+ struct w1_slave *sl = kobj_to_w1_slave(kobj);
+ unsigned int retries = W1_F29_RETRIES;
+
+ if (count != 1 || off != 0)
+ return -EFAULT;
+
+ mutex_lock(&sl->master->mutex);
+
+ if (w1_reset_select_slave(sl))
+ goto error;
+
+ while (retries--) {
+ w1_write_8(sl->master, W1_F29_FUNC_RESET_ACTIVITY_LATCHES);
+ if (w1_read_8(sl->master) == W1_F29_SUCCESS_CONFIRM_BYTE) {
+ mutex_unlock(&sl->master->mutex);
+ return 1;
+ }
+ if (w1_reset_resume_command(sl->master))
+ goto error;
+ }
+
+error:
+ mutex_unlock(&sl->master->mutex);
+ return -EIO;
+}
+
+static ssize_t w1_f29_write_status_control(
+ struct file *filp,
+ struct kobject *kobj,
+ struct bin_attribute *bin_attr,
+ char *buf,
+ loff_t off,
+ size_t count)
+{
+ struct w1_slave *sl = kobj_to_w1_slave(kobj);
+ u8 w1_buf[4];
+ unsigned int retries = W1_F29_RETRIES;
+
+ if (count != 1 || off != 0)
+ return -EFAULT;
+
+ mutex_lock(&sl->master->mutex);
+
+ if (w1_reset_select_slave(sl))
+ goto error;
+
+ while (retries--) {
+ w1_buf[0] = W1_F29_FUNC_WRITE_COND_SEARCH_REG;
+ w1_buf[1] = W1_F29_REG_CONTROL_AND_STATUS;
+ w1_buf[2] = 0;
+ w1_buf[3] = *buf;
+
+ w1_write_block(sl->master, w1_buf, 4);
+ if (w1_reset_resume_command(sl->master))
+ goto error;
+
+ w1_buf[0] = W1_F29_FUNC_READ_PIO_REGS;
+ w1_buf[1] = W1_F29_REG_CONTROL_AND_STATUS;
+ w1_buf[2] = 0;
+
+ w1_write_block(sl->master, w1_buf, 3);
+ if (w1_read_8(sl->master) == *buf) {
+ /* success! */
+ mutex_unlock(&sl->master->mutex);
+ return 1;
+ }
+ }
+error:
+ mutex_unlock(&sl->master->mutex);
+
+ return -EIO;
+}
+
+
+
+#define NB_SYSFS_BIN_FILES 6
+static struct bin_attribute w1_f29_sysfs_bin_files[NB_SYSFS_BIN_FILES] = {
+ {
+ .attr = {
+ .name = "state",
+ .mode = S_IRUGO,
+ },
+ .size = 1,
+ .read = w1_f29_read_state,
+ },
+ {
+ .attr = {
+ .name = "output",
+ .mode = S_IRUGO | S_IWUSR | S_IWGRP,
+ },
+ .size = 1,
+ .read = w1_f29_read_output,
+ .write = w1_f29_write_output,
+ },
+ {
+ .attr = {
+ .name = "activity",
+ .mode = S_IRUGO,
+ },
+ .size = 1,
+ .read = w1_f29_read_activity,
+ .write = w1_f29_write_activity,
+ },
+ {
+ .attr = {
+ .name = "cond_search_mask",
+ .mode = S_IRUGO,
+ },
+ .size = 1,
+ .read = w1_f29_read_cond_search_mask,
+ .write = 0,
+ },
+ {
+ .attr = {
+ .name = "cond_search_polarity",
+ .mode = S_IRUGO,
+ },
+ .size = 1,
+ .read = w1_f29_read_cond_search_polarity,
+ .write = 0,
+ },
+ {
+ .attr = {
+ .name = "status_control",
+ .mode = S_IRUGO | S_IWUSR | S_IWGRP,
+ },
+ .size = 1,
+ .read = w1_f29_read_status_control,
+ .write = w1_f29_write_status_control,
+ }
+};
+
+static int w1_f29_add_slave(struct w1_slave *sl)
+{
+ int err = 0;
+ int i;
+
+ for (i = 0; i < NB_SYSFS_BIN_FILES && !err; ++i)
+ err = sysfs_create_bin_file(
+ &sl->dev.kobj,
+ &(w1_f29_sysfs_bin_files[i]));
+ if (err)
+ while (--i >= 0)
+ sysfs_remove_bin_file(&sl->dev.kobj,
+ &(w1_f29_sysfs_bin_files[i]));
+ return err;
+}
+
+static void w1_f29_remove_slave(struct w1_slave *sl)
+{
+ int i;
+ for (i = NB_SYSFS_BIN_FILES; i <= 0; --i)
+ sysfs_remove_bin_file(&sl->dev.kobj,
+ &(w1_f29_sysfs_bin_files[i]));
+}
+
+static struct w1_family_ops w1_f29_fops = {
+ .add_slave = w1_f29_add_slave,
+ .remove_slave = w1_f29_remove_slave,
+};
+
+static struct w1_family w1_family_29 = {
+ .fid = W1_FAMILY_DS2408,
+ .fops = &w1_f29_fops,
+};
+
+static int __init w1_f29_init(void)
+{
+ return w1_register_family(&w1_family_29);
+}
+
+static void __exit w1_f29_exit(void)
+{
+ w1_unregister_family(&w1_family_29);
+}
+
+module_init(w1_f29_init);
+module_exit(w1_f29_exit);
diff --git a/drivers/w1/w1_family.h b/drivers/w1/w1_family.h
index f3b636d..7513759 100644
--- a/drivers/w1/w1_family.h
+++ b/drivers/w1/w1_family.h
@@ -34,6 +34,7 @@
#define W1_THERM_DS1822 0x22
#define W1_EEPROM_DS2433 0x23
#define W1_THERM_DS18B20 0x28
+#define W1_FAMILY_DS2408 0x29
#define W1_EEPROM_DS2431 0x2D
#define W1_FAMILY_DS2760 0x30
--
1.7.4.1
Signed-off-by: Jean-François Dagenais <[email protected]>
---
:100644 100644 d8a9709... f804eba... M drivers/w1/w1.h
:100644 100644 3ebe972... 8e8b64c... M drivers/w1/w1_io.c
drivers/w1/w1.h | 2 ++
drivers/w1/w1_io.c | 26 ++++++++++++++++++++++++++
2 files changed, 28 insertions(+), 0 deletions(-)
diff --git a/drivers/w1/w1.h b/drivers/w1/w1.h
index d8a9709..f804eba 100644
--- a/drivers/w1/w1.h
+++ b/drivers/w1/w1.h
@@ -55,6 +55,7 @@ struct w1_reg_num
#define W1_READ_ROM 0x33
#define W1_READ_PSUPPLY 0xB4
#define W1_MATCH_ROM 0x55
+#define W1_RESUME_CMD 0xA5
#define W1_SLAVE_ACTIVE 0
@@ -213,6 +214,7 @@ void w1_write_block(struct w1_master *, const u8 *, int);
void w1_touch_block(struct w1_master *, u8 *, int);
u8 w1_read_block(struct w1_master *, u8 *, int);
int w1_reset_select_slave(struct w1_slave *sl);
+int w1_reset_resume_command(struct w1_master *);
void w1_next_pullup(struct w1_master *, int);
static inline struct w1_slave* dev_to_w1_slave(struct device *dev)
diff --git a/drivers/w1/w1_io.c b/drivers/w1/w1_io.c
index 3ebe972..8e8b64c 100644
--- a/drivers/w1/w1_io.c
+++ b/drivers/w1/w1_io.c
@@ -390,6 +390,32 @@ int w1_reset_select_slave(struct w1_slave *sl)
EXPORT_SYMBOL_GPL(w1_reset_select_slave);
/**
+ * When the workflow with a slave amongst many requires several
+ * successive commands a reset between each, this function is similar
+ * to doing a reset then a match ROM for the last matched ROM. The
+ * advantage being that the matched ROM step is skipped in favor of the
+ * resume command. The slave must support the command of course.
+ *
+ * If the bus has only one slave, traditionnaly the match ROM is skipped
+ * and a "SKIP ROM" is done for efficiency. On multi-slave busses, this
+ * doesn't work of course, but the resume command is the next best thing.
+ *
+ * The w1 master lock must be held.
+ *
+ * @param dev the master device
+ */
+int w1_reset_resume_command(struct w1_master *dev)
+{
+ if (w1_reset_bus(dev))
+ return -1;
+
+ /* This will make only the last matched slave perform a skip ROM. */
+ w1_write_8(dev, W1_RESUME_CMD);
+ return 0;
+}
+EXPORT_SYMBOL_GPL(w1_reset_resume_command);
+
+/**
* Put out a strong pull-up of the specified duration after the next write
* operation. Not all hardware supports strong pullups. Hardware that
* doesn't support strong pullups will sleep for the given time after the
--
1.7.4.1
from: Jean-Fran?ois Dagenais <[email protected]>
add generic functionnality to w1_io for Resume Command [A5h]
lots of slaves support. It is useful for multi-commands/reset workflows
with the same slave on a multi-slave bus where reset-skip-ROM is
inappropriate.
Signed-off-by: Jean-Fran?ois Dagenais <[email protected]>
---
:100644 100644 d8a9709... f804eba... M drivers/w1/w1.h
:100644 100644 3ebe972... 8e8b64c... M drivers/w1/w1_io.c
drivers/w1/w1.h | 2 ++
drivers/w1/w1_io.c | 26 ++++++++++++++++++++++++++
2 files changed, 28 insertions(+), 0 deletions(-)
diff --git a/drivers/w1/w1.h b/drivers/w1/w1.h
index d8a9709..f804eba 100644
--- a/drivers/w1/w1.h
+++ b/drivers/w1/w1.h
@@ -55,6 +55,7 @@ struct w1_reg_num
#define W1_READ_ROM 0x33
#define W1_READ_PSUPPLY 0xB4
#define W1_MATCH_ROM 0x55
+#define W1_RESUME_CMD 0xA5
#define W1_SLAVE_ACTIVE 0
@@ -213,6 +214,7 @@ void w1_write_block(struct w1_master *, const u8 *, int);
void w1_touch_block(struct w1_master *, u8 *, int);
u8 w1_read_block(struct w1_master *, u8 *, int);
int w1_reset_select_slave(struct w1_slave *sl);
+int w1_reset_resume_command(struct w1_master *);
void w1_next_pullup(struct w1_master *, int);
static inline struct w1_slave* dev_to_w1_slave(struct device *dev)
diff --git a/drivers/w1/w1_io.c b/drivers/w1/w1_io.c
index 3ebe972..8e8b64c 100644
--- a/drivers/w1/w1_io.c
+++ b/drivers/w1/w1_io.c
@@ -390,6 +390,32 @@ int w1_reset_select_slave(struct w1_slave *sl)
EXPORT_SYMBOL_GPL(w1_reset_select_slave);
/**
+ * When the workflow with a slave amongst many requires several
+ * successive commands a reset between each, this function is similar
+ * to doing a reset then a match ROM for the last matched ROM. The
+ * advantage being that the matched ROM step is skipped in favor of the
+ * resume command. The slave must support the command of course.
+ *
+ * If the bus has only one slave, traditionnaly the match ROM is skipped
+ * and a "SKIP ROM" is done for efficiency. On multi-slave busses, this
+ * doesn't work of course, but the resume command is the next best thing.
+ *
+ * The w1 master lock must be held.
+ *
+ * @param dev the master device
+ */
+int w1_reset_resume_command(struct w1_master *dev)
+{
+ if (w1_reset_bus(dev))
+ return -1;
+
+ /* This will make only the last matched slave perform a skip ROM. */
+ w1_write_8(dev, W1_RESUME_CMD);
+ return 0;
+}
+EXPORT_SYMBOL_GPL(w1_reset_resume_command);
+
+/**
* Put out a strong pull-up of the specified duration after the next write
* operation. Not all hardware supports strong pullups. Hardware that
* doesn't support strong pullups will sleep for the given time after the
--
1.7.4.1
from: Jean-Fran?ois Dagenais <[email protected]>
This patch depends on patch "[PATCH] w1: Add 1-wire reset and resume API (0xA5)" This DS2408 w1 slave driver is not complete for all the
features of the chip, but its sufficient if you use it as
a simple IO expander.
Signed-off-by: Jean-Fran?ois Dagenais <[email protected]>
---
:100644 100644 f0c9096... cd1b724... M drivers/w1/slaves/Kconfig
:100644 100644 3c76350... 75e3913... M drivers/w1/slaves/Makefile
:000000 100644 0000000... 3547e80... A drivers/w1/slaves/w1_ds2408.c
:100644 100644 f3b636d... 7513759... M drivers/w1/w1_family.h
drivers/w1/slaves/Kconfig | 7 +
drivers/w1/slaves/Makefile | 1 +
drivers/w1/slaves/w1_ds2408.c | 402 +++++++++++++++++++++++++++++++++++++++++
drivers/w1/w1_family.h | 1 +
4 files changed, 411 insertions(+), 0 deletions(-)
diff --git a/drivers/w1/slaves/Kconfig b/drivers/w1/slaves/Kconfig
index f0c9096..cd1b724 100644
--- a/drivers/w1/slaves/Kconfig
+++ b/drivers/w1/slaves/Kconfig
@@ -16,6 +16,13 @@ config W1_SLAVE_SMEM
Say Y here if you want to connect 1-wire
simple 64bit memory rom(ds2401/ds2411/ds1990*) to your wire.
+config W1_SLAVE_DS2408
+ tristate "8-Channel Addressable Switch (IO Expander) 0x29 family support (DS2408)"
+ help
+ Say Y here if you want to use a 1-wire
+
+ DS2408 8-Channel Addressable Switch device support
+
config W1_SLAVE_DS2423
tristate "Counter 1-wire device (DS2423)"
select CRC16
diff --git a/drivers/w1/slaves/Makefile b/drivers/w1/slaves/Makefile
index 3c76350..75e3913 100644
--- a/drivers/w1/slaves/Makefile
+++ b/drivers/w1/slaves/Makefile
@@ -4,6 +4,7 @@
obj-$(CONFIG_W1_SLAVE_THERM) += w1_therm.o
obj-$(CONFIG_W1_SLAVE_SMEM) += w1_smem.o
+obj-$(CONFIG_W1_SLAVE_DS2408) += w1_ds2408.o
obj-$(CONFIG_W1_SLAVE_DS2423) += w1_ds2423.o
obj-$(CONFIG_W1_SLAVE_DS2431) += w1_ds2431.o
obj-$(CONFIG_W1_SLAVE_DS2433) += w1_ds2433.o
diff --git a/drivers/w1/slaves/w1_ds2408.c b/drivers/w1/slaves/w1_ds2408.c
new file mode 100644
index 0000000..3547e80
--- /dev/null
+++ b/drivers/w1/slaves/w1_ds2408.c
@@ -0,0 +1,402 @@
+/*
+ * w1_ds2408.c - w1 family 29 (DS2408) driver
+ *
+ * Copyright (c) 2010 Jean-Francois Dagenais <[email protected]>
+ *
+ * This source code is licensed under the GNU General Public License,
+ * Version 2. See the file COPYING for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/device.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+
+#include "../w1.h"
+#include "../w1_int.h"
+#include "../w1_family.h"
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Jean-Francois Dagenais <[email protected]>");
+MODULE_DESCRIPTION("w1 family 29 driver for DS2408 8 Pin IO");
+
+
+#define W1_F29_RETRIES 3
+
+#define W1_F29_REG_LOGIG_STATE 0x88 /* R */
+#define W1_F29_REG_OUTPUT_LATCH_STATE 0x89 /* R */
+#define W1_F29_REG_ACTIVITY_LATCH_STATE 0x8A /* R */
+#define W1_F29_REG_COND_SEARCH_SELECT_MASK 0x8B /* RW */
+#define W1_F29_REG_COND_SEARCH_POL_SELECT 0x8C /* RW */
+#define W1_F29_REG_CONTROL_AND_STATUS 0x8D /* RW */
+
+#define W1_F29_FUNC_READ_PIO_REGS 0xF0
+#define W1_F29_FUNC_CHANN_ACCESS_READ 0xF5
+#define W1_F29_FUNC_CHANN_ACCESS_WRITE 0x5A
+/* also used to write the control/status reg (0x8D): */
+#define W1_F29_FUNC_WRITE_COND_SEARCH_REG 0xCC
+#define W1_F29_FUNC_RESET_ACTIVITY_LATCHES 0xC3
+
+#define W1_F29_SUCCESS_CONFIRM_BYTE 0xAA
+
+static int _read_reg(struct w1_slave *sl, u8 address, unsigned char* buf)
+{
+ u8 wrbuf[3];
+ dev_dbg(&sl->dev,
+ "Reading with slave: %p, reg addr: %0#4x, buff addr: %p",
+ sl, (unsigned int)address, buf);
+
+ if (!buf)
+ return -EINVAL;
+
+ mutex_lock(&sl->master->mutex);
+ dev_dbg(&sl->dev, "mutex locked");
+
+ if (w1_reset_select_slave(sl)) {
+ mutex_unlock(&sl->master->mutex);
+ return -EIO;
+ }
+
+ wrbuf[0] = W1_F29_FUNC_READ_PIO_REGS;
+ wrbuf[1] = address;
+ wrbuf[2] = 0;
+ w1_write_block(sl->master, wrbuf, 3);
+ *buf = w1_read_8(sl->master);
+
+ mutex_unlock(&sl->master->mutex);
+ dev_dbg(&sl->dev, "mutex unlocked");
+ return 1;
+}
+
+static ssize_t w1_f29_read_state(
+ struct file *filp, struct kobject *kobj,
+ struct bin_attribute *bin_attr,
+ char *buf, loff_t off, size_t count)
+{
+ dev_dbg(&kobj_to_w1_slave(kobj)->dev,
+ "Reading %s kobj: %p, off: %0#10x, count: %lu, buff addr: %p",
+ bin_attr->attr.name, kobj, (unsigned int)off, count, buf);
+ if (count != 1 || off != 0)
+ return -EFAULT;
+ return _read_reg(kobj_to_w1_slave(kobj), W1_F29_REG_LOGIG_STATE, buf);
+}
+
+static ssize_t w1_f29_read_output(
+ struct file *filp, struct kobject *kobj,
+ struct bin_attribute *bin_attr,
+ char *buf, loff_t off, size_t count)
+{
+ dev_dbg(&kobj_to_w1_slave(kobj)->dev,
+ "Reading %s kobj: %p, off: %0#10x, count: %lu, buff addr: %p",
+ bin_attr->attr.name, kobj, (unsigned int)off, count, buf);
+ if (count != 1 || off != 0)
+ return -EFAULT;
+ return _read_reg(kobj_to_w1_slave(kobj),
+ W1_F29_REG_OUTPUT_LATCH_STATE, buf);
+}
+
+static ssize_t w1_f29_read_activity(
+ struct file *filp, struct kobject *kobj,
+ struct bin_attribute *bin_attr,
+ char *buf, loff_t off, size_t count)
+{
+ dev_dbg(&kobj_to_w1_slave(kobj)->dev,
+ "Reading %s kobj: %p, off: %0#10x, count: %lu, buff addr: %p",
+ bin_attr->attr.name, kobj, (unsigned int)off, count, buf);
+ if (count != 1 || off != 0)
+ return -EFAULT;
+ return _read_reg(kobj_to_w1_slave(kobj),
+ W1_F29_REG_ACTIVITY_LATCH_STATE, buf);
+}
+
+static ssize_t w1_f29_read_cond_search_mask(
+ struct file *filp, struct kobject *kobj,
+ struct bin_attribute *bin_attr,
+ char *buf, loff_t off, size_t count)
+{
+ dev_dbg(&kobj_to_w1_slave(kobj)->dev,
+ "Reading %s kobj: %p, off: %0#10x, count: %lu, buff addr: %p",
+ bin_attr->attr.name, kobj, (unsigned int)off, count, buf);
+ if (count != 1 || off != 0)
+ return -EFAULT;
+ return _read_reg(kobj_to_w1_slave(kobj),
+ W1_F29_REG_COND_SEARCH_SELECT_MASK, buf);
+}
+
+static ssize_t w1_f29_read_cond_search_polarity(
+ struct file *filp, struct kobject *kobj,
+ struct bin_attribute *bin_attr,
+ char *buf, loff_t off, size_t count)
+{
+ if (count != 1 || off != 0)
+ return -EFAULT;
+ return _read_reg(kobj_to_w1_slave(kobj),
+ W1_F29_REG_COND_SEARCH_POL_SELECT, buf);
+}
+
+static ssize_t w1_f29_read_status_control(
+ struct file *filp, struct kobject *kobj,
+ struct bin_attribute *bin_attr,
+ char *buf, loff_t off, size_t count)
+{
+ if (count != 1 || off != 0)
+ return -EFAULT;
+ return _read_reg(kobj_to_w1_slave(kobj),
+ W1_F29_REG_CONTROL_AND_STATUS, buf);
+}
+
+
+
+
+static ssize_t w1_f29_write_output(
+ struct file *filp, struct kobject *kobj,
+ struct bin_attribute *bin_attr,
+ char *buf, loff_t off, size_t count)
+{
+ struct w1_slave *sl = kobj_to_w1_slave(kobj);
+ u8 w1_buf[3];
+ u8 readBack;
+ unsigned int retries = W1_F29_RETRIES;
+
+ if (count != 1 || off != 0)
+ return -EFAULT;
+
+ dev_dbg(&sl->dev, "locking mutex for write_output");
+ mutex_lock(&sl->master->mutex);
+ dev_dbg(&sl->dev, "mutex locked");
+
+ if (w1_reset_select_slave(sl))
+ goto error;
+
+ while (retries--) {
+ w1_buf[0] = W1_F29_FUNC_CHANN_ACCESS_WRITE;
+ w1_buf[1] = *buf;
+ w1_buf[2] = ~(*buf);
+ w1_write_block(sl->master, w1_buf, 3);
+
+ readBack = w1_read_8(sl->master);
+ /* here the master could read another byte which
+ would be the PIO reg (the actual pin logic state)
+ since in this driver we don't know which pins are
+ in and outs, there's no value to read the state and
+ compare. with (*buf) so end this command abruptly: */
+ if (w1_reset_resume_command(sl->master))
+ goto error;
+
+ if (readBack != 0xAA) {
+ /* try again, the slave is ready for a command */
+ continue;
+ }
+
+ /* go read back the output latches */
+ /* (the direct effect of the write above) */
+ w1_buf[0] = W1_F29_FUNC_READ_PIO_REGS;
+ w1_buf[1] = W1_F29_REG_OUTPUT_LATCH_STATE;
+ w1_buf[2] = 0;
+ w1_write_block(sl->master, w1_buf, 3);
+ /* read the result of the READ_PIO_REGS command */
+ if (w1_read_8(sl->master) == *buf) {
+ /* success! */
+ mutex_unlock(&sl->master->mutex);
+ dev_dbg(&sl->dev,
+ "mutex unlocked, retries:%d", retries);
+ return 1;
+ }
+ }
+error:
+ mutex_unlock(&sl->master->mutex);
+ dev_dbg(&sl->dev, "mutex unlocked in error, retries:%d", retries);
+
+ return -EIO;
+}
+
+
+/**
+ * Writing to the activity file resets the activity latches.
+ */
+static ssize_t w1_f29_write_activity(
+ struct file *filp, struct kobject *kobj,
+ struct bin_attribute *bin_attr,
+ char *buf, loff_t off, size_t count)
+{
+ struct w1_slave *sl = kobj_to_w1_slave(kobj);
+ unsigned int retries = W1_F29_RETRIES;
+
+ if (count != 1 || off != 0)
+ return -EFAULT;
+
+ mutex_lock(&sl->master->mutex);
+
+ if (w1_reset_select_slave(sl))
+ goto error;
+
+ while (retries--) {
+ w1_write_8(sl->master, W1_F29_FUNC_RESET_ACTIVITY_LATCHES);
+ if (w1_read_8(sl->master) == W1_F29_SUCCESS_CONFIRM_BYTE) {
+ mutex_unlock(&sl->master->mutex);
+ return 1;
+ }
+ if (w1_reset_resume_command(sl->master))
+ goto error;
+ }
+
+error:
+ mutex_unlock(&sl->master->mutex);
+ return -EIO;
+}
+
+static ssize_t w1_f29_write_status_control(
+ struct file *filp,
+ struct kobject *kobj,
+ struct bin_attribute *bin_attr,
+ char *buf,
+ loff_t off,
+ size_t count)
+{
+ struct w1_slave *sl = kobj_to_w1_slave(kobj);
+ u8 w1_buf[4];
+ unsigned int retries = W1_F29_RETRIES;
+
+ if (count != 1 || off != 0)
+ return -EFAULT;
+
+ mutex_lock(&sl->master->mutex);
+
+ if (w1_reset_select_slave(sl))
+ goto error;
+
+ while (retries--) {
+ w1_buf[0] = W1_F29_FUNC_WRITE_COND_SEARCH_REG;
+ w1_buf[1] = W1_F29_REG_CONTROL_AND_STATUS;
+ w1_buf[2] = 0;
+ w1_buf[3] = *buf;
+
+ w1_write_block(sl->master, w1_buf, 4);
+ if (w1_reset_resume_command(sl->master))
+ goto error;
+
+ w1_buf[0] = W1_F29_FUNC_READ_PIO_REGS;
+ w1_buf[1] = W1_F29_REG_CONTROL_AND_STATUS;
+ w1_buf[2] = 0;
+
+ w1_write_block(sl->master, w1_buf, 3);
+ if (w1_read_8(sl->master) == *buf) {
+ /* success! */
+ mutex_unlock(&sl->master->mutex);
+ return 1;
+ }
+ }
+error:
+ mutex_unlock(&sl->master->mutex);
+
+ return -EIO;
+}
+
+
+
+#define NB_SYSFS_BIN_FILES 6
+static struct bin_attribute w1_f29_sysfs_bin_files[NB_SYSFS_BIN_FILES] = {
+ {
+ .attr = {
+ .name = "state",
+ .mode = S_IRUGO,
+ },
+ .size = 1,
+ .read = w1_f29_read_state,
+ },
+ {
+ .attr = {
+ .name = "output",
+ .mode = S_IRUGO | S_IWUSR | S_IWGRP,
+ },
+ .size = 1,
+ .read = w1_f29_read_output,
+ .write = w1_f29_write_output,
+ },
+ {
+ .attr = {
+ .name = "activity",
+ .mode = S_IRUGO,
+ },
+ .size = 1,
+ .read = w1_f29_read_activity,
+ .write = w1_f29_write_activity,
+ },
+ {
+ .attr = {
+ .name = "cond_search_mask",
+ .mode = S_IRUGO,
+ },
+ .size = 1,
+ .read = w1_f29_read_cond_search_mask,
+ .write = 0,
+ },
+ {
+ .attr = {
+ .name = "cond_search_polarity",
+ .mode = S_IRUGO,
+ },
+ .size = 1,
+ .read = w1_f29_read_cond_search_polarity,
+ .write = 0,
+ },
+ {
+ .attr = {
+ .name = "status_control",
+ .mode = S_IRUGO | S_IWUSR | S_IWGRP,
+ },
+ .size = 1,
+ .read = w1_f29_read_status_control,
+ .write = w1_f29_write_status_control,
+ }
+};
+
+static int w1_f29_add_slave(struct w1_slave *sl)
+{
+ int err = 0;
+ int i;
+
+ for (i = 0; i < NB_SYSFS_BIN_FILES && !err; ++i)
+ err = sysfs_create_bin_file(
+ &sl->dev.kobj,
+ &(w1_f29_sysfs_bin_files[i]));
+ if (err)
+ while (--i >= 0)
+ sysfs_remove_bin_file(&sl->dev.kobj,
+ &(w1_f29_sysfs_bin_files[i]));
+ return err;
+}
+
+static void w1_f29_remove_slave(struct w1_slave *sl)
+{
+ int i;
+ for (i = NB_SYSFS_BIN_FILES; i <= 0; --i)
+ sysfs_remove_bin_file(&sl->dev.kobj,
+ &(w1_f29_sysfs_bin_files[i]));
+}
+
+static struct w1_family_ops w1_f29_fops = {
+ .add_slave = w1_f29_add_slave,
+ .remove_slave = w1_f29_remove_slave,
+};
+
+static struct w1_family w1_family_29 = {
+ .fid = W1_FAMILY_DS2408,
+ .fops = &w1_f29_fops,
+};
+
+static int __init w1_f29_init(void)
+{
+ return w1_register_family(&w1_family_29);
+}
+
+static void __exit w1_f29_exit(void)
+{
+ w1_unregister_family(&w1_family_29);
+}
+
+module_init(w1_f29_init);
+module_exit(w1_f29_exit);
diff --git a/drivers/w1/w1_family.h b/drivers/w1/w1_family.h
index f3b636d..7513759 100644
--- a/drivers/w1/w1_family.h
+++ b/drivers/w1/w1_family.h
@@ -34,6 +34,7 @@
#define W1_THERM_DS1822 0x22
#define W1_EEPROM_DS2433 0x23
#define W1_THERM_DS18B20 0x28
+#define W1_FAMILY_DS2408 0x29
#define W1_EEPROM_DS2431 0x2D
#define W1_FAMILY_DS2760 0x30
--
1.7.4.1
from: Jean-Francois Dagenais <[email protected]>
The initial patch purpose was to extend the search algo from single slave to multi-slave by exploiting the search acceleration provided by ds1wm. More tweaks were added.
The ds1wm had Kconfig dependencies towards ARM && HAVE_CLK. I took them
out since I was using the ds1wm on an x86_64 platform (ds1wm in a FPGA through
pcie) and found them irrelevant.
The clock freq/divisors at the top of ds1wm.c did not have the MSB set to 1.
This bit is CLK_EN which turns the whole prescaler and dividers on. The driver
never mentionned this bit either, so I just included this bit right in the table
entries. I also took the liberty to add a couple of entries to the table. The
spec doesn't explicitely mentions these possibilities but the description and
examination of the core shows the prescalers & dividers can be used for more
than the table explicitely shows. The table I enlarged still doesn't cover all
possibilities, but it's a good start.
I also made a few tweaks to a couple of the read and write algorithms which
made sense while I had my head very deep in the ds1wm documentation. We stressed
it a lot with 10+ slaves on the bus, many ds2408, ds2431 and ds2433 at the same
time doing extensive interaction. It proved quite stable in our production
environment.
Fixes and tweaks based on the rev3 of the datasheet
http://datasheets.maxim-ic.com/en/ds/DS1WM.pdf
Signed-off-by: Jean-Francois Dagenais <[email protected]>
---
:100644 100644 80b3b12... e3739df... M drivers/w1/masters/Kconfig
:100644 100644 6b85e7f... 949d38f... M drivers/w1/masters/ds1wm.c
drivers/w1/masters/Kconfig | 2 +-
drivers/w1/masters/ds1wm.c | 321 ++++++++++++++++++++++++++++++--------------
2 files changed, 220 insertions(+), 103 deletions(-)
diff --git a/drivers/w1/masters/Kconfig b/drivers/w1/masters/Kconfig
index 80b3b12..e3739df 100644
--- a/drivers/w1/masters/Kconfig
+++ b/drivers/w1/masters/Kconfig
@@ -42,7 +42,7 @@ config W1_MASTER_MXC
config W1_MASTER_DS1WM
tristate "Maxim DS1WM 1-wire busmaster"
- depends on W1 && ARM && HAVE_CLK
+ depends on W1
help
Say Y here to enable the DS1WM 1-wire driver, such as that
in HP iPAQ devices like h5xxx, h2200, and ASIC3-based like
diff --git a/drivers/w1/masters/ds1wm.c b/drivers/w1/masters/ds1wm.c
index 6b85e7f..949d38f 100644
--- a/drivers/w1/masters/ds1wm.c
+++ b/drivers/w1/masters/ds1wm.c
@@ -33,6 +33,7 @@
#define DS1WM_INT 0x02 /* R/W interrupt status */
#define DS1WM_INT_EN 0x03 /* R/W interrupt enable */
#define DS1WM_CLKDIV 0x04 /* R/W 5 bits of divisor and pre-scale */
+#define DS1WM_CNTRL 0x05 /* R/W master control register (not used yet) */
#define DS1WM_CMD_1W_RESET (1 << 0) /* force reset on 1-wire bus */
#define DS1WM_CMD_SRA (1 << 1) /* enable Search ROM accelerator mode */
@@ -56,6 +57,7 @@
#define DS1WM_INTEN_ERSRF (1 << 5) /* enable rx shift register full int */
#define DS1WM_INTEN_DQO (1 << 6) /* enable direct bus driving ops */
+#define DS1WM_INTEN_NOT_IAS (~DS1WM_INTEN_IAS) /* all but INTR active state */
#define DS1WM_TIMEOUT (HZ * 5)
@@ -63,41 +65,50 @@ static struct {
unsigned long freq;
unsigned long divisor;
} freq[] = {
- { 4000000, 0x8 },
- { 5000000, 0x2 },
- { 6000000, 0x5 },
- { 7000000, 0x3 },
- { 8000000, 0xc },
- { 10000000, 0x6 },
- { 12000000, 0x9 },
- { 14000000, 0x7 },
- { 16000000, 0x10 },
- { 20000000, 0xa },
- { 24000000, 0xd },
- { 28000000, 0xb },
- { 32000000, 0x14 },
- { 40000000, 0xe },
- { 48000000, 0x11 },
- { 56000000, 0xf },
- { 64000000, 0x18 },
- { 80000000, 0x12 },
- { 96000000, 0x15 },
- { 112000000, 0x13 },
- { 128000000, 0x1c },
+ { 1000000, 0x80 },
+ { 2000000, 0x84 },
+ { 3000000, 0x81 },
+ { 4000000, 0x88 },
+ { 5000000, 0x82 },
+ { 6000000, 0x85 },
+ { 7000000, 0x83 },
+ { 8000000, 0x8c },
+ { 10000000, 0x86 },
+ { 12000000, 0x89 },
+ { 14000000, 0x87 },
+ { 16000000, 0x90 },
+ { 20000000, 0x8a },
+ { 24000000, 0x8d },
+ { 28000000, 0x8b },
+ { 32000000, 0x94 },
+ { 40000000, 0x8e },
+ { 48000000, 0x91 },
+ { 56000000, 0x8f },
+ { 64000000, 0x98 },
+ { 80000000, 0x92 },
+ { 96000000, 0x95 },
+ { 112000000, 0x93 },
+ { 128000000, 0x9c },
+/* you can continue this table, consult the OPERATION - CLOCK DIVISOR
+ section of the ds1wm spec sheet. */
};
struct ds1wm_data {
- void __iomem *map;
- int bus_shift; /* # of shifts to calc register offsets */
+ void __iomem *map;
+ int bus_shift; /* # of shifts to calc register offsets */
struct platform_device *pdev;
- struct mfd_cell *cell;
- int irq;
- int active_high;
- int slave_present;
- void *reset_complete;
- void *read_complete;
- void *write_complete;
- u8 read_byte; /* last byte received */
+ struct mfd_cell *cell;
+ int irq;
+ int slave_present;
+ void *reset_complete;
+ void *read_complete;
+ void *write_complete;
+ int read_error;
+ /* last byte received */
+ u8 read_byte;
+ /* byte to write that makes all intr disabled, */
+ /* considering active_state (IAS) (optimization) */
+ u8 int_en_reg_none;
};
static inline void ds1wm_write_register(struct ds1wm_data *ds1wm_data, u32 reg,
@@ -115,23 +126,39 @@ static inline u8 ds1wm_read_register(struct ds1wm_data *ds1wm_data, u32 reg)
static irqreturn_t ds1wm_isr(int isr, void *data)
{
struct ds1wm_data *ds1wm_data = data;
- u8 intr = ds1wm_read_register(ds1wm_data, DS1WM_INT);
+ u8 intr;
+ u8 inten = ds1wm_read_register(ds1wm_data, DS1WM_INT_EN);
+ /* if no bits are set in int enable register (except the IAS)
+ than go no further, reading the regs below has side effects */
+ if (!(inten & DS1WM_INTEN_NOT_IAS))
+ return IRQ_NONE;
- ds1wm_data->slave_present = (intr & DS1WM_INT_PDR) ? 0 : 1;
+ ds1wm_write_register(ds1wm_data,
+ DS1WM_INT_EN, ds1wm_data->int_en_reg_none);
- if ((intr & DS1WM_INT_PD) && ds1wm_data->reset_complete)
- complete(ds1wm_data->reset_complete);
+ /* this read action clears the INTR and certain flags in ds1wm */
+ intr = ds1wm_read_register(ds1wm_data, DS1WM_INT);
- if ((intr & DS1WM_INT_TSRE) && ds1wm_data->write_complete)
- complete(ds1wm_data->write_complete);
+ ds1wm_data->slave_present = (intr & DS1WM_INT_PDR) ? 0 : 1;
+ if ((intr & DS1WM_INT_TSRE) && ds1wm_data->write_complete) {
+ inten &= ~DS1WM_INTEN_ETMT;
+ complete(ds1wm_data->write_complete);
+ }
if (intr & DS1WM_INT_RBF) {
+ /* this read clears the RBF flag */
ds1wm_data->read_byte = ds1wm_read_register(ds1wm_data,
- DS1WM_DATA);
+ DS1WM_DATA);
+ inten &= ~DS1WM_INTEN_ERBF;
if (ds1wm_data->read_complete)
complete(ds1wm_data->read_complete);
}
+ if ((intr & DS1WM_INT_PD) && ds1wm_data->reset_complete) {
+ inten &= ~DS1WM_INTEN_EPD;
+ complete(ds1wm_data->reset_complete);
+ }
+ ds1wm_write_register(ds1wm_data, DS1WM_INT_EN, inten);
return IRQ_HANDLED;
}
@@ -142,33 +169,19 @@ static int ds1wm_reset(struct ds1wm_data *ds1wm_data)
ds1wm_data->reset_complete = &reset_done;
+ /* enable Presence detect only */
ds1wm_write_register(ds1wm_data, DS1WM_INT_EN, DS1WM_INTEN_EPD |
- (ds1wm_data->active_high ? DS1WM_INTEN_IAS : 0));
+ ds1wm_data->int_en_reg_none);
ds1wm_write_register(ds1wm_data, DS1WM_CMD, DS1WM_CMD_1W_RESET);
timeleft = wait_for_completion_timeout(&reset_done, DS1WM_TIMEOUT);
ds1wm_data->reset_complete = NULL;
if (!timeleft) {
- dev_err(&ds1wm_data->pdev->dev, "reset failed\n");
+ dev_err(&ds1wm_data->pdev->dev, "reset failed, timed out\n");
return 1;
}
- /* Wait for the end of the reset. According to the specs, the time
- * from when the interrupt is asserted to the end of the reset is:
- * tRSTH - tPDH - tPDL - tPDI
- * 625 us - 60 us - 240 us - 100 ns = 324.9 us
- *
- * We'll wait a bit longer just to be sure.
- * Was udelay(500), but if it is going to busywait the cpu that long,
- * might as well come back later.
- */
- msleep(1);
-
- ds1wm_write_register(ds1wm_data, DS1WM_INT_EN,
- DS1WM_INTEN_ERBF | DS1WM_INTEN_ETMT | DS1WM_INTEN_EPD |
- (ds1wm_data->active_high ? DS1WM_INTEN_IAS : 0));
-
if (!ds1wm_data->slave_present) {
dev_dbg(&ds1wm_data->pdev->dev, "reset: no devices found\n");
return 1;
@@ -179,26 +192,47 @@ static int ds1wm_reset(struct ds1wm_data *ds1wm_data)
static int ds1wm_write(struct ds1wm_data *ds1wm_data, u8 data)
{
+ unsigned long timeleft;
DECLARE_COMPLETION_ONSTACK(write_done);
ds1wm_data->write_complete = &write_done;
+ ds1wm_write_register(ds1wm_data, DS1WM_INT_EN,
+ ds1wm_data->int_en_reg_none | DS1WM_INTEN_ETMT);
+
ds1wm_write_register(ds1wm_data, DS1WM_DATA, data);
- wait_for_completion_timeout(&write_done, DS1WM_TIMEOUT);
+ timeleft = wait_for_completion_timeout(&write_done, DS1WM_TIMEOUT);
+
ds1wm_data->write_complete = NULL;
+ if (!timeleft) {
+ dev_err(&ds1wm_data->pdev->dev, "write failed, timed out\n");
+ return -ETIMEDOUT;
+ }
return 0;
}
-static int ds1wm_read(struct ds1wm_data *ds1wm_data, unsigned char write_data)
+static u8 ds1wm_read(struct ds1wm_data *ds1wm_data, unsigned char write_data)
{
+ unsigned long timeleft;
+ u8 intEnable = DS1WM_INTEN_ERBF | ds1wm_data->int_en_reg_none;
DECLARE_COMPLETION_ONSTACK(read_done);
+
+ ds1wm_read_register(ds1wm_data, DS1WM_DATA);
+
ds1wm_data->read_complete = &read_done;
+ ds1wm_write_register(ds1wm_data, DS1WM_INT_EN, intEnable);
- ds1wm_write(ds1wm_data, write_data);
- wait_for_completion_timeout(&read_done, DS1WM_TIMEOUT);
- ds1wm_data->read_complete = NULL;
+ ds1wm_write_register(ds1wm_data, DS1WM_DATA, write_data);
+ timeleft = wait_for_completion_timeout(&read_done, DS1WM_TIMEOUT);
+ ds1wm_data->read_complete = NULL;
+ if (!timeleft) {
+ dev_err(&ds1wm_data->pdev->dev, "read failed, timed out\n");
+ ds1wm_data->read_error = -ETIMEDOUT;
+ return 0xFF;
+ }
+ ds1wm_data->read_error = 0;
return ds1wm_data->read_byte;
}
@@ -206,8 +240,8 @@ static int ds1wm_find_divisor(int gclk)
{
int i;
- for (i = 0; i < ARRAY_SIZE(freq); i++)
- if (gclk <= freq[i].freq)
+ for (i = ARRAY_SIZE(freq)-1; i >= 0; --i)
+ if (gclk >= freq[i].freq)
return freq[i].divisor;
return 0;
@@ -222,6 +256,8 @@ static void ds1wm_up(struct ds1wm_data *ds1wm_data)
ds1wm_data->cell->enable(ds1wm_data->pdev);
divisor = ds1wm_find_divisor(plat->clock_rate);
+ dev_dbg(&ds1wm_data->pdev->dev,
+ "found divisor 0x%x for clock %d\n", divisor, plat->clock_rate);
if (divisor == 0) {
dev_err(&ds1wm_data->pdev->dev,
"no suitable divisor for %dHz clock\n",
@@ -242,7 +278,7 @@ static void ds1wm_down(struct ds1wm_data *ds1wm_data)
/* Disable interrupts. */
ds1wm_write_register(ds1wm_data, DS1WM_INT_EN,
- ds1wm_data->active_high ? DS1WM_INTEN_IAS : 0);
+ ds1wm_data->int_en_reg_none);
if (ds1wm_data->cell->disable)
ds1wm_data->cell->disable(ds1wm_data->pdev);
@@ -279,41 +315,121 @@ static void ds1wm_search(void *data, struct w1_master *master_dev,
{
struct ds1wm_data *ds1wm_data = data;
int i;
- unsigned long long rom_id;
-
- /* XXX We need to iterate for multiple devices per the DS1WM docs.
- * See http://www.maxim-ic.com/appnotes.cfm/appnote_number/120. */
- if (ds1wm_reset(ds1wm_data))
- return;
-
- ds1wm_write(ds1wm_data, search_type);
- ds1wm_write_register(ds1wm_data, DS1WM_CMD, DS1WM_CMD_SRA);
-
- for (rom_id = 0, i = 0; i < 16; i++) {
-
- unsigned char resp, r, d;
-
- resp = ds1wm_read(ds1wm_data, 0x00);
-
- r = ((resp & 0x02) >> 1) |
- ((resp & 0x08) >> 2) |
- ((resp & 0x20) >> 3) |
- ((resp & 0x80) >> 4);
-
- d = ((resp & 0x01) >> 0) |
- ((resp & 0x04) >> 1) |
- ((resp & 0x10) >> 2) |
- ((resp & 0x40) >> 3);
-
- rom_id |= (unsigned long long) r << (i * 4);
-
- }
- dev_dbg(&ds1wm_data->pdev->dev, "found 0x%08llX\n", rom_id);
-
- ds1wm_write_register(ds1wm_data, DS1WM_CMD, ~DS1WM_CMD_SRA);
- ds1wm_reset(ds1wm_data);
-
- slave_found(master_dev, rom_id);
+ int ms_discrep_bit = -1;
+ u64 r = 0; /* holds the progress of the search */
+ u64 r_prime, d;
+ unsigned slaves_found = 0;
+ unsigned int pass = 0;
+
+ dev_dbg(&ds1wm_data->pdev->dev, "search begin\n");
+ while (true) {
+ ++pass;
+ if (pass > 100) {
+ dev_dbg(&ds1wm_data->pdev->dev,
+ "too many attempts (100), search aborted\n");
+ return;
+ }
+
+ if (ds1wm_reset(ds1wm_data)) {
+ dev_dbg(&ds1wm_data->pdev->dev,
+ "pass: %d reset error (or no slaves)\n", pass);
+ break;
+ }
+
+ dev_dbg(&ds1wm_data->pdev->dev,
+ "pass: %d r : %0#18llx writing SEARCH_ROM\n", pass, r);
+ ds1wm_write(ds1wm_data, search_type);
+ dev_dbg(&ds1wm_data->pdev->dev,
+ "pass: %d entering ASM\n", pass);
+ ds1wm_write_register(ds1wm_data, DS1WM_CMD, DS1WM_CMD_SRA);
+ dev_dbg(&ds1wm_data->pdev->dev,
+ "pass: %d begining nibble loop\n", pass);
+
+ r_prime = 0;
+ d = 0;
+ /* we work one nibble at a time */
+ /* each nibble is interleaved to form a byte */
+ for (i = 0; i < 16; i++) {
+
+ unsigned char resp, _r, _r_prime, _d;
+
+ _r = (r >> (4*i)) & 0xf;
+ _r = ((_r & 0x1) << 1) |
+ ((_r & 0x2) << 2) |
+ ((_r & 0x4) << 3) |
+ ((_r & 0x8) << 4);
+
+ /* writes _r, then reads back: */
+ resp = ds1wm_read(ds1wm_data, _r);
+
+ if (ds1wm_data->read_error) {
+ dev_err(&ds1wm_data->pdev->dev,
+ "pass: %d nibble: %d read error\n", pass, i);
+ break;
+ }
+
+ _r_prime = ((resp & 0x02) >> 1) |
+ ((resp & 0x08) >> 2) |
+ ((resp & 0x20) >> 3) |
+ ((resp & 0x80) >> 4);
+
+ _d = ((resp & 0x01) >> 0) |
+ ((resp & 0x04) >> 1) |
+ ((resp & 0x10) >> 2) |
+ ((resp & 0x40) >> 3);
+
+ r_prime |= (unsigned long long) _r_prime << (i * 4);
+ d |= (unsigned long long) _d << (i * 4);
+
+ }
+ if (ds1wm_data->read_error) {
+ dev_err(&ds1wm_data->pdev->dev,
+ "pass: %d read error, retrying\n", pass);
+ break;
+ }
+ dev_dbg(&ds1wm_data->pdev->dev,
+ "pass: %d r\': %0#18llx d:%0#18llx\n",
+ pass, r_prime, d);
+ dev_dbg(&ds1wm_data->pdev->dev,
+ "pass: %d nibble loop complete, exiting ASM\n", pass);
+ ds1wm_write_register(ds1wm_data, DS1WM_CMD, ~DS1WM_CMD_SRA);
+ dev_dbg(&ds1wm_data->pdev->dev,
+ "pass: %d resetting bus\n", pass);
+ ds1wm_reset(ds1wm_data);
+ if ((r_prime & ((u64)1 << 63)) && (d & ((u64)1 << 63))) {
+ dev_err(&ds1wm_data->pdev->dev,
+ "pass: %d bus error, retrying\n", pass);
+ continue; /* start over */
+ }
+
+
+ dev_dbg(&ds1wm_data->pdev->dev,
+ "pass: %d found %0#18llx\n", pass, r_prime);
+ slave_found(master_dev, r_prime);
+ ++slaves_found;
+ dev_dbg(&ds1wm_data->pdev->dev,
+ "pass: %d complete, preparing next pass\n", pass);
+
+ /* any discrepency found which we already choose the
+ '1' branch is now is now irrelevant we reveal the
+ next branch with this: */
+ d &= ~r;
+ /* find last bit set, i.e. the most signif. bit set */
+ ms_discrep_bit = fls64(d) - 1;
+ dev_dbg(&ds1wm_data->pdev->dev,
+ "pass: %d new d:%0#18llx MS discrep bit:%d\n",
+ pass, d, ms_discrep_bit);
+
+ /* prev_ms_discrep_bit = ms_discrep_bit;
+ prepare for next ROM search: */
+ if (ms_discrep_bit == -1)
+ break;
+
+ r = (r & ~(~0ull << (ms_discrep_bit))) | 1 << ms_discrep_bit;
+ } /* end while true */
+ dev_dbg(&ds1wm_data->pdev->dev,
+ "pass: %d total: %d search done ms d bit pos: %d\n", pass,
+ slaves_found, ms_discrep_bit);
}
/* --------------------------------------------------------------------- */
@@ -370,15 +486,15 @@ static int ds1wm_probe(struct platform_device *pdev)
goto err1;
}
ds1wm_data->irq = res->start;
- ds1wm_data->active_high = plat->active_high;
+ ds1wm_data->int_en_reg_none = (plat->active_high ? DS1WM_INTEN_IAS : 0);
if (res->flags & IORESOURCE_IRQ_HIGHEDGE)
set_irq_type(ds1wm_data->irq, IRQ_TYPE_EDGE_RISING);
if (res->flags & IORESOURCE_IRQ_LOWEDGE)
set_irq_type(ds1wm_data->irq, IRQ_TYPE_EDGE_FALLING);
- ret = request_irq(ds1wm_data->irq, ds1wm_isr, IRQF_DISABLED,
- "ds1wm", ds1wm_data);
+ ret = request_irq(ds1wm_data->irq, ds1wm_isr,
+ IRQF_DISABLED | IRQF_SHARED, "ds1wm", ds1wm_data);
if (ret)
goto err1;
@@ -465,5 +581,6 @@ module_exit(ds1wm_exit);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Szabolcs Gyurko <[email protected]>, "
- "Matt Reimer <[email protected]>");
+ "Matt Reimer <[email protected]>,"
+ "Jean-Francois Dagenais <[email protected]>");
MODULE_DESCRIPTION("DS1WM w1 busmaster driver");
--
1.7.4.1