This patch series adds I2S support for the StarFive JH7110 RISC-V
SoC based on Designware I2S controller. There has three I2S channels
(RX/TX0/TX1) on the JH7110 SoC, one of which is for record(RX) and
two for playback(TX).
The first patch adds the ops to get data from platform bus in the
I2S driver.
The second patch adds support for the StarFive JH7110 SoC in
the Designware I2S bindings.
The third patch adds support for the StarFive JH7110 SoC in
the Designware I2S driver.
The fourth patch fixes the name of I2STX1 pinmux.
The last patch adds device node of I2S RX/TX0/TX1 in JH7110 dts.
This patch series is based on Linux-next which is merge clock,
syscon and dma nodes for the StarFive JH7110 SoC. And these
should be applied after the following patchset:
https://lore.kernel.org/all/[email protected]/
The series has been tested and works normally on the VisionFive 2
board by plugging an audio expansion board.
Xingyu Wu (5):
ASoC: dwc: Use ops to get platform data
ASoC: dt-bindings: snps,designware-i2s: Add StarFive JH7110 SoC
support
ASoC: dwc: i2s: Add StarFive JH7110 SoC support
riscv: dts: starfive: pinfunc: Fix the pins name of I2STX1
riscv: dts: starfive: Add the nodes and pins of I2Srx/I2Stx0/I2Stx1
.../bindings/sound/snps,designware-i2s.yaml | 101 +++++-
arch/riscv/boot/dts/starfive/jh7110-pinfunc.h | 4 +-
.../jh7110-starfive-visionfive-2.dtsi | 58 ++++
arch/riscv/boot/dts/starfive/jh7110.dtsi | 65 ++++
include/sound/designware_i2s.h | 3 +
sound/soc/dwc/dwc-i2s.c | 318 ++++++++++++++++--
sound/soc/dwc/local.h | 1 +
7 files changed, 523 insertions(+), 27 deletions(-)
base-commit: 0fee53365d051781156b75c6f6e6015757e71fd8
prerequisite-patch-id: 0159f09bb0a1ff711a00ae17ef5b12662c9c7d3d
--
2.25.1
Add I2Srx/I2Stx0/I2Stx1 nodes and pins configuration for the
StarFive JH7110 SoC.
Signed-off-by: Xingyu Wu <[email protected]>
---
.../jh7110-starfive-visionfive-2.dtsi | 58 +++++++++++++++++
arch/riscv/boot/dts/starfive/jh7110.dtsi | 65 +++++++++++++++++++
2 files changed, 123 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
index f874d31006a6..8f90d1b6fd66 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -185,6 +185,24 @@ &i2c6 {
status = "okay";
};
+&i2srx {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2srx_pins>;
+ status = "okay";
+};
+
+&i2stx0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mclk_ext_pins>;
+ status = "okay";
+};
+
+&i2stx1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2stx1_pins>;
+ status = "okay";
+};
+
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>;
@@ -254,6 +272,46 @@ GPOEN_SYS_I2C6_DATA,
};
};
+ i2srx_pins: i2srx-0 {
+ clk-sd-pins {
+ pinmux = <GPIOMUX(38, GPOUT_LOW,
+ GPOEN_DISABLE,
+ GPI_SYS_I2SRX_BCLK)>,
+ <GPIOMUX(63, GPOUT_LOW,
+ GPOEN_DISABLE,
+ GPI_SYS_I2SRX_LRCK)>,
+ <GPIOMUX(38, GPOUT_LOW,
+ GPOEN_DISABLE,
+ GPI_SYS_I2STX1_BCLK)>,
+ <GPIOMUX(63, GPOUT_LOW,
+ GPOEN_DISABLE,
+ GPI_SYS_I2STX1_LRCK)>,
+ <GPIOMUX(61, GPOUT_LOW,
+ GPOEN_DISABLE,
+ GPI_SYS_I2SRX_SDIN0)>;
+ input-enable;
+ };
+ };
+
+ i2stx1_pins: i2stx1-0 {
+ sd-pins {
+ pinmux = <GPIOMUX(44, GPOUT_SYS_I2STX1_SDO0,
+ GPOEN_ENABLE,
+ GPI_NONE)>;
+ bias-disable;
+ input-disable;
+ };
+ };
+
+ mclk_ext_pins: mclk-ext-0 {
+ mclk-ext-pins {
+ pinmux = <GPIOMUX(4, GPOUT_LOW,
+ GPOEN_DISABLE,
+ GPI_SYS_MCLK_EXT)>;
+ input-enable;
+ };
+ };
+
spi0_pins: spi0-0 {
mosi-pins {
pinmux = <GPIOMUX(52, GPOUT_SYS_SPI0_TXD,
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 05f843b8ca03..507312eb6053 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -512,6 +512,30 @@ tdm: tdm@10090000 {
status = "disabled";
};
+ i2srx: i2srx@100e0000 {
+ compatible = "starfive,jh7110-i2srx";
+ reg = <0x0 0x100e0000 0x0 0x1000>;
+ clocks = <&syscrg JH7110_SYSCLK_I2SRX_BCLK_MST>,
+ <&syscrg JH7110_SYSCLK_I2SRX_APB>,
+ <&syscrg JH7110_SYSCLK_MCLK>,
+ <&syscrg JH7110_SYSCLK_MCLK_INNER>,
+ <&mclk_ext>,
+ <&syscrg JH7110_SYSCLK_I2SRX_BCLK>,
+ <&syscrg JH7110_SYSCLK_I2SRX_LRCK>,
+ <&i2srx_bclk_ext>,
+ <&i2srx_lrck_ext>;
+ clock-names = "i2sclk", "apb", "mclk",
+ "mclk_inner", "mclk_ext", "bclk",
+ "lrck", "bclk_ext", "lrck_ext";
+ resets = <&syscrg JH7110_SYSRST_I2SRX_APB>,
+ <&syscrg JH7110_SYSRST_I2SRX_BCLK>;
+ dmas = <0>, <&dma 24>;
+ dma-names = "tx", "rx";
+ starfive,syscon = <&sys_syscon 0x18 0x2>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
usb0: usb@10100000 {
compatible = "starfive,jh7110-usb";
ranges = <0x0 0x0 0x10100000 0x100000>;
@@ -736,6 +760,47 @@ spi6: spi@120a0000 {
status = "disabled";
};
+ i2stx0: i2stx0@120b0000 {
+ compatible = "starfive,jh7110-i2stx0";
+ reg = <0x0 0x120b0000 0x0 0x1000>;
+ clocks = <&syscrg JH7110_SYSCLK_I2STX0_BCLK_MST>,
+ <&syscrg JH7110_SYSCLK_I2STX0_APB>,
+ <&syscrg JH7110_SYSCLK_MCLK>,
+ <&syscrg JH7110_SYSCLK_MCLK_INNER>,
+ <&mclk_ext>;
+ clock-names = "i2sclk", "apb", "mclk",
+ "mclk_inner","mclk_ext";
+ resets = <&syscrg JH7110_SYSRST_I2STX0_APB>,
+ <&syscrg JH7110_SYSRST_I2STX0_BCLK>;
+ dmas = <&dma 47>;
+ dma-names = "tx";
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ i2stx1: i2stx1@120c0000 {
+ compatible = "starfive,jh7110-i2stx1";
+ reg = <0x0 0x120c0000 0x0 0x1000>;
+ clocks = <&syscrg JH7110_SYSCLK_I2STX1_BCLK_MST>,
+ <&syscrg JH7110_SYSCLK_I2STX1_APB>,
+ <&syscrg JH7110_SYSCLK_MCLK>,
+ <&syscrg JH7110_SYSCLK_MCLK_INNER>,
+ <&mclk_ext>,
+ <&syscrg JH7110_SYSCLK_I2STX1_BCLK>,
+ <&syscrg JH7110_SYSCLK_I2STX1_LRCK>,
+ <&i2stx_bclk_ext>,
+ <&i2stx_lrck_ext>;
+ clock-names = "i2sclk", "apb", "mclk",
+ "mclk_inner", "mclk_ext", "bclk",
+ "lrck", "bclk_ext", "lrck_ext";
+ resets = <&syscrg JH7110_SYSRST_I2STX1_APB>,
+ <&syscrg JH7110_SYSRST_I2STX1_BCLK>;
+ dmas = <&dma 48>;
+ dma-names = "tx";
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
sfctemp: temperature-sensor@120e0000 {
compatible = "starfive,jh7110-temp";
reg = <0x0 0x120e0000 0x0 0x10000>;
--
2.25.1
Add the StarFive JH7110 (TX0/TX1/RX channel) SoC support in the bindings
of Designware I2S controller. The I2S controller needs two reset items
to work properly on the JH7110 SoC. And TX0 channel as master mode needs
5 clock items and TX1/RX channels as slave mode need 9 clock items on
the JH7110 SoC. The RX channel needs System Register Controller property
to enable it and other platforms do not need it.
Signed-off-by: Xingyu Wu <[email protected]>
---
.../bindings/sound/snps,designware-i2s.yaml | 101 +++++++++++++++++-
1 file changed, 98 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/snps,designware-i2s.yaml b/Documentation/devicetree/bindings/sound/snps,designware-i2s.yaml
index a970fd264b21..a5ab7f3e49b2 100644
--- a/Documentation/devicetree/bindings/sound/snps,designware-i2s.yaml
+++ b/Documentation/devicetree/bindings/sound/snps,designware-i2s.yaml
@@ -17,6 +17,9 @@ properties:
- const: snps,designware-i2s
- enum:
- snps,designware-i2s
+ - starfive,jh7110-i2stx0
+ - starfive,jh7110-i2stx1
+ - starfive,jh7110-i2srx
reg:
maxItems: 1
@@ -29,15 +32,36 @@ properties:
maxItems: 1
clocks:
- description: Sampling rate reference clock
- maxItems: 1
+ items:
+ - description: Sampling rate reference clock
+ - description: APB clock
+ - description: Audio master clock
+ - description: Inner audio master clock source
+ - description: External audio master clock source
+ - description: Bit clock
+ - description: Left/right channel clock
+ - description: External bit clock
+ - description: External left/right channel clock
+ minItems: 1
clock-names:
- const: i2sclk
+ items:
+ - const: i2sclk
+ - const: apb
+ - const: mclk
+ - const: mclk_inner
+ - const: mclk_ext
+ - const: bclk
+ - const: lrck
+ - const: bclk_ext
+ - const: lrck_ext
+ minItems: 1
resets:
items:
- description: Optional controller resets
+ - description: controller reset of Sampling rate
+ minItems: 1
dmas:
items:
@@ -51,6 +75,17 @@ properties:
- const: rx
minItems: 1
+ starfive,syscon:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: phandle to System Register Controller sys_syscon node.
+ - description: I2S-rx enabled control offset of SYS_SYSCONSAIF__SYSCFG register.
+ - description: I2S-rx enabled control mask
+ description:
+ The phandle to System Register Controller syscon node and the I2S-rx(ADC)
+ enabled control offset and mask of SYS_SYSCONSAIF__SYSCFG register.
+
allOf:
- $ref: dai-common.yaml#
- if:
@@ -66,6 +101,66 @@ allOf:
properties:
"#sound-dai-cells":
const: 0
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: snps,designware-i2s
+ then:
+ properties:
+ clocks:
+ maxItems: 1
+ clock-names:
+ maxItems: 1
+ resets:
+ maxItems: 1
+ else:
+ properties:
+ resets:
+ minItems: 2
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: starfive,jh7110-i2stx0
+ then:
+ properties:
+ clocks:
+ minItems: 5
+ clock-names:
+ minItems: 5
+ required:
+ - resets
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: starfive,jh7110-i2stx1
+ then:
+ properties:
+ clocks:
+ minItems: 9
+ clock-names:
+ minItems: 9
+ required:
+ - resets
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: starfive,jh7110-i2srx
+ then:
+ properties:
+ clocks:
+ minItems: 9
+ clock-names:
+ minItems: 9
+ required:
+ - resets
+ - starfive,syscon
+ else:
+ properties:
+ starfive,syscon: false
required:
- compatible
--
2.25.1
On 02/08/2023 10:42, Xingyu Wu wrote:
> Add the StarFive JH7110 (TX0/TX1/RX channel) SoC support in the bindings
> of Designware I2S controller. The I2S controller needs two reset items''
Thank you for your patch. There is something to discuss/improve.
>
> resets:
> items:
> - description: Optional controller resets
> + - description: controller reset of Sampling rate
> + minItems: 1
>
> dmas:
> items:
> @@ -51,6 +75,17 @@ properties:
> - const: rx
> minItems: 1
>
> + starfive,syscon:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + items:
> + - items:
> + - description: phandle to System Register Controller sys_syscon node.
> + - description: I2S-rx enabled control offset of SYS_SYSCONSAIF__SYSCFG register.
> + - description: I2S-rx enabled control mask
> + description:
> + The phandle to System Register Controller syscon node and the I2S-rx(ADC)
> + enabled control offset and mask of SYS_SYSCONSAIF__SYSCFG register.
> +
> allOf:
> - $ref: dai-common.yaml#
> - if:
> @@ -66,6 +101,66 @@ allOf:
> properties:
> "#sound-dai-cells":
> const: 0
You need to constrain clocks and resets also for all other existing
variants.
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: snps,designware-i2s
> + then:
> + properties:
> + clocks:
> + maxItems: 1
> + clock-names:
> + maxItems: 1
> + resets:
> + maxItems: 1
> + else:
> + properties:
> + resets:
> + minItems: 2
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: starfive,jh7110-i2stx0
> + then:
> + properties:
> + clocks:
> + minItems: 5
Also maxItems
> + clock-names:
> + minItems: 5
Also maxItems
What about resets? 1 or 2 items?
> + required:
> + - resets
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: starfive,jh7110-i2stx1
> + then:
> + properties:
> + clocks:
> + minItems: 9
> + clock-names:
> + minItems: 9
resets?
> + required:
> + - resets
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: starfive,jh7110-i2srx
> + then:
> + properties:
> + clocks:
> + minItems: 9
> + clock-names:
> + minItems: 9
resets?
> + required:
> + - resets
> + - starfive,syscon
> + else:
> + properties:
> + starfive,syscon: false
>
> required:
> - compatible
Best regards,
Krzysztof
On 02/08/2023 10:43, Xingyu Wu wrote:
> Add I2Srx/I2Stx0/I2Stx1 nodes and pins configuration for the
> StarFive JH7110 SoC.
>
> Signed-off-by: Xingyu Wu <[email protected]>
> ---
...
> +
> spi0_pins: spi0-0 {
> mosi-pins {
> pinmux = <GPIOMUX(52, GPOUT_SYS_SPI0_TXD,
> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> index 05f843b8ca03..507312eb6053 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> @@ -512,6 +512,30 @@ tdm: tdm@10090000 {
> status = "disabled";
> };
>
> + i2srx: i2srx@100e0000 {
Node names should be generic, so:
i2s@
> + compatible = "starfive,jh7110-i2srx";
> + reg = <0x0 0x100e0000 0x0 0x1000>;
> + clocks = <&syscrg JH7110_SYSCLK_I2SRX_BCLK_MST>,
> + <&syscrg JH7110_SYSCLK_I2SRX_APB>,
> + <&syscrg JH7110_SYSCLK_MCLK>,
> + <&syscrg JH7110_SYSCLK_MCLK_INNER>,
> + <&mclk_ext>,
> + <&syscrg JH7110_SYSCLK_I2SRX_BCLK>,
> + <&syscrg JH7110_SYSCLK_I2SRX_LRCK>,
> + <&i2srx_bclk_ext>,
> + <&i2srx_lrck_ext>;
> + clock-names = "i2sclk", "apb", "mclk",
> + "mclk_inner", "mclk_ext", "bclk",
> + "lrck", "bclk_ext", "lrck_ext";
> + resets = <&syscrg JH7110_SYSRST_I2SRX_APB>,
> + <&syscrg JH7110_SYSRST_I2SRX_BCLK>;
> + dmas = <0>, <&dma 24>;
> + dma-names = "tx", "rx";
> + starfive,syscon = <&sys_syscon 0x18 0x2>;
> + #sound-dai-cells = <0>;
> + status = "disabled";
> + };
> +
> usb0: usb@10100000 {
> compatible = "starfive,jh7110-usb";
> ranges = <0x0 0x0 0x10100000 0x100000>;
> @@ -736,6 +760,47 @@ spi6: spi@120a0000 {
> status = "disabled";
> };
>
> + i2stx0: i2stx0@120b0000 {
i2s@
> + compatible = "starfive,jh7110-i2stx0";
> + reg = <0x0 0x120b0000 0x0 0x1000>;
> + clocks = <&syscrg JH7110_SYSCLK_I2STX0_BCLK_MST>,
> + <&syscrg JH7110_SYSCLK_I2STX0_APB>,
> + <&syscrg JH7110_SYSCLK_MCLK>,
> + <&syscrg JH7110_SYSCLK_MCLK_INNER>,
> + <&mclk_ext>;
> + clock-names = "i2sclk", "apb", "mclk",
> + "mclk_inner","mclk_ext";
> + resets = <&syscrg JH7110_SYSRST_I2STX0_APB>,
> + <&syscrg JH7110_SYSRST_I2STX0_BCLK>;
> + dmas = <&dma 47>;
> + dma-names = "tx";
> + #sound-dai-cells = <0>;
> + status = "disabled";
> + };
> +
> + i2stx1: i2stx1@120c0000 {
i2s@
Best regards,
Krzysztof
On 2023/8/6 5:02, Krzysztof Kozlowski wrote:
> On 02/08/2023 10:42, Xingyu Wu wrote:
>> Add the StarFive JH7110 (TX0/TX1/RX channel) SoC support in the bindings
>> of Designware I2S controller. The I2S controller needs two reset items''
>
> Thank you for your patch. There is something to discuss/improve.
>
>>
>> resets:
>> items:
>> - description: Optional controller resets
>> + - description: controller reset of Sampling rate
>> + minItems: 1
>>
>> dmas:
>> items:
>> @@ -51,6 +75,17 @@ properties:
>> - const: rx
>> minItems: 1
>>
>> + starfive,syscon:
>> + $ref: /schemas/types.yaml#/definitions/phandle-array
>> + items:
>> + - items:
>> + - description: phandle to System Register Controller sys_syscon node.
>> + - description: I2S-rx enabled control offset of SYS_SYSCONSAIF__SYSCFG register.
>> + - description: I2S-rx enabled control mask
>> + description:
>> + The phandle to System Register Controller syscon node and the I2S-rx(ADC)
>> + enabled control offset and mask of SYS_SYSCONSAIF__SYSCFG register.
>> +
>> allOf:
>> - $ref: dai-common.yaml#
>> - if:
>> @@ -66,6 +101,66 @@ allOf:
>> properties:
>> "#sound-dai-cells":
>> const: 0
>
> You need to constrain clocks and resets also for all other existing
> variants.
>>> + - if:
>> + properties:
>> + compatible:
>> + contains:
>> + const: snps,designware-i2s
>> + then:
>> + properties:
>> + clocks:
>> + maxItems: 1
>> + clock-names:
>> + maxItems: 1
>> + resets:
>> + maxItems: 1
>> + else:
>> + properties:
>> + resets:
>> + minItems: 2
The resets of TX0/TX1/RX on JH7110 SoC are mentioned in 'else' here.
>> + - if:
>> + properties:
>> + compatible:
>> + contains:
>> + const: starfive,jh7110-i2stx0
>> + then:
>> + properties:
>> + clocks:
>> + minItems: 5
>
> Also maxItems
Will add.
>
>> + clock-names:
>> + minItems: 5
>
> Also maxItems
Will add.
>
> What about resets? 1 or 2 items?
Mentioned it in the 'else'.
Or do you mean I should drop the 'else' and add the resets in here?
And is the same for TX1 and RX?
>
>> + required:
>> + - resets
>> + - if:
>> + properties:
>> + compatible:
>> + contains:
>> + const: starfive,jh7110-i2stx1
>> + then:
>> + properties:
>> + clocks:
>> + minItems: 9
>> + clock-names:
>> + minItems: 9
>
> resets?>
>> + required:
>> + - resets
>> + - if:
>> + properties:
>> + compatible:
>> + contains:
>> + const: starfive,jh7110-i2srx
>> + then:
>> + properties:
>> + clocks:
>> + minItems: 9
>> + clock-names:
>> + minItems: 9
>
> resets?
>
>> + required:
>> + - resets
>> + - starfive,syscon
>> + else:
>> + properties:
>> + starfive,syscon: false
>>
>> required:
>> - compatible
>
Best regards,
Xingyu Wu
On 2023/8/7 17:17, Krzysztof Kozlowski wrote:
> On 07/08/2023 11:03, Xingyu Wu wrote:
>>>>> + - if:
>>>> + properties:
>>>> + compatible:
>>>> + contains:
>>>> + const: snps,designware-i2s
>>>> + then:
>>>> + properties:
>>>> + clocks:
>>>> + maxItems: 1
>>>> + clock-names:
>>>> + maxItems: 1
>>>> + resets:
>>>> + maxItems: 1
>>>> + else:
>>>> + properties:
>>>> + resets:
>>>> + minItems: 2
>>
>> The resets of TX0/TX1/RX on JH7110 SoC are mentioned in 'else' here.
>
> Ah, its fine. Clocks seem to be also constrained.
OK, I will keep it here.
>
>>
>>>> + - if:
>>>> + properties:
>>>> + compatible:
>>>> + contains:
>>>> + const: starfive,jh7110-i2stx0
>>>> + then:
>>>> + properties:
>>>> + clocks:
>>>> + minItems: 5
>>>
>>> Also maxItems
>>
>> Will add.
>>
>>>
>>>> + clock-names:
>>>> + minItems: 5
>>>
>>> Also maxItems
>>
>> Will add.
>>
>>>
>>> What about resets? 1 or 2 items?
>>
>> Mentioned it in the 'else'.
>> Or do you mean I should drop the 'else' and add the resets in here?
>> And is the same for TX1 and RX?
>
> It won't be easy to read... probably the binding should be split.
> Anyway, it's fine as is, except the maxItems above.
>
So I will keep it and just add the maxItems in next version.
Thanks,
Xingyu Wu
On 2023/8/6 5:04, Krzysztof Kozlowski wrote:
> On 02/08/2023 10:43, Xingyu Wu wrote:
>> Add I2Srx/I2Stx0/I2Stx1 nodes and pins configuration for the
>> StarFive JH7110 SoC.
>>
>> Signed-off-by: Xingyu Wu <[email protected]>
>> ---
>
> ...
>
>> +
>> spi0_pins: spi0-0 {
>> mosi-pins {
>> pinmux = <GPIOMUX(52, GPOUT_SYS_SPI0_TXD,
>> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> index 05f843b8ca03..507312eb6053 100644
>> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> @@ -512,6 +512,30 @@ tdm: tdm@10090000 {
>> status = "disabled";
>> };
>>
>> + i2srx: i2srx@100e0000 {
>
> Node names should be generic, so:
> i2s@
Will fix. Thanks.
>
>> + compatible = "starfive,jh7110-i2srx";
>> + reg = <0x0 0x100e0000 0x0 0x1000>;
>> + clocks = <&syscrg JH7110_SYSCLK_I2SRX_BCLK_MST>,
>> + <&syscrg JH7110_SYSCLK_I2SRX_APB>,
>> + <&syscrg JH7110_SYSCLK_MCLK>,
>> + <&syscrg JH7110_SYSCLK_MCLK_INNER>,
>> + <&mclk_ext>,
>> + <&syscrg JH7110_SYSCLK_I2SRX_BCLK>,
>> + <&syscrg JH7110_SYSCLK_I2SRX_LRCK>,
>> + <&i2srx_bclk_ext>,
>> + <&i2srx_lrck_ext>;
>> + clock-names = "i2sclk", "apb", "mclk",
>> + "mclk_inner", "mclk_ext", "bclk",
>> + "lrck", "bclk_ext", "lrck_ext";
>> + resets = <&syscrg JH7110_SYSRST_I2SRX_APB>,
>> + <&syscrg JH7110_SYSRST_I2SRX_BCLK>;
>> + dmas = <0>, <&dma 24>;
>> + dma-names = "tx", "rx";
>> + starfive,syscon = <&sys_syscon 0x18 0x2>;
>> + #sound-dai-cells = <0>;
>> + status = "disabled";
>> + };
>> +
>> usb0: usb@10100000 {
>> compatible = "starfive,jh7110-usb";
>> ranges = <0x0 0x0 0x10100000 0x100000>;
>> @@ -736,6 +760,47 @@ spi6: spi@120a0000 {
>> status = "disabled";
>> };
>>
>> + i2stx0: i2stx0@120b0000 {
>
> i2s@
Will fix.
>
>> + compatible = "starfive,jh7110-i2stx0";
>> + reg = <0x0 0x120b0000 0x0 0x1000>;
>> + clocks = <&syscrg JH7110_SYSCLK_I2STX0_BCLK_MST>,
>> + <&syscrg JH7110_SYSCLK_I2STX0_APB>,
>> + <&syscrg JH7110_SYSCLK_MCLK>,
>> + <&syscrg JH7110_SYSCLK_MCLK_INNER>,
>> + <&mclk_ext>;
>> + clock-names = "i2sclk", "apb", "mclk",
>> + "mclk_inner","mclk_ext";
>> + resets = <&syscrg JH7110_SYSRST_I2STX0_APB>,
>> + <&syscrg JH7110_SYSRST_I2STX0_BCLK>;
>> + dmas = <&dma 47>;
>> + dma-names = "tx";
>> + #sound-dai-cells = <0>;
>> + status = "disabled";
>> + };
>> +
>> + i2stx1: i2stx1@120c0000 {
>
> i2s@
Will fix.
Best regards,
Xingyu Wu
On 07/08/2023 11:03, Xingyu Wu wrote:
>>>> + - if:
>>> + properties:
>>> + compatible:
>>> + contains:
>>> + const: snps,designware-i2s
>>> + then:
>>> + properties:
>>> + clocks:
>>> + maxItems: 1
>>> + clock-names:
>>> + maxItems: 1
>>> + resets:
>>> + maxItems: 1
>>> + else:
>>> + properties:
>>> + resets:
>>> + minItems: 2
>
> The resets of TX0/TX1/RX on JH7110 SoC are mentioned in 'else' here.
Ah, its fine. Clocks seem to be also constrained.
>
>>> + - if:
>>> + properties:
>>> + compatible:
>>> + contains:
>>> + const: starfive,jh7110-i2stx0
>>> + then:
>>> + properties:
>>> + clocks:
>>> + minItems: 5
>>
>> Also maxItems
>
> Will add.
>
>>
>>> + clock-names:
>>> + minItems: 5
>>
>> Also maxItems
>
> Will add.
>
>>
>> What about resets? 1 or 2 items?
>
> Mentioned it in the 'else'.
> Or do you mean I should drop the 'else' and add the resets in here?
> And is the same for TX1 and RX?
It won't be easy to read... probably the binding should be split.
Anyway, it's fine as is, except the maxItems above.
Best regards,
Krzysztof