Architectural MSRs associated with microcode are for P6 or higher.
Add a check to early microcode to detect < P6.
Without a check for < P6 - we end up reading from unimplemented MSRs
on Pentium.
Thanks to Borislav Petkov for suggestion on where to intercept the P5
resulting in fewer cycles and less code to accomplish the fix.
Signed-off-by: Bryan O'Donoghue <[email protected]>
---
arch/x86/kernel/microcode_core_early.c | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kernel/microcode_core_early.c b/arch/x86/kernel/microcode_core_early.c
index 577db84..bd251b3 100644
--- a/arch/x86/kernel/microcode_core_early.c
+++ b/arch/x86/kernel/microcode_core_early.c
@@ -50,8 +50,17 @@ static int __cpuinit x86_vendor(void)
native_cpuid(&eax, &ebx, &ecx, &edx);
- if (CPUID_IS(CPUID_INTEL1, CPUID_INTEL2, CPUID_INTEL3, ebx, ecx, edx))
+ if (CPUID_IS(CPUID_INTEL1, CPUID_INTEL2, CPUID_INTEL3, ebx, ecx, edx)) {
+
+ eax = 0x00000001;
+ ecx = 0;
+ native_cpuid(&eax, &ebx, &ecx, &edx);
+
+ if (((edx >> 8) & 0xf) < 0x6)
+ return X86_VENDOR_UNKNOWN;
+
return X86_VENDOR_INTEL;
+ }
if (CPUID_IS(CPUID_AMD1, CPUID_AMD2, CPUID_AMD3, ebx, ecx, edx))
return X86_VENDOR_AMD;
--
1.7.10.4