Hi all,
This patch is required for USB support on Tegra30 due to a likely hardware
bug in the PLL_U oscillator which clocks the USB complex.
The other USB patches for Tegra30 and Tegra114 are already on their way
to 3.12, this is the only one left for Tegra30.
Peter, Prashant, any comments on this patch?
Tuomas Tynkkynen (1):
clk: tegra30: Don't wait for PLL_U lock bit
drivers/clk/tegra/clk-tegra30.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--
1.8.1.5
The lock bit on PLL_U does not seem to be working correctly and
sometimes never gets set when waiting for the PLL to come up.
Remove the TEGRA_PLL_USE_LOCK flag to use a constant delay.
Signed-off-by: Tuomas Tynkkynen <[email protected]>
---
drivers/clk/tegra/clk-tegra30.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index e2c6ca0..9103fc8 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -971,7 +971,7 @@ static void __init tegra30_pll_init(void)
/* PLLU */
clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc_base, 0,
0, &pll_u_params, TEGRA_PLLU | TEGRA_PLL_HAS_CPCON |
- TEGRA_PLL_SET_LFCON | TEGRA_PLL_USE_LOCK,
+ TEGRA_PLL_SET_LFCON,
pll_u_freq_table,
NULL);
clk_register_clkdev(clk, "pll_u", NULL);
--
1.8.1.5
On 08/14/2013 02:09 PM, Tuomas Tynkkynen wrote:
> The lock bit on PLL_U does not seem to be working correctly and
> sometimes never gets set when waiting for the PLL to come up.
> Remove the TEGRA_PLL_USE_LOCK flag to use a constant delay.
Tested-by: Stephen Warren <[email protected]>
Acked-by: Stephen Warren <[email protected]>
(Mike I assume you'll take this through the clock tree)
I do suspect there's some underlying issue that needs fixing so that
PLL_U does report lock as expected. However, this fix does enable USB to
work correctly on Tegra30 right now (so I assume it is locking, but just
isn't reporting it), and should have zero negative fallout since nothing
else uses PLL_U. I'm following up internally to work out why the PLL
isn't reporting that it's locking as expected.