enable handling of separate mask registers for Orion SoC GPIOs,
fixing indeed the regression introduced by e59347a
"arm: orion: Use generic irq chip".
Reported-by: Joey Oravec <[email protected]>
Signed-off-by: Holger Brunck <[email protected]>
Signed-off-by: Gerlando Falauto <[email protected]>
Cc: [email protected]
Cc: Simon Guinot <[email protected]>
---
#Cc: <[email protected]> # 3.0.x cfeaa93 genirq: Generic chip: Remove the local cur_regs() function
#Cc: <[email protected]> # 3.0.x 899f0e6 genirq: Generic chip: Add support for per chip type mask cache
#Cc: <[email protected]> # 3.0.x af80b0f genirq: Generic chip: Handle separate mask registers
#Cc: <[email protected]> # 3.0.x
arch/arm/plat-orion/gpio.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c
index ebc0934..0b9f7c3 100644
--- a/arch/arm/plat-orion/gpio.c
+++ b/arch/arm/plat-orion/gpio.c
@@ -583,7 +583,8 @@ void __init orion_gpio_init(struct device_node *np,
ct->handler = handle_edge_irq;
ct->chip.name = ochip->chip.label;
- irq_setup_generic_chip(gc, IRQ_MSK(ngpio), IRQ_GC_INIT_MASK_CACHE,
+ irq_setup_generic_chip(gc, IRQ_MSK(ngpio), IRQ_GC_INIT_MASK_CACHE |
+ IRQ_GC_MASK_CACHE_PER_TYPE,
IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
/* Setup irq domain on top of the generic chip. */
--
1.8.0.1