On Tue, Dec 17, 2013 at 8:37 PM, Sergei Ianovich <[email protected]> wrote:
> ICP DAS LP-8x4x contains FPGA chip. The chip functions as a interrupt
> source providing 16 additional interrupts among other things. The
> interrupt lines are muxed to a GPIO pin. GPIO pins are in turn muxed
> to a CPU interrupt line.
>
> Until pxa is completely converted to device tree, it is impossible
> to use IRQCHIP_DECLARE() and the irqdomain needs to added manually.
>
> Signed-off-by: Sergei Ianovich <[email protected]>
> CC: Arnd Bergmann <[email protected]>
> CC: Linus Walleij <[email protected]>
(...)
> +++ b/drivers/irqchip/irq-lp8x4x.c
Usually combined GPIO+IRQ controllers are put into drivers/gpio but
this is a bit special as it seems to handle also non-GPIO-related IRQs
so let's get some input on this.
> +static unsigned char irq_sys_enabled;
> +static unsigned char irq_high_enabled;
> +static void *base;
> +static int irq_base;
> +static int num_irq = 16;
Please use the state container design pattern and get rid of these
global variables.
This documentation patch describes this pattern and has been
merged for v3.14, so please read this:
http://marc.info/?l=linux-kernel&m=138615980524966&w=2
> +static void lp8x4x_mask_irq(struct irq_data *d)
> +{
> + unsigned mask;
> + int irq = d->irq - irq_base;
Don't calculate hardware IRQ numbers from offsets. Use
irqdomain, which is done for exactly this purpose.
> + if (irq < 8) {
> + irq_high_enabled &= ~(1 << irq);
I usually use the BIT() macro for this, like:
#include <linux/bitops.h>
irq_high_enabled &= ~BIT(irq);
> +static struct irq_chip lp8x4x_irq_chip = {
> + .name = "FPGA",
> + .irq_ack = lp8x4x_mask_irq,
> + .irq_mask = lp8x4x_mask_irq,
> + .irq_mask_ack = lp8x4x_mask_irq,
> + .irq_unmask = lp8x4x_unmask_irq,
> +};
After you have added your state container you will have
a handle to your struct gpio_chip in the cookie passed to
as irqdata.
Then you need to mark the GPIO lines used for IRQs by
doing something similar to this patch in your startup()
and shutdown() callbacks:
http://marc.info/?l=linux-gpio&m=138547223832167&w=2
> +static void lp8x4x_irq_handler(unsigned int irq, struct irq_desc *desc)
> +{> +static void lp8x4x_unmask_irq(struct irq_data *d)
> +{
> + unsigned mask;
> + int irq = d->irq - irq_base;
Use the irqdomain.
> + int loop, n;
> + unsigned long mask;
> + struct irq_chip *chip = irq_desc_get_chip(desc);
> +
> + chained_irq_enter(chip, desc);
> +
> + do {
> + loop = 0;
> + mask = ioread8(base + CLRHILVINT) & 0xff;
> + mask |= (ioread8(base + SECOINT) & 0x1f) << 8;
> + mask |= (ioread8(base + PRIMINT) & 0xe0) << 8;
#define these magic constants so we know what they mean.
0x1f, 0xe0...
> + mask &= (irq_high_enabled | (irq_sys_enabled << 8));
> + for_each_set_bit(n, &mask, BITS_PER_LONG) {
> + loop = 1;
> +
> + generic_handle_irq(irq_base + n);
> + }
> + } while (loop);
If you're going to do it like this then have "loop" be a bool variable.
However I don't quite like this construction, an eternal for() loop
with a break; statement works too, but try to just use the mask and
get rid of the "loop" helper variable.
> + iowrite8(0, base + EOI);
This looks dangerous, what are you doing here?
> +static int lp8x4x_irq_probe(struct platform_device *pdev)
> +{
> + struct resource *rm, *ri;
Explain these names. Usually we call them "res" or something
simple like this.
> + irq_base = irq_alloc_descs(-1, 0, num_irq, 0);
> + if (irq_base < 0) {
> + dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n");
> + return irq_base;
> + }
Instead of doing this, create the descriptors by calling
irq_create_mapping() on all the hardware lines after adding
the irq domain.
> + domain = irq_domain_add_legacy(np, num_irq, irq_base, 0,
> + &lp8x4x_irq_domain_ops, NULL);
> + if (!domain) {
> + dev_err(&pdev->dev, "Failed to add IRQ domain\n");
> + return -ENOMEM;
> + }
Why are you using a legacy irqdomain? You're not dependent
on any specific base so use a linear domain.
> + iowrite8(0, base + CLRRISEINT);
> + iowrite8(0, base + ENRISEINT);
> + iowrite8(0, base + CLRFALLINT);
> + iowrite8(0, base + ENFALLINT);
> + iowrite8(0, base + CLRHILVINT);
> + iowrite8(0, base + ENHILVINT);
> + iowrite8(0, base + ENSYSINT);
> + iowrite8(0, base + SECOINT);
Add a comment explaining what you're doing here.
> +static int __init lp8x4x_irq_init(void)
> +{
> + return platform_driver_register(&lp8x4x_irq_driver);
> +}
> +postcore_initcall(lp8x4x_irq_init);
Do you *have* to do it this early? I guess if it's used for
the UARTs then yes, but make a case for it...
Yours,
Linus Walleij
On Thu, 2014-01-02 at 13:32 +0100, Linus Walleij wrote:
> On Tue, Dec 17, 2013 at 8:37 PM, Sergei Ianovich <[email protected]> wrote:
> Usually combined GPIO+IRQ controllers are put into drivers/gpio but
> this is a bit special as it seems to handle also non-GPIO-related IRQs
> so let's get some input on this.
This one is a plain IRQ controller. It has simple input lines, not GPIO
pins. The chip reports its status to upper level interrupt controller.
The upper level controller is PXA GPIO in this case.
(...)
> > +static struct irq_chip lp8x4x_irq_chip = {
> > + .name = "FPGA",
> > + .irq_ack = lp8x4x_mask_irq,
> > + .irq_mask = lp8x4x_mask_irq,
> > + .irq_mask_ack = lp8x4x_mask_irq,
> > + .irq_unmask = lp8x4x_unmask_irq,
> > +};
>
> After you have added your state container you will have
> a handle to your struct gpio_chip in the cookie passed to
> as irqdata.
>
> Then you need to mark the GPIO lines used for IRQs by
> doing something similar to this patch in your startup()
> and shutdown() callbacks:
> http://marc.info/?l=linux-gpio&m=138547223832167&w=2
The chip requires no GPIO initialization.
(...)
> > + iowrite8(0, base + EOI);
>
> This looks dangerous, what are you doing here?
This is done in kernel source which comes with the device. The
controller won't work without this line.
I cannot know for sure, as I don't have board datasheets or drawings. I
suspect, this clears GPIO line which reports interrupts to the upper
level controller.
(...)
> > +static int __init lp8x4x_irq_init(void)
> > +{
> > + return platform_driver_register(&lp8x4x_irq_driver);
> > +}
> > +postcore_initcall(lp8x4x_irq_init);
>
> Do you *have* to do it this early? I guess if it's used for
> the UARTs then yes, but make a case for it...
PXA isn't DT-only at the moment. As a result, it is impossible
to use IRQCHIP_DECLARE(). So drivers for the on-CPU IRQs and GPIO-IRQs
are loaded using postcore_initcall(). We need to have all irq domain
drivers loaded prior to DT parsing in order to allow normal
initialization of IRQ resources with DT. I'll update the commit message.
The rest of review comment are implemented. The changes don't affect any
other patches in the series. Should I repost the whole series?
Or only this patch?
Thanks.
On Wed, Jan 8, 2014 at 8:01 PM, Sergei Ianovich <[email protected]> wrote:
> On Thu, 2014-01-02 at 13:32 +0100, Linus Walleij wrote:
>> On Tue, Dec 17, 2013 at 8:37 PM, Sergei Ianovich <[email protected]> wrote:
>> Usually combined GPIO+IRQ controllers are put into drivers/gpio but
>> this is a bit special as it seems to handle also non-GPIO-related IRQs
>> so let's get some input on this.
>
> This one is a plain IRQ controller. It has simple input lines, not GPIO
> pins. The chip reports its status to upper level interrupt controller.
> The upper level controller is PXA GPIO in this case.
Hm I don't know why I was deluded into thinking this had something to
do with GPIO. I must have been soft in the head. Sorry about all those
comments ...
I'll re-read the irqchip driver v3.1.
Yours,
Linus Walleij
On Wed, 2014-01-15 at 08:39 +0100, Linus Walleij wrote:
> On Wed, Jan 8, 2014 at 8:01 PM, Sergei Ianovich <[email protected]> wrote:
> Hm I don't know why I was deluded into thinking this had something to
> do with GPIO. I must have been soft in the head. Sorry about all those
> comments ...
It's not your fault for sure. My commit message wasn't clear enough and
needed clarifications. It is better now.
Thanks for constructive reviewing.