Due to implementation of exynos_boot_secondary function
only one secondary core boots on Exynos SoC's.
Two new functions added to power up and power down secondary cores:
static int exynos_core_power_up(unsigned int cpu);
static int exynos_core_power_down(unsigned int cpu).
Tested on linux kernel v3.14-rc2.
Comments and additions would be appreciated.
Thank you.
Tarek.
Tarek Dakhran (1):
ARM: EXYNOS: enable boot all secondary cpus instead 2
arch/arm/mach-exynos/hotplug.c | 11 ++++--
arch/arm/mach-exynos/platsmp.c | 75 ++++++++++++++++++++++++++++-----------
arch/arm/mach-exynos/regs-pmu.h | 5 +++
3 files changed, 68 insertions(+), 23 deletions(-)
--
1.7.10.4
Functions to boot secondary cpus added.
exynos_core_power_up(unsigned int cpu) added for power up any cpu.
exynos_core_power_down(unsigned int cpu) for power down any cpu.
Signed-off-by: Tarek Dakhran <[email protected]>
---
arch/arm/mach-exynos/hotplug.c | 11 ++++--
arch/arm/mach-exynos/platsmp.c | 75 ++++++++++++++++++++++++++++-----------
arch/arm/mach-exynos/regs-pmu.h | 5 +++
3 files changed, 68 insertions(+), 23 deletions(-)
diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
index 5eead53..71982fa 100644
--- a/arch/arm/mach-exynos/hotplug.c
+++ b/arch/arm/mach-exynos/hotplug.c
@@ -90,13 +90,18 @@ static inline void cpu_leave_lowpower(void)
: "cc");
}
+static void exynos_core_power_down(unsigned int cpu)
+{
+ writel_relaxed(0, S5P_ARM_CORE_CONFIGURATION(cpu));
+}
+
static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
{
for (;;) {
- /* make cpu1 to be turned off at next WFI command */
- if (cpu == 1)
- __raw_writel(0, S5P_ARM_CORE1_CONFIGURATION);
+ /* make cpu to be turned off at next WFI command */
+ if (cpu)
+ exynos_core_power_down(cpu);
/*
* here's the WFI
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 8ea02f6..4008fc8 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -88,10 +88,61 @@ static void exynos_secondary_init(unsigned int cpu)
spin_unlock(&boot_lock);
}
+/*
+ * core_power_state is used to get core power state.
+ * returns:
+ * 0x0 - powered off;
+ * 0x3 - powered on;
+ * other values - in process;
+ */
+static unsigned int core_power_state(unsigned int cpu)
+{
+ unsigned int status = readl_relaxed(S5P_ARM_CORE_STATUS(cpu));
+
+ return status & CORE_PWR_STATE_MASK;
+}
+
+#define TIMEOUT 10
+#define DELAY_TIME 1
+
+static int wait_core_power_up(unsigned int cpu)
+{
+ int timeout = TIMEOUT;
+
+ do {
+ /* checking if power controller in reset */
+ if (core_power_state(cpu) == S5P_CORE_LOCAL_PWR_EN)
+ return 0;
+ mdelay(DELAY_TIME);
+ timeout -= DELAY_TIME;
+ } while (timeout > 0);
+
+ return -ETIMEDOUT; /* timeout */
+}
+
+static int exynos_core_power_up(unsigned int cpu)
+{
+ int ret;
+
+ if (core_power_state(cpu) != S5P_CORE_LOCAL_PWR_EN) {
+ writel_relaxed(S5P_CORE_LOCAL_PWR_EN,
+ S5P_ARM_CORE_CONFIGURATION(cpu));
+
+ ret = wait_core_power_up(cpu);
+ if (ret) {
+ pr_debug("timeout powering on CPU%d\n", cpu);
+ return ret; /* timeout */
+ }
+ }
+
+ return 0;
+}
+
static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
unsigned long timeout;
unsigned long phys_cpu = cpu_logical_map(cpu);
+ int ret;
/*
* Set synchronisation state between this boot processor
@@ -109,26 +160,10 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
*/
write_pen_release(phys_cpu);
- if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) {
- __raw_writel(S5P_CORE_LOCAL_PWR_EN,
- S5P_ARM_CORE1_CONFIGURATION);
-
- timeout = 10;
-
- /* wait max 10 ms until cpu1 is on */
- while ((__raw_readl(S5P_ARM_CORE1_STATUS)
- & S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) {
- if (timeout-- == 0)
- break;
-
- mdelay(1);
- }
-
- if (timeout == 0) {
- printk(KERN_ERR "cpu1 power enable failed");
- spin_unlock(&boot_lock);
- return -ETIMEDOUT;
- }
+ ret = exynos_core_power_up(cpu);
+ if (ret) {
+ spin_unlock(&boot_lock);
+ return ret;
}
/*
* Send the secondary CPU a soft interrupt, thereby causing
diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index 7c029ce..4fc1e8f 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -104,6 +104,11 @@
#define S5P_GPS_LOWPWR S5P_PMUREG(0x139C)
#define S5P_GPS_ALIVE_LOWPWR S5P_PMUREG(0x13A0)
+#define CORE_PWR_STATE_MASK 0x3
+
+#define S5P_ARM_CORE_CONFIGURATION(_nr) (S5P_PMUREG(0x2000) + ((_nr) * 0x80))
+#define S5P_ARM_CORE_STATUS(_nr) (S5P_PMUREG(0x2004) + ((_nr) * 0x80))
+
#define S5P_ARM_CORE1_CONFIGURATION S5P_PMUREG(0x2080)
#define S5P_ARM_CORE1_STATUS S5P_PMUREG(0x2084)
--
1.7.10.4
Hi Tarek,
On 11 February 2014 07:45, Tarek Dakhran <[email protected]> wrote:
> Due to implementation of exynos_boot_secondary function
> only one secondary core boots on Exynos SoC's.
Even without this patch I could boot the secondary CPUs on Exynos4210, 4412 and
5250 based boards with the latest Linux kernel (v3.14-rc2+). Is this
patch required for
a specific use case or am I missing something?
---
With warm regards,
Sachin
Hi Tarek,
On 11 February 2014 12:56, Tarek Dakhran <[email protected]> wrote:
> Hi Sachin,
>
>
>
> Current implementation allow to boot only one secondary core.
>
> This patch makes possible to boot 4 cores on Exynos5420 and Exynos5410 SoC's
I also get 4 cores up with the mainline kernel on SMDK 5420 board
without this patch.
Please see log below:
[ 0.000000] Linux version 3.14.0-rc2-00027-gce8ee8a (sachin@linaro)
(gcc version 4.8.2 20130805 (prerelease) (crosstool-NG linaro-1
.13.1-4.8-2013.08 - Linaro GCC 2013.08) ) #76 SMP PREEMPT Tue Feb 11
15:18:30 IST 2014
[ 0.000000] CPU: ARMv7 Processor [412fc0f3] revision 3 (ARMv7), cr=10c5387d
[ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache
[ 0.000000] Machine model: Samsung SMDK5420 board based on EXYNOS5420
[ 0.000000] NR_BANKS too low, ignoring high memory
[ 0.000000] Memory policy: Data cache writealloc
[ 0.000000] CPU EXYNOS5420 (id 0xe5420200)
[ 0.000000] On node 0 totalpages: 522240
[ 0.000000] Normal zone: 1520 pages used for memmap
[ 0.000000] Normal zone: 0 pages reserved
[ 0.000000] Normal zone: 194560 pages, LIFO batch:31
[ 0.000000] HighMem zone: 2576 pages used for memmap
[ 0.000000] HighMem zone: 327680 pages, LIFO batch:31
[ 0.000000] PERCPU: Embedded 7 pages/cpu @ee795000 s7424 r8192 d13056 u32768
[ 0.000000] pcpu-alloc: s7424 r8192 d13056 u32768 alloc=8*4096
[ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3 [0] 4 [0] 5 [0] 6 [0] 7
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on.
Total pages: 520720
[ 0.000000] Kernel command line: root=/dev/mmcblk1p1 rw rootwait
console=ttySAC2,115200n8 init=/linuxrc earlyprintk loglevel=8 no_c
onsole_suspend
[ 0.000000] PID hash table entries: 4096 (order: 2, 16384 bytes)
[ 0.000000] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
[ 0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
[ 0.000000] Memory: 2065876K/2088960K available (3705K kernel code,
227K rwdata, 1124K rodata, 223K init, 263K bss, 23084K reserved
, 1310720K highmem)
[ 0.000000] Virtual kernel memory layout:
[ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB)
[ 0.000000] fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
[ 0.000000] vmalloc : 0xf0000000 - 0xff000000 ( 240 MB)
[ 0.000000] lowmem : 0xc0000000 - 0xef800000 ( 760 MB)
[ 0.000000] pkmap : 0xbfe00000 - 0xc0000000 ( 2 MB)
[ 0.000000] modules : 0xbf000000 - 0xbfe00000 ( 14 MB)
[ 0.000000] .text : 0xc0008000 - 0xc04bf6e8 (4830 kB)
[ 0.000000] .init : 0xc04c0000 - 0xc04f7d00 ( 224 kB)
[ 0.000000] .data : 0xc04f8000 - 0xc0530e80 ( 228 kB)
[ 0.000000] .bss : 0xc0530e8c - 0xc0572e34 ( 264 kB)
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
[ 0.000000] Preemptible hierarchical RCU implementation.
[ 0.000000] NR_IRQS:16 nr_irqs:16 16
[ 0.000000] sched_clock: 32 bits at 200 Hz, resolution 5000000ns,
wraps every 10737418240000000ns
[ 0.000000] Console: colour dummy device 80x30
[ 0.045000] Calibrating delay loop... 1590.88 BogoMIPS (lpj=3977216)
[ 0.045000] pid_max: default: 32768 minimum: 301
[ 0.045000] Mount-cache hash table entries: 512
[ 0.055000] CPU: Testing write buffer coherency: ok
[ 0.055000] CPU0: update cpu_power 1535
[ 0.055000] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
[ 0.055000] Setting up static identity map for 0x20387210 - 0x20387268
[ 0.075000] CPU1: Booted secondary processor
[ 0.125000] CPU1: update cpu_power 1535
[ 0.125000] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
[ 0.135000] CPU2: Booted secondary processor
[ 0.175000] CPU2: update cpu_power 1535
[ 0.175000] CPU2: thread -1, cpu 2, socket 0, mpidr 80000002
[ 0.185000] CPU3: Booted secondary processor
[ 0.235000] CPU3: update cpu_power 1535
[ 0.235000] CPU3: thread -1, cpu 3, socket 0, mpidr 80000003
[ 1.245000] CPU4: failed to boot: -38
[ 2.245000] CPU5: failed to boot: -38
[ 3.255000] CPU6: failed to boot: -38
[ 4.255000] CPU7: failed to boot: -38
[ 4.255000] Brought up 4 CPUs
[ 4.255000] SMP: Total of 4 processors activated.
Regards,
Sachin
>
> On Tue, Feb 11, 2014 at 3:17 PM, Sachin Kamat <[email protected]>
> wrote:
>
>>Hi Tarek,
>
>>
> On 11 February 2014 07:45, Tarek Dakhran <[email protected]> wrote:
>> Due to implementation of exynos_boot_secondary function
>> only one secondary core boots on Exynos SoC's.
>
>>Even without this patch I could boot the secondary CPUs on Exynos4210, 4412
>> and
>>5250 based boards with the latest Linux kernel (v3.14-rc2+). Is this
>>patch required for
>>a specific use case or am I missing something?
>>
>>---
>>With warm regards,
>>Sachin
>
>
>
> Best regards,
>
> Tarek Dakhran
--
With warm regards,
Sachin