This patchset support cpufreq driver for Exynos3250 which uses the Cortex-A7
dual cores and has a target speed of 1.0 GHz and code clean using dev_err/info
instead of pr_err/info function.
This patchset has a dependency on following patchset[1] to support Exynos3250:
[1] https://lkml.org/lkml/2014/4/17/669
Chanwoo Choi (2):
cpufreq: exynos: Use dev_err/info function instead of pr_err/info
cpufreq: exynos: Add new Exynos3250 cpufreq driver
drivers/cpufreq/Kconfig.arm | 11 +++
drivers/cpufreq/Makefile | 1 +
drivers/cpufreq/exynos-cpufreq.c | 25 +++---
drivers/cpufreq/exynos-cpufreq.h | 18 ++++
drivers/cpufreq/exynos3250-cpufreq.c | 158 +++++++++++++++++++++++++++++++++++
5 files changed, 203 insertions(+), 10 deletions(-)
create mode 100644 drivers/cpufreq/exynos3250-cpufreq.c
--
1.8.0
This patch uses dev_err/info function to show accurate log message with device name
instead of pr_err/info function.
Signed-off-by: Chanwoo Choi <[email protected]>
Acked-by: Kyungmin Park <[email protected]>
---
drivers/cpufreq/exynos-cpufreq.c | 21 ++++++++++++---------
drivers/cpufreq/exynos-cpufreq.h | 1 +
2 files changed, 13 insertions(+), 9 deletions(-)
diff --git a/drivers/cpufreq/exynos-cpufreq.c b/drivers/cpufreq/exynos-cpufreq.c
index f99cfe2..8b4bb4a 100644
--- a/drivers/cpufreq/exynos-cpufreq.c
+++ b/drivers/cpufreq/exynos-cpufreq.c
@@ -49,6 +49,7 @@ static int exynos_cpufreq_scale(unsigned int target_freq)
struct cpufreq_policy *policy = cpufreq_cpu_get(0);
unsigned int arm_volt, safe_arm_volt = 0;
unsigned int mpll_freq_khz = exynos_info->mpll_freq_khz;
+ struct device *dev = exynos_info->dev;
unsigned int old_freq;
int index, old_index;
int ret = 0;
@@ -90,8 +91,8 @@ static int exynos_cpufreq_scale(unsigned int target_freq)
/* Firstly, voltage up to increase frequency */
ret = regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
if (ret) {
- pr_err("%s: failed to set cpu voltage to %d\n",
- __func__, arm_volt);
+ dev_err(dev, "failed to set cpu voltage to %d\n",
+ arm_volt);
return ret;
}
}
@@ -100,8 +101,8 @@ static int exynos_cpufreq_scale(unsigned int target_freq)
ret = regulator_set_voltage(arm_regulator, safe_arm_volt,
safe_arm_volt);
if (ret) {
- pr_err("%s: failed to set cpu voltage to %d\n",
- __func__, safe_arm_volt);
+ dev_err(dev, "failed to set cpu voltage to %d\n",
+ safe_arm_volt);
return ret;
}
}
@@ -115,8 +116,8 @@ static int exynos_cpufreq_scale(unsigned int target_freq)
ret = regulator_set_voltage(arm_regulator, arm_volt,
arm_volt);
if (ret) {
- pr_err("%s: failed to set cpu voltage to %d\n",
- __func__, arm_volt);
+ dev_err(dev, "failed to set cpu voltage to %d\n",
+ arm_volt);
goto out;
}
}
@@ -163,6 +164,8 @@ static int exynos_cpufreq_probe(struct platform_device *pdev)
if (!exynos_info)
return -ENOMEM;
+ exynos_info->dev = &pdev->dev;
+
if (soc_is_exynos4210())
ret = exynos4210_cpufreq_init(exynos_info);
else if (soc_is_exynos4212() || soc_is_exynos4412())
@@ -176,13 +179,13 @@ static int exynos_cpufreq_probe(struct platform_device *pdev)
goto err_vdd_arm;
if (exynos_info->set_freq == NULL) {
- pr_err("%s: No set_freq function (ERR)\n", __func__);
+ dev_err(&pdev->dev, "No set_freq function (ERR)\n");
goto err_vdd_arm;
}
arm_regulator = regulator_get(NULL, "vdd_arm");
if (IS_ERR(arm_regulator)) {
- pr_err("%s: failed to get resource vdd_arm\n", __func__);
+ dev_err(&pdev->dev, "failed to get resource vdd_arm\n");
goto err_vdd_arm;
}
@@ -192,7 +195,7 @@ static int exynos_cpufreq_probe(struct platform_device *pdev)
if (!cpufreq_register_driver(&exynos_driver))
return 0;
- pr_err("%s: failed to register cpufreq driver\n", __func__);
+ dev_err(&pdev->dev, "failed to register cpufreq driver\n");
regulator_put(arm_regulator);
err_vdd_arm:
kfree(exynos_info);
diff --git a/drivers/cpufreq/exynos-cpufreq.h b/drivers/cpufreq/exynos-cpufreq.h
index 3ddade8..b72ff10 100644
--- a/drivers/cpufreq/exynos-cpufreq.h
+++ b/drivers/cpufreq/exynos-cpufreq.h
@@ -34,6 +34,7 @@ struct apll_freq {
};
struct exynos_dvfs_info {
+ struct device *dev;
unsigned long mpll_freq_khz;
unsigned int pll_safe_idx;
struct clk *cpu_clk;
--
1.8.0
This patch add new Exynos3250 cpufreq driver to support DVFS (Dynamic Voltage
Frequency Scaling). Exynos3250 uses the Cortex-A7 dual cores and has a target
speed of 1.0 GHz. Exynos3250 cpufreq driver has range from 100MHz to 1000MHz.
Signed-off-by: Chanwoo Choi <[email protected]>
Acked-by: Kyungmin Park <[email protected]>
---
drivers/cpufreq/Kconfig.arm | 11 +++
drivers/cpufreq/Makefile | 1 +
drivers/cpufreq/exynos-cpufreq.c | 4 +-
drivers/cpufreq/exynos-cpufreq.h | 17 ++++
drivers/cpufreq/exynos3250-cpufreq.c | 158 +++++++++++++++++++++++++++++++++++
5 files changed, 190 insertions(+), 1 deletion(-)
create mode 100644 drivers/cpufreq/exynos3250-cpufreq.c
diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index 0e9cce8..8af1bd1 100644
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -28,6 +28,17 @@ config ARM_VEXPRESS_SPC_CPUFREQ
config ARM_EXYNOS_CPUFREQ
bool
+config ARM_EXYNOS3250_CPUFREQ
+ bool "SAMSUNG EXYNOS3250"
+ depends on SOC_EXYNOS3250 && !ARCH_MULTIPLATFORM
+ default y
+ select ARM_EXYNOS_CPUFREQ
+ help
+ This adds the CPUFreq driver for Samsung EXYNOS3250 SoC based on
+ Cortex-A7 dual-core.
+
+ If in doubt, say N.
+
config ARM_EXYNOS4210_CPUFREQ
bool "SAMSUNG EXYNOS4210"
depends on CPU_EXYNOS4210 && !ARCH_MULTIPLATFORM
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
index 0dbb963..18260bb 100644
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -50,6 +50,7 @@ obj-$(CONFIG_ARM_DT_BL_CPUFREQ) += arm_big_little_dt.o
obj-$(CONFIG_ARCH_DAVINCI_DA850) += davinci-cpufreq.o
obj-$(CONFIG_UX500_SOC_DB8500) += dbx500-cpufreq.o
obj-$(CONFIG_ARM_EXYNOS_CPUFREQ) += exynos-cpufreq.o
+obj-$(CONFIG_ARM_EXYNOS3250_CPUFREQ) += exynos3250-cpufreq.o
obj-$(CONFIG_ARM_EXYNOS4210_CPUFREQ) += exynos4210-cpufreq.o
obj-$(CONFIG_ARM_EXYNOS4X12_CPUFREQ) += exynos4x12-cpufreq.o
obj-$(CONFIG_ARM_EXYNOS5250_CPUFREQ) += exynos5250-cpufreq.o
diff --git a/drivers/cpufreq/exynos-cpufreq.c b/drivers/cpufreq/exynos-cpufreq.c
index 8b4bb4a..e72cc60 100644
--- a/drivers/cpufreq/exynos-cpufreq.c
+++ b/drivers/cpufreq/exynos-cpufreq.c
@@ -166,7 +166,9 @@ static int exynos_cpufreq_probe(struct platform_device *pdev)
exynos_info->dev = &pdev->dev;
- if (soc_is_exynos4210())
+ if (soc_is_exynos3250())
+ ret = exynos3250_cpufreq_init(exynos_info);
+ else if (soc_is_exynos4210())
ret = exynos4210_cpufreq_init(exynos_info);
else if (soc_is_exynos4212() || soc_is_exynos4412())
ret = exynos4x12_cpufreq_init(exynos_info);
diff --git a/drivers/cpufreq/exynos-cpufreq.h b/drivers/cpufreq/exynos-cpufreq.h
index b72ff10..9c5e491 100644
--- a/drivers/cpufreq/exynos-cpufreq.h
+++ b/drivers/cpufreq/exynos-cpufreq.h
@@ -26,6 +26,15 @@ enum cpufreq_level_index {
.mps = ((m) << 16 | (p) << 8 | (s)), \
}
+#define APLL_FREQ_EXYNOS3(f, a0, a1, a2, a3, a4, a5, b0, b1, b2, m, p, s) \
+ { \
+ .freq = (f) * 1000, \
+ .clk_div_cpu0 = ((a0) | (a1) << 4 | (a2) << 16 | (a3) << 20 | \
+ (a4) << 24 | (a5) << 28), \
+ .clk_div_cpu1 = (b0 << 0 | b1 << 4 | b2 << 8), \
+ .mps = ((m) << 16 | (p) << 8 | (s)), \
+ }
+
struct apll_freq {
unsigned int freq;
u32 clk_div_cpu0;
@@ -44,6 +53,14 @@ struct exynos_dvfs_info {
bool (*need_apll_change)(unsigned int, unsigned int);
};
+#ifdef CONFIG_ARM_EXYNOS3250_CPUFREQ
+extern int exynos3250_cpufreq_init(struct exynos_dvfs_info *);
+#else
+static inline int exynos3250_cpufreq_init(struct exynos_dvfs_info *info)
+{
+ return -EOPNOTSUPP;
+}
+#endif
#ifdef CONFIG_ARM_EXYNOS4210_CPUFREQ
extern int exynos4210_cpufreq_init(struct exynos_dvfs_info *);
#else
diff --git a/drivers/cpufreq/exynos3250-cpufreq.c b/drivers/cpufreq/exynos3250-cpufreq.c
new file mode 100644
index 0000000..71f72b8
--- /dev/null
+++ b/drivers/cpufreq/exynos3250-cpufreq.c
@@ -0,0 +1,158 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * EXYNOS3250 - CPU frequency scaling support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/device.h>
+#include <linux/slab.h>
+#include <linux/cpufreq.h>
+
+#include "exynos-cpufreq.h"
+
+static struct clk *cpu_clk;
+static struct clk *mout_core;
+static struct clk *mout_mpll;
+static struct clk *mout_apll;
+
+static unsigned int exynos3250_volt_table[] = {
+ 1050000, 1050000, 1000000, 950000, 900000,
+ 900000, 900000, 900000, 900000, 900000,
+};
+
+static struct cpufreq_frequency_table exynos3250_freq_table[] = {
+ {0, L0, 1000 * 1000},
+ {0, L1, 900 * 1000},
+ {0, L2, 800 * 1000},
+ {0, L3, 700 * 1000},
+ {0, L4, 600 * 1000},
+ {0, L5, 500 * 1000},
+ {0, L6, 400 * 1000},
+ {0, L7, 300 * 1000},
+ {0, L8, 200 * 1000},
+ {0, L9, 100 * 1000},
+ {0, 0, CPUFREQ_TABLE_END},
+};
+
+static struct apll_freq apll_freq_3250[] = {
+ /*
+ * values:
+ * freq
+ * clock divider for CORE, COREM, ATB, PCLK_DBG, APLL, CORE2
+ * clock divider for COPY, HPM, RESERVED
+ * PLL M, P, S
+ */
+ APLL_FREQ_EXYNOS3(1000, 0, 1, 4, 7, 1, 0, 7, 7, 0, 250, 3, 1),
+ APLL_FREQ_EXYNOS3(900, 0, 1, 3, 7, 1, 0, 7, 7, 0, 300, 4, 1),
+ APLL_FREQ_EXYNOS3(800, 0, 1, 3, 7, 1, 0, 7, 7, 0, 200, 3, 1),
+ APLL_FREQ_EXYNOS3(700, 0, 1, 3, 7, 1, 0, 7, 7, 0, 175, 3, 1),
+ APLL_FREQ_EXYNOS3(600, 0, 1, 3, 7, 1, 0, 7, 7, 0, 400, 4, 2),
+ APLL_FREQ_EXYNOS3(500, 0, 1, 3, 7, 1, 0, 7, 7, 0, 250, 3, 2),
+ APLL_FREQ_EXYNOS3(400, 0, 1, 3, 7, 1, 0, 7, 7, 0, 200, 3, 2),
+ APLL_FREQ_EXYNOS3(300, 0, 1, 3, 5, 1, 0, 7, 7, 0, 400, 4, 3),
+ APLL_FREQ_EXYNOS3(200, 0, 1, 3, 3, 1, 0, 7, 7, 0, 200, 3, 3),
+ APLL_FREQ_EXYNOS3(100, 0, 1, 1, 1, 1, 0, 7, 7, 0, 200, 3, 4),
+};
+
+static void exynos3250_set_clkdiv(unsigned int div_index)
+{
+ unsigned int tmp;
+
+ /* Change Divider - CPU0 */
+ tmp = apll_freq_3250[div_index].clk_div_cpu0;
+
+ __raw_writel(tmp, EXYNOS4_CLKDIV_CPU);
+
+ while (__raw_readl(EXYNOS4_CLKDIV_STATCPU) & 0x11111111)
+ cpu_relax();
+
+ /* Change Divider - CPU1 */
+ tmp = apll_freq_3250[div_index].clk_div_cpu1;
+
+ __raw_writel(tmp, EXYNOS4_CLKDIV_CPU1);
+
+ while (__raw_readl(EXYNOS4_CLKDIV_STATCPU1) & 0x111)
+ cpu_relax();
+}
+
+static void exynos3250_set_apll(unsigned int index)
+{
+ unsigned int tmp, freq = apll_freq_3250[index].freq * 1000;
+ struct clk *clk;
+
+ clk = clk_get_parent(mout_apll);
+
+ /* MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
+ clk_set_parent(mout_core, mout_mpll);
+ do {
+ cpu_relax();
+ tmp = (__raw_readl(EXYNOS4_CLKMUX_STATCPU)
+ >> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT);
+ tmp &= 0x7;
+ } while (tmp != 0x2);
+
+ clk_set_rate(clk, freq);
+
+ /* MUX_CORE_SEL = APLL */
+ clk_set_parent(mout_core, mout_apll);
+ do {
+ cpu_relax();
+ tmp = __raw_readl(EXYNOS4_CLKMUX_STATCPU);
+ tmp &= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK;
+ } while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT));
+}
+
+static void exynos3250_set_frequency(unsigned int old_index,
+ unsigned int new_index)
+{
+ if (old_index > new_index) {
+ exynos3250_set_clkdiv(new_index);
+ exynos3250_set_apll(new_index);
+ } else if (old_index < new_index) {
+ exynos3250_set_apll(new_index);
+ exynos3250_set_clkdiv(new_index);
+ }
+}
+
+int exynos3250_cpufreq_init(struct exynos_dvfs_info *info)
+{
+ unsigned long rate;
+
+ cpu_clk = devm_clk_get(info->dev, "div_core2");
+ if (IS_ERR(cpu_clk))
+ return PTR_ERR(cpu_clk);
+
+ mout_core = devm_clk_get(info->dev, "mout_core");
+ if (IS_ERR(mout_core))
+ return PTR_ERR(mout_core);
+
+ mout_mpll = devm_clk_get(info->dev, "mout_mpll_user_c");
+ if (IS_ERR(mout_mpll))
+ return PTR_ERR(mout_mpll);
+ rate = clk_get_rate(mout_mpll) / 1000;
+
+ mout_apll = devm_clk_get(info->dev, "mout_apll");
+ if (IS_ERR(mout_apll))
+ return PTR_ERR(mout_apll);
+
+ info->mpll_freq_khz = rate;
+ info->pll_safe_idx = L2;
+ info->cpu_clk = cpu_clk;
+
+ info->volt_table = exynos3250_volt_table;
+ info->freq_table = exynos3250_freq_table;
+ info->set_freq = exynos3250_set_frequency;
+
+ return 0;
+}
+EXPORT_SYMBOL(exynos3250_cpufreq_init);
--
1.8.0
Hi Chanwoo,
On 18 April 2014 07:50, Chanwoo Choi <[email protected]> wrote:
> This patchset support cpufreq driver for Exynos3250 which uses the Cortex-A7
> dual cores and has a target speed of 1.0 GHz and code clean using dev_err/info
> instead of pr_err/info function.
Per SoC cpufreq driver which does not use CCF is no more encouraged for new
Exynos platforms. Thomas has already posted patches to make use of
generic cpu freq driver
on Exynos platforms. Please refer to [1] and try to utilize it for
this platform as well.
[1] http://permalink.gmane.org/gmane.linux.kernel.samsung-soc/26886
--
With warm regards,
Sachin
Hi Sachin,
On Fri, Apr 18, 2014 at 5:14 PM, Sachin Kamat <[email protected]> wrote:
> Hi Chanwoo,
>
> On 18 April 2014 07:50, Chanwoo Choi <[email protected]> wrote:
>> This patchset support cpufreq driver for Exynos3250 which uses the Cortex-A7
>> dual cores and has a target speed of 1.0 GHz and code clean using dev_err/info
>> instead of pr_err/info function.
>
> Per SoC cpufreq driver which does not use CCF is no more encouraged for new
> Exynos platforms. Thomas has already posted patches to make use of
> generic cpu freq driver
> on Exynos platforms. Please refer to [1] and try to utilize it for
> this platform as well.
>
> [1] http://permalink.gmane.org/gmane.linux.kernel.samsung-soc/26886
OK, I'll refer to this new patch for cpufreq and rebase it.
Thanks for your reply.
Best Regards,
Chanwoo Choi
Hi Chanwoo, Sachin,
On 19.04.2014 15:43, Chanwoo Choi wrote:
> Hi Sachin,
>
> On Fri, Apr 18, 2014 at 5:14 PM, Sachin Kamat <[email protected]> wrote:
>> Hi Chanwoo,
>>
>> On 18 April 2014 07:50, Chanwoo Choi <[email protected]> wrote:
>>> This patchset support cpufreq driver for Exynos3250 which uses the Cortex-A7
>>> dual cores and has a target speed of 1.0 GHz and code clean using dev_err/info
>>> instead of pr_err/info function.
>>
>> Per SoC cpufreq driver which does not use CCF is no more encouraged for new
>> Exynos platforms. Thomas has already posted patches to make use of
>> generic cpu freq driver
>> on Exynos platforms. Please refer to [1] and try to utilize it for
>> this platform as well.
>>
>> [1] http://permalink.gmane.org/gmane.linux.kernel.samsung-soc/26886
>
> OK, I'll refer to this new patch for cpufreq and rebase it.
>
> Thanks for your reply.
The last version posted by Thomas still had several comments to be
addressed that could lead to quite big changes in the whole design in
next version. According to the information from Thomas, the work on it
is in progress and we should see updated patchset soon.
Best regards,
Tomasz
Hi Tomasz,
On 19 April 2014 19:21, Tomasz Figa <[email protected]> wrote:
> Hi Chanwoo, Sachin,
>
>
> On 19.04.2014 15:43, Chanwoo Choi wrote:
>>
>> Hi Sachin,
>>
>> On Fri, Apr 18, 2014 at 5:14 PM, Sachin Kamat <[email protected]>
>> wrote:
>>>
>>> Hi Chanwoo,
>>>
>>> On 18 April 2014 07:50, Chanwoo Choi <[email protected]> wrote:
>>>>
>>>> This patchset support cpufreq driver for Exynos3250 which uses the
>>>> Cortex-A7
>>>> dual cores and has a target speed of 1.0 GHz and code clean using
>>>> dev_err/info
>>>> instead of pr_err/info function.
>>>
>>>
>>> Per SoC cpufreq driver which does not use CCF is no more encouraged for
>>> new
>>> Exynos platforms. Thomas has already posted patches to make use of
>>> generic cpu freq driver
>>> on Exynos platforms. Please refer to [1] and try to utilize it for
>>> this platform as well.
>>>
>>> [1] http://permalink.gmane.org/gmane.linux.kernel.samsung-soc/26886
>>
>>
>> OK, I'll refer to this new patch for cpufreq and rebase it.
>>
>> Thanks for your reply.
>
>
> The last version posted by Thomas still had several comments to be addressed
> that could lead to quite big changes in the whole design in next version.
> According to the information from Thomas, the work on it is in progress and
> we should see updated patchset soon.
Yes, that is right. I wanted Chanwoo to be aware of this new design
and track the same.
--
With warm regards,
Sachin
On 19.04.2014 16:35, Sachin Kamat wrote:
> Hi Tomasz,
>
>
> On 19 April 2014 19:21, Tomasz Figa <[email protected]> wrote:
>> Hi Chanwoo, Sachin,
>>
>>
>> On 19.04.2014 15:43, Chanwoo Choi wrote:
>>>
>>> Hi Sachin,
>>>
>>> On Fri, Apr 18, 2014 at 5:14 PM, Sachin Kamat <[email protected]>
>>> wrote:
>>>>
>>>> Hi Chanwoo,
>>>>
>>>> On 18 April 2014 07:50, Chanwoo Choi <[email protected]> wrote:
>>>>>
>>>>> This patchset support cpufreq driver for Exynos3250 which uses the
>>>>> Cortex-A7
>>>>> dual cores and has a target speed of 1.0 GHz and code clean using
>>>>> dev_err/info
>>>>> instead of pr_err/info function.
>>>>
>>>>
>>>> Per SoC cpufreq driver which does not use CCF is no more encouraged for
>>>> new
>>>> Exynos platforms. Thomas has already posted patches to make use of
>>>> generic cpu freq driver
>>>> on Exynos platforms. Please refer to [1] and try to utilize it for
>>>> this platform as well.
>>>>
>>>> [1] http://permalink.gmane.org/gmane.linux.kernel.samsung-soc/26886
>>>
>>>
>>> OK, I'll refer to this new patch for cpufreq and rebase it.
>>>
>>> Thanks for your reply.
>>
>>
>> The last version posted by Thomas still had several comments to be addressed
>> that could lead to quite big changes in the whole design in next version.
>> According to the information from Thomas, the work on it is in progress and
>> we should see updated patchset soon.
>
> Yes, that is right. I wanted Chanwoo to be aware of this new design
> and track the same.
>
Sure. Just wanted to make sure this is clear.
Best regards,
Tomasz
On 18 April 2014 07:50, Chanwoo Choi <[email protected]> wrote:
> This patch uses dev_err/info function to show accurate log message with device name
> instead of pr_err/info function.
>
> Signed-off-by: Chanwoo Choi <[email protected]>
> Acked-by: Kyungmin Park <[email protected]>
> ---
> drivers/cpufreq/exynos-cpufreq.c | 21 ++++++++++++---------
> drivers/cpufreq/exynos-cpufreq.h | 1 +
> 2 files changed, 13 insertions(+), 9 deletions(-)
This still looks fine even if we don't take the new driver ?
Acked-by: Viresh Kumar <[email protected]>
> diff --git a/drivers/cpufreq/exynos-cpufreq.c b/drivers/cpufreq/exynos-cpufreq.c
> index f99cfe2..8b4bb4a 100644
> --- a/drivers/cpufreq/exynos-cpufreq.c
> +++ b/drivers/cpufreq/exynos-cpufreq.c
> @@ -49,6 +49,7 @@ static int exynos_cpufreq_scale(unsigned int target_freq)
> struct cpufreq_policy *policy = cpufreq_cpu_get(0);
> unsigned int arm_volt, safe_arm_volt = 0;
> unsigned int mpll_freq_khz = exynos_info->mpll_freq_khz;
> + struct device *dev = exynos_info->dev;
> unsigned int old_freq;
> int index, old_index;
> int ret = 0;
> @@ -90,8 +91,8 @@ static int exynos_cpufreq_scale(unsigned int target_freq)
> /* Firstly, voltage up to increase frequency */
> ret = regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
> if (ret) {
> - pr_err("%s: failed to set cpu voltage to %d\n",
> - __func__, arm_volt);
> + dev_err(dev, "failed to set cpu voltage to %d\n",
> + arm_volt);
> return ret;
> }
> }
> @@ -100,8 +101,8 @@ static int exynos_cpufreq_scale(unsigned int target_freq)
> ret = regulator_set_voltage(arm_regulator, safe_arm_volt,
> safe_arm_volt);
> if (ret) {
> - pr_err("%s: failed to set cpu voltage to %d\n",
> - __func__, safe_arm_volt);
> + dev_err(dev, "failed to set cpu voltage to %d\n",
> + safe_arm_volt);
> return ret;
> }
> }
> @@ -115,8 +116,8 @@ static int exynos_cpufreq_scale(unsigned int target_freq)
> ret = regulator_set_voltage(arm_regulator, arm_volt,
> arm_volt);
> if (ret) {
> - pr_err("%s: failed to set cpu voltage to %d\n",
> - __func__, arm_volt);
> + dev_err(dev, "failed to set cpu voltage to %d\n",
> + arm_volt);
> goto out;
> }
> }
> @@ -163,6 +164,8 @@ static int exynos_cpufreq_probe(struct platform_device *pdev)
> if (!exynos_info)
> return -ENOMEM;
>
> + exynos_info->dev = &pdev->dev;
> +
> if (soc_is_exynos4210())
> ret = exynos4210_cpufreq_init(exynos_info);
> else if (soc_is_exynos4212() || soc_is_exynos4412())
> @@ -176,13 +179,13 @@ static int exynos_cpufreq_probe(struct platform_device *pdev)
> goto err_vdd_arm;
>
> if (exynos_info->set_freq == NULL) {
> - pr_err("%s: No set_freq function (ERR)\n", __func__);
> + dev_err(&pdev->dev, "No set_freq function (ERR)\n");
> goto err_vdd_arm;
> }
>
> arm_regulator = regulator_get(NULL, "vdd_arm");
> if (IS_ERR(arm_regulator)) {
> - pr_err("%s: failed to get resource vdd_arm\n", __func__);
> + dev_err(&pdev->dev, "failed to get resource vdd_arm\n");
> goto err_vdd_arm;
> }
>
> @@ -192,7 +195,7 @@ static int exynos_cpufreq_probe(struct platform_device *pdev)
> if (!cpufreq_register_driver(&exynos_driver))
> return 0;
>
> - pr_err("%s: failed to register cpufreq driver\n", __func__);
> + dev_err(&pdev->dev, "failed to register cpufreq driver\n");
> regulator_put(arm_regulator);
> err_vdd_arm:
> kfree(exynos_info);
> diff --git a/drivers/cpufreq/exynos-cpufreq.h b/drivers/cpufreq/exynos-cpufreq.h
> index 3ddade8..b72ff10 100644
> --- a/drivers/cpufreq/exynos-cpufreq.h
> +++ b/drivers/cpufreq/exynos-cpufreq.h
> @@ -34,6 +34,7 @@ struct apll_freq {
> };
>
> struct exynos_dvfs_info {
> + struct device *dev;
> unsigned long mpll_freq_khz;
> unsigned int pll_safe_idx;
> struct clk *cpu_clk;
> --
> 1.8.0
>
On 04/21/2014 03:05 PM, Viresh Kumar wrote:
> On 18 April 2014 07:50, Chanwoo Choi <[email protected]> wrote:
>> This patch uses dev_err/info function to show accurate log message with device name
>> instead of pr_err/info function.
>>
>> Signed-off-by: Chanwoo Choi <[email protected]>
>> Acked-by: Kyungmin Park <[email protected]>
>> ---
>> drivers/cpufreq/exynos-cpufreq.c | 21 ++++++++++++---------
>> drivers/cpufreq/exynos-cpufreq.h | 1 +
>> 2 files changed, 13 insertions(+), 9 deletions(-)
>
> This still looks fine even if we don't take the new driver ?
>
> Acked-by: Viresh Kumar <[email protected]>
Thanks for your review.
Best regards,
Chanwoo Choi