2014-06-20 11:35:30

by Maxime Coquelin

Subject: [PATCH] pinctrl: st: Fix irqmux handler

st_gpio_irqmux_handler() reads the status register to find out
which banks inside the controller have pending IRQs.
For each banks having pending IRQs, it calls the corresponding handler.

Problem is that current code restricts the number of possible banks inside the
controller to ST_GPIO_PINS_PER_BANK. This define represents the number of pins
inside a bank, so it shouldn't be used here.

On STiH407, PIO_FRONT0 controller has 10 banks, so IRQs pending in the two
last banks (PIO18 & PIO19) aren't handled.

This patch replace ST_GPIO_PINS_PER_BANK by the number of banks inside the
controller.

Cc: Srinivas Kandagatla <[email protected]>
Cc: Linus Walleij <[email protected]>
Cc: <[email protected]> #v3.15+
Signed-off-by: Maxime Coquelin <[email protected]>
---
drivers/pinctrl/pinctrl-st.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c
index 1bd6363bc9..9f43916 100644
--- a/drivers/pinctrl/pinctrl-st.c
+++ b/drivers/pinctrl/pinctrl-st.c
@@ -1431,7 +1431,7 @@ static void st_gpio_irqmux_handler(unsigned irq, struct irq_desc *desc)

status = readl(info->irqmux_base);

- for_each_set_bit(n, &status, ST_GPIO_PINS_PER_BANK)
+ for_each_set_bit(n, &status, info->nbanks)
__gpio_irq_handler(&info->banks[n]);

chained_irq_exit(chip, desc);
--
1.9.1

2014-06-20 11:38:49

by Srinivas Kandagatla

Subject: Re: [PATCH] pinctrl: st: Fix irqmux handler

On 20/06/14 12:34, Maxime COQUELIN wrote:
> st_gpio_irqmux_handler() reads the status register to find out
> which banks inside the controller have pending IRQs.
> For each banks having pending IRQs, it calls the corresponding handler.
>
> Problem is that current code restricts the number of possible banks inside the
> controller to ST_GPIO_PINS_PER_BANK. This define represents the number of pins
> inside a bank, so it shouldn't be used here.
You are right.
Good find.

Acked-by: Srinivas Kandagatla <[email protected]>


>
> On STiH407, PIO_FRONT0 controller has 10 banks, so IRQs pending in the two
> last banks (PIO18 & PIO19) aren't handled.
>
> This patch replace ST_GPIO_PINS_PER_BANK by the number of banks inside the
> controller.
>
> Cc: Srinivas Kandagatla <[email protected]>
> Cc: Linus Walleij <[email protected]>
> Cc: <[email protected]> #v3.15+
> Signed-off-by: Maxime Coquelin <[email protected]>
> ---
> drivers/pinctrl/pinctrl-st.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c
> index 1bd6363bc9..9f43916 100644
> --- a/drivers/pinctrl/pinctrl-st.c
> +++ b/drivers/pinctrl/pinctrl-st.c
> @@ -1431,7 +1431,7 @@ static void st_gpio_irqmux_handler(unsigned irq, struct irq_desc *desc)
>
> status = readl(info->irqmux_base);
>
> - for_each_set_bit(n, &status, ST_GPIO_PINS_PER_BANK)
> + for_each_set_bit(n, &status, info->nbanks)
> __gpio_irq_handler(&info->banks[n]);
>
> chained_irq_exit(chip, desc);
>

2014-07-07 14:59:23

by Linus Walleij

Subject: Re: [PATCH] pinctrl: st: Fix irqmux handler

On Fri, Jun 20, 2014 at 1:34 PM, Maxime COQUELIN <[email protected]> wrote:

> st_gpio_irqmux_handler() reads the status register to find out
> which banks inside the controller have pending IRQs.
> For each banks having pending IRQs, it calls the corresponding handler.
>
> Problem is that current code restricts the number of possible banks inside the
> controller to ST_GPIO_PINS_PER_BANK. This define represents the number of pins
> inside a bank, so it shouldn't be used here.
>
> On STiH407, PIO_FRONT0 controller has 10 banks, so IRQs pending in the two
> last banks (PIO18 & PIO19) aren't handled.
>
> This patch replace ST_GPIO_PINS_PER_BANK by the number of banks inside the
> controller.
>
> Cc: Srinivas Kandagatla <[email protected]>
> Cc: Linus Walleij <[email protected]>
> Cc: <[email protected]> #v3.15+
> Signed-off-by: Maxime Coquelin <[email protected]>

Patch applied for fixes with Srinivas ACK.

Thanks!
Yours,
Linus Walleij