Syscon is a regmap based framework to help various drivers access misc
bits in registers which does not belong to another module.
For example, Power Module, SYSREGs.
With syscon, ADC can use generic regmap API to access
registers of PMU which are registered into syscon.
This patch does the following
1. Use the syscon and Regmap API instead of ioremappaing the
ADC_PHY register from PMU.
2. Moves the exynos-adc.txt from bindings/arm/samsung/
to bindings/iio/adc/.
3. Updates the Documentation in exynos-adc.txt with syscon phandle
for the ADC nodes.
4. Updates the Dts files for Exynos3250, Exynos4x12, Exynos5250,
Exynos5420 with the syscon phandle.
Tested on Exynos5420 based Peach PIT and Exynos5800 based Peach PI
by verifying sysfs entries provided by HWMON based NTC thermistors.
Tested-By for Exynos3250, Exynos4x12 would be appreciated.
Changes since v1:
Adding syscon description in commit message
Rebased on top of v5 version of ADC for exynos3250 from Changwoo.
iio: adc: exynos_adc: Support Exynos3250 ADC and code clean
https://lkml.org/lkml/2014/6/27/16
Naveen Krishna Chatradhi (4):
iio: exyno-adc: use syscon for PMU register access
Documentation: dt-bindings: move exynos-adc.txt to more iio/adc/
Documentation: dt-bindings: update exynos-adc.txt with syscon handle
ARM: dts: exynos: Add sysreg phandle to ADC node
.../devicetree/bindings/arm/samsung/exynos-adc.txt | 82 ------------------
.../devicetree/bindings/iio/adc/exynos-adc.txt | 87 ++++++++++++++++++++
arch/arm/boot/dts/exynos3250.dtsi | 3 +-
arch/arm/boot/dts/exynos4x12.dtsi | 3 +-
arch/arm/boot/dts/exynos5250.dtsi | 3 +-
arch/arm/boot/dts/exynos5420.dtsi | 3 +-
drivers/iio/adc/exynos_adc.c | 29 +++++--
7 files changed, 115 insertions(+), 95 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
create mode 100644 Documentation/devicetree/bindings/iio/adc/exynos-adc.txt
--
1.7.9.5
The DT bindings in exynos-adc.txt applies to the ADC
driver (exynos-adc.c) developed based on IIO framework.
The bindings are more appropriate to be under
Documentation/devicetree/bindings/iio/adc/
Signed-off-by: Naveen Krishna Chatradhi <[email protected]>
To: [email protected]
---
Changes since v1:
Use git format-patch -M to reduce the patch size
.../{arm/samsung => iio/adc}/exynos-adc.txt | 0
1 file changed, 0 insertions(+), 0 deletions(-)
rename Documentation/devicetree/bindings/{arm/samsung => iio/adc}/exynos-adc.txt (100%)
diff --git a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt b/Documentation/devicetree/bindings/iio/adc/exynos-adc.txt
similarity index 100%
rename from Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
rename to Documentation/devicetree/bindings/iio/adc/exynos-adc.txt
--
1.7.9.5
Instead of using the ADC_PHY register base address, use sysreg phandle
in ADC node to control ADC_PHY configuration register.
This patch adds syscon node for Exynos3250, Exynos4x12, Exynos5250,
and Exynos5420, Exynos5800.
Signed-off-by: Naveen Krishna Chatradhi <[email protected]>
To: [email protected]
---
Changes since v1:
None
arch/arm/boot/dts/exynos3250.dtsi | 3 ++-
arch/arm/boot/dts/exynos4x12.dtsi | 3 ++-
arch/arm/boot/dts/exynos5250.dtsi | 3 ++-
arch/arm/boot/dts/exynos5420.dtsi | 3 ++-
4 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index c5e15db..51c9b0d 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -262,12 +262,13 @@
adc: adc@126C0000 {
compatible = "samsung,exynos3250-adc-v2";
- reg = <0x126C0000 0x100>, <0x10020718 0x4>;
+ reg = <0x126C0000 0x100>;
interrupts = <0 137 0>;
clock-names = "adc", "sclk_adc";
clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
#io-channel-cells = <1>;
io-channel-ranges;
+ samsung,syscon-phandle = <&pmu_system_controller>;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index c5a943d..9a18d9b 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -114,13 +114,14 @@
adc: adc@126C0000 {
compatible = "samsung,exynos-adc-v1";
- reg = <0x126C0000 0x100>, <0x10020718 0x4>;
+ reg = <0x126C0000 0x100>;
interrupt-parent = <&combiner>;
interrupts = <10 3>;
clocks = <&clock CLK_TSADC>;
clock-names = "adc";
#io-channel-cells = <1>;
io-channel-ranges;
+ samsung,syscon-phandle = <&pmu_system_controller>;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 834fb5a..6003777 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -762,12 +762,13 @@
adc: adc@12D10000 {
compatible = "samsung,exynos-adc-v1";
- reg = <0x12D10000 0x100>, <0x10040718 0x4>;
+ reg = <0x12D10000 0x100>
interrupts = <0 106 0>;
clocks = <&clock CLK_ADC>;
clock-names = "adc";
#io-channel-cells = <1>;
io-channel-ranges;
+ samsung,syscon-phandle = <&pmu_system_controller>;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index e385322..6979da8 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -525,12 +525,13 @@
adc: adc@12D10000 {
compatible = "samsung,exynos-adc-v2";
- reg = <0x12D10000 0x100>, <0x10040720 0x4>;
+ reg = <0x12D10000 0x100>;
interrupts = <0 106 0>;
clocks = <&clock CLK_TSADC>;
clock-names = "adc";
#io-channel-cells = <1>;
io-channel-ranges;
+ samsung,syscon-phandle = <&pmu_system_controller>;
status = "disabled";
};
--
1.7.9.5
This patch updates the DT bindings in exynos-adc.txt with the
syscon phandle to the ADC nodes.
Also removes the 2nd "reg" property, which used to carry the
ADC_PHY regiser base from PMU.
Signed-off-by: Naveen Krishna Chatradhi <[email protected]>
To: [email protected]
---
Changes since v1:
rebased on top of Changwoo's v5 ADC patches for exynos3250
iio: adc: exynos_adc: Support Exynos3250 ADC and code clean
https://lkml.org/lkml/2014/6/27/16
.../devicetree/bindings/iio/adc/exynos-adc.txt | 15 ++++++++++-----
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/iio/adc/exynos-adc.txt b/Documentation/devicetree/bindings/iio/adc/exynos-adc.txt
index 0b0ed85..1634df3 100644
--- a/Documentation/devicetree/bindings/iio/adc/exynos-adc.txt
+++ b/Documentation/devicetree/bindings/iio/adc/exynos-adc.txt
@@ -1,10 +1,11 @@
Samsung Exynos Analog to Digital Converter bindings
The devicetree bindings are for the new ADC driver written for
-Exynos4 and upward SoCs from Samsung.
+Exynos4 and Exynos5 series SoCs from Samsung.
+Now supports Exynos3250 too.
New driver handles the following
-1. Supports ADC IF found on EXYNOS4412/EXYNOS5250
+1. Supports ADC IF found on Exynos3250/EXYNOS4412/EXYNOS5 series
and future SoCs from Samsung
2. Add ADC driver under iio/adc framework
3. Also adds the Documentation for device tree bindings
@@ -18,7 +19,7 @@ Required properties:
for controllers compatible with ADC of
Exynos3250.
- reg: Contains ADC register address range (base address and
- length) and the address of the phy enable register.
+ length)
- interrupts: Contains the interrupt information for the timer. The
format is being dependent on which interrupt controller
the Samsung device uses.
@@ -31,6 +32,8 @@ Required properties:
- "sclk_adc" : ADC special clock (only for Exynos3250
and compatible ADC block)
- vdd-supply VDD input supply.
+- samsung,syscon-phandle Contains the PMU system controller node
+ (To access the ADC_PHY register)
Note: child nodes can be added for auto probing from device tree.
@@ -38,7 +41,7 @@ Example: adding device info in dtsi file
adc: adc@12D10000 {
compatible = "samsung,exynos-adc-v1";
- reg = <0x12D10000 0x100>, <0x10040718 0x4>;
+ reg = <0x12D10000 0x100>;
interrupts = <0 106 0>;
#io-channel-cells = <1>;
io-channel-ranges;
@@ -47,13 +50,14 @@ adc: adc@12D10000 {
clock-names = "adc";
vdd-supply = <&buck5_reg>;
+ samsung,syscon-phandle = <&pmu_system_controller>;
};
Example: adding device info in dtsi file for Exynos3250 with additional sclk
adc: adc@126C0000 {
compatible = "samsung,exynos3250-adc-v2";
- reg = <0x126C0000 0x100>, <0x10020718 0x4>;
+ reg = <0x126C0000 0x100>;
interrupts = <0 137 0>;
#io-channel-cells = <1>;
io-channel-ranges;
@@ -62,6 +66,7 @@ adc: adc@126C0000 {
clock-names = "adc", "sclk_adc";
vdd-supply = <&buck5_reg>;
+ samsung,syscon-phandle = <&pmu_system_controller>;
};
Example: Adding child nodes in dts file
--
1.7.9.5
This patch updates the IIO based ADC driver to use syscon and regmap
APIs to access and use PMU registers instead of remapping the PMU
registers in the driver.
Signed-off-by: Naveen Krishna Chatradhi <[email protected]>
To: [email protected]
---
Changes since v1:
None
drivers/iio/adc/exynos_adc.c | 29 ++++++++++++++++++++---------
1 file changed, 20 insertions(+), 9 deletions(-)
diff --git a/drivers/iio/adc/exynos_adc.c b/drivers/iio/adc/exynos_adc.c
index b63e882..60847ef 100644
--- a/drivers/iio/adc/exynos_adc.c
+++ b/drivers/iio/adc/exynos_adc.c
@@ -38,6 +38,8 @@
#include <linux/iio/iio.h>
#include <linux/iio/machine.h>
#include <linux/iio/driver.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
/* EXYNOS4412/5250 ADC_V1 registers definitions */
#define ADC_V1_CON(x) ((x) + 0x00)
@@ -79,11 +81,14 @@
#define EXYNOS_ADC_TIMEOUT (msecs_to_jiffies(100))
+#define EXYNOS_ADCV1_PHY_OFFSET 0x0718
+#define EXYNOS_ADCV2_PHY_OFFSET 0x0720
+
struct exynos_adc {
struct exynos_adc_data *data;
struct device *dev;
void __iomem *regs;
- void __iomem *enable_reg;
+ struct regmap *pmu_map;
struct clk *clk;
struct clk *sclk;
unsigned int irq;
@@ -98,6 +103,7 @@ struct exynos_adc {
struct exynos_adc_data {
int num_channels;
bool needs_sclk;
+ int phy_offset;
void (*init_hw)(struct exynos_adc *info);
void (*exit_hw)(struct exynos_adc *info);
@@ -169,7 +175,7 @@ static void exynos_adc_v1_init_hw(struct exynos_adc *info)
{
u32 con1;
- writel(1, info->enable_reg);
+ regmap_write(info->pmu_map, info->data->phy_offset, 1);
/* set default prescaler values and Enable prescaler */
con1 = ADC_V1_CON_PRSCLV(49) | ADC_V1_CON_PRSCEN;
@@ -183,7 +189,7 @@ static void exynos_adc_v1_exit_hw(struct exynos_adc *info)
{
u32 con;
- writel(0, info->enable_reg);
+ regmap_write(info->pmu_map, info->data->phy_offset, 0);
con = readl(ADC_V1_CON(info->regs));
con |= ADC_V1_CON_STANDBY;
@@ -208,6 +214,7 @@ static void exynos_adc_v1_start_conv(struct exynos_adc *info,
static struct exynos_adc_data const exynos_adc_v1_data = {
.num_channels = MAX_ADC_V1_CHANNELS,
+ .phy_offset = EXYNOS_ADCV1_PHY_OFFSET,
.init_hw = exynos_adc_v1_init_hw,
.exit_hw = exynos_adc_v1_exit_hw,
@@ -219,7 +226,7 @@ static void exynos_adc_v2_init_hw(struct exynos_adc *info)
{
u32 con1, con2;
- writel(1, info->enable_reg);
+ regmap_write(info->pmu_map, info->data->phy_offset, 1);
con1 = ADC_V2_CON1_SOFT_RESET;
writel(con1, ADC_V2_CON1(info->regs));
@@ -236,7 +243,7 @@ static void exynos_adc_v2_exit_hw(struct exynos_adc *info)
{
u32 con;
- writel(0, info->enable_reg);
+ regmap_write(info->pmu_map, info->data->phy_offset, 0);
con = readl(ADC_V2_CON1(info->regs));
con &= ~ADC_CON_EN_START;
@@ -271,10 +278,12 @@ static void exynos_adc_v2_start_conv(struct exynos_adc *info,
static struct exynos_adc_data const exynos_adc_v2_data = {
__EXYNOS_ADC_V2_DATA
+ .phy_offset = EXYNOS_ADCV2_PHY_OFFSET,
};
static struct exynos_adc_data const exynos3250_adc_v2_data = {
__EXYNOS_ADC_V2_DATA
+ .phy_offset = EXYNOS_ADCV1_PHY_OFFSET,
.needs_sclk = true,
};
@@ -437,10 +446,12 @@ static int exynos_adc_probe(struct platform_device *pdev)
if (IS_ERR(info->regs))
return PTR_ERR(info->regs);
- mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
- info->enable_reg = devm_ioremap_resource(&pdev->dev, mem);
- if (IS_ERR(info->enable_reg))
- return PTR_ERR(info->enable_reg);
+ info->pmu_map = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
+ "samsung,syscon-phandle");
+ if (IS_ERR(info->pmu_map)) {
+ dev_err(&pdev->dev, "syscon regmap lookup failed.\n");
+ return PTR_ERR(info->pmu_map);
+ }
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
--
1.7.9.5
Hi Naveen,
On Thu, Jul 17, 2014 at 4:49 PM, Naveen Krishna Chatradhi
<[email protected]> wrote:
> This patch updates the IIO based ADC driver to use syscon and regmap
> APIs to access and use PMU registers instead of remapping the PMU
> registers in the driver.
>
> Signed-off-by: Naveen Krishna Chatradhi <[email protected]>
> To: [email protected]
With only this patch applied, I believe the ADC functionality would be broken.
Perhaps the DT changes should be merged along with this patch?
--
Regards,
Sachin.
Hello Sachin,
On 17 July 2014 17:24, Sachin Kamat <[email protected]> wrote:
> Hi Naveen,
>
> On Thu, Jul 17, 2014 at 4:49 PM, Naveen Krishna Chatradhi
> <[email protected]> wrote:
>> This patch updates the IIO based ADC driver to use syscon and regmap
>> APIs to access and use PMU registers instead of remapping the PMU
>> registers in the driver.
>>
>> Signed-off-by: Naveen Krishna Chatradhi <[email protected]>
>> To: [email protected]
>
> With only this patch applied, I believe the ADC functionality would be broken.
> Perhaps the DT changes should be merged along with this patch?
Jonathan already mentioned that, he would wait for Ack from Kukjin.
With out the dts changes ADC driver will fail to probe but it wont
crash the system.
git bisect should still work.
>
> --
> Regards,
> Sachin.
--
Shine bright,
(: Nav :)
Hi,
On Thursday, July 17, 2014 05:41:16 PM Naveen Krishna Ch wrote:
> Hello Sachin,
>
> On 17 July 2014 17:24, Sachin Kamat <[email protected]> wrote:
> > Hi Naveen,
> >
> > On Thu, Jul 17, 2014 at 4:49 PM, Naveen Krishna Chatradhi
> > <[email protected]> wrote:
> >> This patch updates the IIO based ADC driver to use syscon and regmap
> >> APIs to access and use PMU registers instead of remapping the PMU
> >> registers in the driver.
> >>
> >> Signed-off-by: Naveen Krishna Chatradhi <[email protected]>
> >> To: [email protected]
> >
> > With only this patch applied, I believe the ADC functionality would be broken.
> > Perhaps the DT changes should be merged along with this patch?
>
> Jonathan already mentioned that, he would wait for Ack from Kukjin.
> With out the dts changes ADC driver will fail to probe but it wont
> crash the system.
> git bisect should still work.
Unless someone bisects things related to ADC functionality..
Also patch #1 seems to break device tree ABI (the old dtb will no longer
work with the new kernel).
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics
On 17/07/14 14:56, Bartlomiej Zolnierkiewicz wrote:
>
> Hi,
>
> On Thursday, July 17, 2014 05:41:16 PM Naveen Krishna Ch wrote:
>> Hello Sachin,
>>
>> On 17 July 2014 17:24, Sachin Kamat <[email protected]> wrote:
>>> Hi Naveen,
>>>
>>> On Thu, Jul 17, 2014 at 4:49 PM, Naveen Krishna Chatradhi
>>> <[email protected]> wrote:
>>>> This patch updates the IIO based ADC driver to use syscon and regmap
>>>> APIs to access and use PMU registers instead of remapping the PMU
>>>> registers in the driver.
>>>>
>>>> Signed-off-by: Naveen Krishna Chatradhi <[email protected]>
>>>> To: [email protected]
>>>
>>> With only this patch applied, I believe the ADC functionality would be broken.
>>> Perhaps the DT changes should be merged along with this patch?
>>
>> Jonathan already mentioned that, he would wait for Ack from Kukjin.
>> With out the dts changes ADC driver will fail to probe but it wont
>> crash the system.
>> git bisect should still work.
>
> Unless someone bisects things related to ADC functionality..
>
> Also patch #1 seems to break device tree ABI (the old dtb will no longer
> work with the new kernel).
A very good point. How to avoid this breakage? Supporting the whole
old mechanism is going to be a little painful but without that phandle
is there any other way?
>
> Best regards,
> --
> Bartlomiej Zolnierkiewicz
> Samsung R&D Institute Poland
> Samsung Electronics
>
> --
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