LinuxLists.cc - [PATCH v4 0/4] Add Phytec pbab01 audio support

2014-10-03 13:19:28

Subject: [PATCH v4 0/4] Add Phytec pbab01 audio support

New phyFLEX board audio patchset version.

Small changes made since last version:

- removed unnecessary 'regulator-always-on' in fixed regulators dts
description;
- removed 'fsl,mode = "i2s-slave"' from ssi2 node in dts since it was
already removed from fsl-ssi driver.

Based on branch for-next from
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git

2014-10-03 13:19:32

by Dmitry Lavnikevich

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Subject: [PATCH v4 1/4] ARM: dts: pbab01: move i2c pins and frequency configuration into pfla02

Since pins and frequency are specific to module (pfla02), not base board
(pbab02), it is better to be initialized in corresponding dts file.

This patch fixes i2c2, i2c3 pin configuration which caused messages:

imx6q-pinctrl 20e0000.iomuxc: no groups defined in /soc/aips-bus@02000000/iomuxc@020e0000/i2c2grp
imx6q-pinctrl 20e0000.iomuxc: no groups defined in /soc/aips-bus@02000000/iomuxc@020e0000/i2c3grp
imx6q-pinctrl 20e0000.iomuxc: unable to find group for node i2c2grp
imx6q-pinctrl 20e0000.iomuxc: unable to find group for node i2c3grp

Signed-off-by: Dmitry Lavnikevich <[email protected]>
---
arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi | 22 ----------------------
arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi | 26 ++++++++++++++++++++++++++
2 files changed, 26 insertions(+), 22 deletions(-)

diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi
index 584721264121..f1bdcae5b97d 100644
--- a/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi
@@ -28,9 +28,6 @@
};

&i2c2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- clock-frequency = <100000>;
status = "okay";

tlv320@18 {
@@ -55,9 +52,6 @@
};

&i2c3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- clock-frequency = <100000>;
status = "okay";
};

@@ -84,19 +78,3 @@
&usdhc3 {
status = "okay";
};
-
-&iomuxc {
- pinctrl_i2c2: i2c2grp {
- fsl,pins = <
- MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
- MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
- >;
- };
-
- pinctrl_i2c3: i2c3grp {
- fsl,pins = <
- MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
- MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
- >;
- };
-};
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
index 0e50bb0a6b94..aa2275671d2c 100644
--- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
@@ -162,6 +162,18 @@
};
};

+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ clock-frequency = <100000>;
+};
+
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ clock-frequency = <100000>;
+};
+
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
@@ -235,6 +247,20 @@
>;
};

+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
+ >;
+ };
+
pinctrl_uart3: uart3grp {
fsl,pins = <
MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
--
2.1.1

2014-10-03 13:19:26

by Dmitry Lavnikevich

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Subject: [PATCH v4 2/4] ARM: dts: pbab01: enable I2S audio on phyFLEX-i.MX6 boards

Audio on phyFLEX boards is presented by tlv320aic3007 codec connected
over SSI interface.

Signed-off-by: Dmitry Lavnikevich <[email protected]>
---
arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi | 100 ++++++++++++++++++++++++++-
arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi | 15 ++++
2 files changed, 113 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi
index f1bdcae5b97d..668714052103 100644
--- a/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi
@@ -9,10 +9,73 @@
* http://www.gnu.org/copyleft/gpl.html
*/

+#include <dt-bindings/sound/fsl-imx-audmux.h>
+
/ {
chosen {
linux,stdout-path = &uart4;
};
+
+ regulators {
+ sound_1v8: regulator@2 {
+ compatible = "regulator-fixed";
+ reg = <2>;
+ regulator-name = "i2s-audio-1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ sound_3v3: regulator@3 {
+ compatible = "regulator-fixed";
+ reg = <3>;
+ regulator-name = "i2s-audio-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ };
+
+ tlv320_mclk: oscillator {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <19200000>;
+ clock-output-names = "tlv320-mclk";
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "imx6-phyflex-tlv320aic3007";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,bitclock-master = <&dailink_master>;
+ simple-audio-card,frame-master = <&dailink_master>;
+ simple-audio-card,widgets =
+ "Microphone", "Mic Jack",
+ "Line", "Line In",
+ "Line", "Line Out",
+ "Speaker", "Speaker",
+ "Headphone", "Headphone Jack";
+ simple-audio-card,routing =
+ "Line Out", "LLOUT",
+ "Line Out", "RLOUT",
+ "Speaker", "SPOP",
+ "Speaker", "SPOM",
+ "Headphone Jack", "HPLOUT",
+ "Headphone Jack", "HPROUT",
+ "MIC3L", "Mic Jack",
+ "MIC3R", "Mic Jack",
+ "Mic Jack", "Mic Bias",
+ "LINE1L", "Line In",
+ "LINE1R", "Line In";
+
+ simple-audio-card,cpu {
+ sound-dai = <&ssi2>;
+ };
+
+ dailink_master: simple-audio-card,codec {
+ sound-dai = <&codec>;
+ clocks = <&tlv320_mclk>;
+ };
+ };
+
};

&fec {
@@ -27,12 +90,45 @@
status = "okay";
};

+&ssi2 {
+ status = "okay";
+};
+
+&audmux {
+ status = "okay";
+
+ ssi2 {
+ fsl,audmux-port = <1>;
+ fsl,port-config = <
+ (IMX_AUDMUX_V2_PTCR_TFSDIR |
+ IMX_AUDMUX_V2_PTCR_TFSEL(4) |
+ IMX_AUDMUX_V2_PTCR_TCLKDIR |
+ IMX_AUDMUX_V2_PTCR_TCSEL(4))
+ IMX_AUDMUX_V2_PDCR_RXDSEL(4)
+ >;
+ };
+ pins5 {
+ fsl,audmux-port = <4>;
+ fsl,port-config = <
+ 0x00000000
+ IMX_AUDMUX_V2_PDCR_RXDSEL(1)
+ >;
+ };
+};
+
&i2c2 {
status = "okay";

- tlv320@18 {
- compatible = "ti,tlv320aic3x";
+ codec: tlv320@18 {
+ compatible = "ti,tlv320aic3007";
+ #sound-dai-cells = <0>;
reg = <0x18>;
+ ai3x-micbias-vg = <2>;
+
+ AVDD-supply = <&sound_3v3>;
+ IOVDD-supply = <&sound_3v3>;
+ DRVDD-supply = <&sound_3v3>;
+ DVDD-supply = <&sound_1v8>;
};

stmpe@41 {
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
index aa2275671d2c..d7f34664e008 100644
--- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
@@ -58,6 +58,12 @@
};
};

+&audmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_audmux>;
+ status = "disabled";
+};
+
&ecspi3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3>;
@@ -319,6 +325,15 @@
MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
>;
};
+
+ pinctrl_audmux: audmuxgrp {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0
+ MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0
+ MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x110b0
+ MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
+ >;
+ };
};
};

--
2.1.1

2014-10-03 13:20:38

by Dmitry Lavnikevich

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Subject: [PATCH v4 3/4] ARM: imx_v6_v7_defconfig: enable tlv320aic3x audio codec by default

Used on Phytec PBAB01 board.

Signed-off-by: Dmitry Lavnikevich <[email protected]>
---
arch/arm/configs/imx_v6_v7_defconfig | 1 +
1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index 8fca6e276b69..cac07d67b933 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -210,6 +210,7 @@ CONFIG_SND_SOC_IMX_WM8962=y
CONFIG_SND_SOC_IMX_SGTL5000=y
CONFIG_SND_SOC_IMX_SPDIF=y
CONFIG_SND_SOC_IMX_MC13783=y
+CONFIG_SND_SOC_TLV320AIC3X=y
CONFIG_SND_SIMPLE_CARD=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
--
2.1.1

2014-10-03 13:20:44

by Dmitry Lavnikevich

[permalink] [raw]

Subject: [PATCH v4 4/4] ASoC: tlv320aic3x: fix PLL D configuration

Current caching implementation during regcache_sync() call bypasses
all register writes of values that are already known as default
(regmap reg_defaults). Same time in TLV320AIC3x codecs register 5
(AIC3X_PLL_PROGC_REG) write should be immediately followed by register
6 write (AIC3X_PLL_PROGD_REG) even if it was not changed. Otherwise
both registers will not be written.

This brings to issue that appears particulary in case of 44.1kHz
playback with 19.2MHz master clock. In this case AIC3X_PLL_PROGC_REG
is 0x6e while AIC3X_PLL_PROGD_REG is 0x0 (same as register
default). Thus AIC3X_PLL_PROGC_REG also remains not written and we get
wrong playback speed.

In this patch snd_soc_read() is used to get cached pll values and
snd_soc_write() (unlike regcache_sync() this function doesn't bypasses
hardware default values) to write them to registers.

Signed-off-by: Dmitry Lavnikevich <[email protected]>
---
sound/soc/codecs/tlv320aic3x.c | 13 +++++++++++++
1 file changed, 13 insertions(+)

diff --git a/sound/soc/codecs/tlv320aic3x.c b/sound/soc/codecs/tlv320aic3x.c
index 64f179ee9834..5e8626ae612b 100644
--- a/sound/soc/codecs/tlv320aic3x.c
+++ b/sound/soc/codecs/tlv320aic3x.c
@@ -1121,6 +1121,7 @@ static int aic3x_regulator_event(struct notifier_block *nb,
static int aic3x_set_power(struct snd_soc_codec *codec, int power)
{
struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
+ unsigned int pll_c, pll_d;
int ret;

if (power) {
@@ -1138,6 +1139,18 @@ static int aic3x_set_power(struct snd_soc_codec *codec, int power)
/* Sync reg_cache with the hardware */
regcache_cache_only(aic3x->regmap, false);
regcache_sync(aic3x->regmap);
+
+ /* Rewrite paired PLL D registers in case cached sync skipped
+ * writing one of them and thus caused other one also not
+ * being written
+ */
+ pll_c = snd_soc_read(codec, AIC3X_PLL_PROGC_REG);
+ pll_d = snd_soc_read(codec, AIC3X_PLL_PROGD_REG);
+ if (pll_c == aic3x_reg[AIC3X_PLL_PROGC_REG].def ||
+ pll_d == aic3x_reg[AIC3X_PLL_PROGD_REG].def) {
+ snd_soc_write(codec, AIC3X_PLL_PROGC_REG, pll_c);
+ snd_soc_write(codec, AIC3X_PLL_PROGD_REG, pll_d);
+ }
} else {
/*
* Do soft reset to this codec instance in order to clear
--
2.1.1

2014-10-03 15:09:23

by Mark Brown

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Subject: Re: [PATCH v4 4/4] ASoC: tlv320aic3x: fix PLL D configuration

On Fri, Oct 03, 2014 at 04:18:56PM +0300, Dmitry Lavnikevich wrote:
> Current caching implementation during regcache_sync() call bypasses
> all register writes of values that are already known as default
> (regmap reg_defaults). Same time in TLV320AIC3x codecs register 5

Applied, thanks. This should really have been sent separately to the
other patches - it's not in any way specific to the board and there's no
dependency in either direction.

Attachments:

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2014-10-22 09:09:24

by Dmitry Lavnikevich

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Subject: [PATCH v4 0/3 RESEND] Add Phytec pbab01 audio support

Patch fixing PLL D configuration (number 4 in previous patchset) was
already accepted by Mark Brown. No notes or comments on other patches
was made so resending them in case they were lost.

Based on branch for-next branch of
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git

2014-10-22 09:09:22

by Dmitry Lavnikevich

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Subject: [PATCH v4 RESEND 1/3] ARM: dts: pbab01: move i2c pins and frequency configuration into pfla02

2014-10-22 09:11:26

by Dmitry Lavnikevich

[permalink] [raw]

Subject: [PATCH v4 RESEND 3/3] ARM: imx_v6_v7_defconfig: enable tlv320aic3x audio codec by default

2014-10-22 09:12:36

by Dmitry Lavnikevich

[permalink] [raw]

Subject: [PATCH v4 0/4] Add Phytec pbab01 audio support

Subject: [PATCH v4 1/4] ARM: dts: pbab01: move i2c pins and frequency configuration into pfla02

Subject: [PATCH v4 2/4] ARM: dts: pbab01: enable I2S audio on phyFLEX-i.MX6 boards

Subject: [PATCH v4 3/4] ARM: imx_v6_v7_defconfig: enable tlv320aic3x audio codec by default

Subject: [PATCH v4 4/4] ASoC: tlv320aic3x: fix PLL D configuration

Subject: Re: [PATCH v4 4/4] ASoC: tlv320aic3x: fix PLL D configuration

Attachments:

Subject: [PATCH v4 0/3 RESEND] Add Phytec pbab01 audio support

Subject: [PATCH v4 RESEND 1/3] ARM: dts: pbab01: move i2c pins and frequency configuration into pfla02

Subject: [PATCH v4 RESEND 3/3] ARM: imx_v6_v7_defconfig: enable tlv320aic3x audio codec by default

Subject: [PATCH v4 RESEND 2/3] ARM: dts: pbab01: enable I2S audio on phyFLEX-i.MX6 boards