This patch base on 3.18-rc1, which include mediatek MT65XX SOC
UART driver developed by Matthias Brugger, and
Joe.C's Mediatek MT8127 & MT8135 basic SOC support patch[1].
This patch fix one 8250_mtk.c bug that divisor maybe zero, and add device tree support.
Test ok on MT8127 and MT8135 tablet platform.
Eddie Huang (3):
tty: serial: Fix mediatek UART driver setting baudrate issue
ARM: mediatek: add UART dts for mt8127 and mt8135
DTS: serial: Add bindings document for the Mediatek UARTs
.../devicetree/bindings/serial/mtk-uart.txt | 2 ++
arch/arm/boot/dts/mt8127.dtsi | 34 ++++++++++++++++++++
arch/arm/boot/dts/mt8135.dtsi | 36 ++++++++++++++++++++++
drivers/tty/serial/8250/8250_mtk.c | 4 +--
4 files changed, 74 insertions(+), 2 deletions(-)
In mtk8250_set_termios function, calculating quot value can not be zero,
otherwise, using DIV_ROUND_CLOSEST(port->uartclk, quot * baud) will fail due to
divisor is zero.
Signed-off-by: Eddie Huang <[email protected]>
---
drivers/tty/serial/8250/8250_mtk.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/tty/serial/8250/8250_mtk.c b/drivers/tty/serial/8250/8250_mtk.c
index 8f37d57..6f93123 100644
--- a/drivers/tty/serial/8250/8250_mtk.c
+++ b/drivers/tty/serial/8250/8250_mtk.c
@@ -74,14 +74,14 @@ mtk8250_set_termios(struct uart_port *port, struct ktermios *termios,
/* Set to next lower baudrate supported */
if ((baud == 500000) || (baud == 576000))
baud = 460800;
- quot = DIV_ROUND_CLOSEST(port->uartclk, 4 * baud);
+ quot = DIV_ROUND_UP(port->uartclk, 4 * baud);
} else {
serial_port_out(port, UART_MTK_HIGHS, 0x3);
/* Set to highest baudrate supported */
if (baud >= 1152000)
baud = 921600;
- quot = DIV_ROUND_CLOSEST(port->uartclk, 256 * baud);
+ quot = DIV_ROUND_UP(port->uartclk, 256 * baud);
}
/*
--
1.8.1.1.dirty
This patch add s devicetree document for Mediatek UART.
Signed-off-by: Eddie Huang <[email protected]>
---
Documentation/devicetree/bindings/serial/mtk-uart.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/serial/mtk-uart.txt b/Documentation/devicetree/bindings/serial/mtk-uart.txt
index 48358a3..0eebbfe 100644
--- a/Documentation/devicetree/bindings/serial/mtk-uart.txt
+++ b/Documentation/devicetree/bindings/serial/mtk-uart.txt
@@ -2,6 +2,8 @@
Required properties:
- compatible should contain:
+ * "mediatek,mt8135-uart" for MT8135 compatible UARTS
+ * "mediatek,mt8127-uart" for MT8127 compatible UARTS
* "mediatek,mt6589-uart" for MT6589 compatible UARTS
* "mediatek,mt6582-uart" for MT6582 compatible UARTS
* "mediatek,mt6577-uart" for all compatible UARTS (MT6589, MT6582, MT6577)
--
1.8.1.1.dirty
This add dts support for mt8127 and mt8135 SOC UART
Signed-off-by: Eddie Huang <[email protected]>
---
arch/arm/boot/dts/mt8127.dtsi | 34 ++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/mt8135.dtsi | 36 ++++++++++++++++++++++++++++++++++++
2 files changed, 70 insertions(+)
diff --git a/arch/arm/boot/dts/mt8127.dtsi b/arch/arm/boot/dts/mt8127.dtsi
index 25c9f69..249c218 100644
--- a/arch/arm/boot/dts/mt8127.dtsi
+++ b/arch/arm/boot/dts/mt8127.dtsi
@@ -64,6 +64,12 @@
clock-frequency = <32000>;
#clock-cells = <0>;
};
+
+ uart_clk: dummy26m {
+ compatible = "fixed-clock";
+ clock-frequency = <26000000>;
+ #clock-cells = <0>;
+ };
};
soc {
@@ -89,5 +95,33 @@
<0 0x10214000 0 0x2000>,
<0 0x10216000 0 0x2000>;
};
+
+ uart0: serial@11006000 {
+ compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
+ reg = <0 0x11002000 0 0x400>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&uart_clk>;
+ };
+
+ uart1: serial@11007000 {
+ compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
+ reg = <0 0x11003000 0 0x400>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&uart_clk>;
+ };
+
+ uart2: serial@11008000 {
+ compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
+ reg = <0 0x11004000 0 0x400>;
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&uart_clk>;
+ };
+
+ uart3: serial@11009000 {
+ compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
+ reg = <0 0x11005000 0 0x400>;
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&uart_clk>;
+ };
};
};
diff --git a/arch/arm/boot/dts/mt8135.dtsi b/arch/arm/boot/dts/mt8135.dtsi
index 90a56ad..683b761 100644
--- a/arch/arm/boot/dts/mt8135.dtsi
+++ b/arch/arm/boot/dts/mt8135.dtsi
@@ -86,6 +86,13 @@
clock-frequency = <32000>;
#clock-cells = <0>;
};
+
+ uart_clk: dummy26m {
+ compatible = "fixed-clock";
+ clock-frequency = <26000000>;
+ #clock-cells = <0>;
+ };
+
};
soc {
@@ -111,5 +118,34 @@
<0 0x10214000 0 0x2000>,
<0 0x10216000 0 0x2000>;
};
+
+ uart0: serial@11006000 {
+ compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
+ reg = <0 0x11006000 0 0x400>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&uart_clk>;
+ };
+
+ uart1: serial@11007000 {
+ compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
+ reg = <0 0x11007000 0 0x400>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&uart_clk>;
+ };
+
+ uart2: serial@11008000 {
+ compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
+ reg = <0 0x11008000 0 0x400>;
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&uart_clk>;
+ };
+
+ uart3: serial@11009000 {
+ compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
+ reg = <0 0x11009000 0 0x400>;
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&uart_clk>;
+ };
+
};
};
--
1.8.1.1.dirty
2014-10-22 15:12 GMT+02:00 Eddie Huang <[email protected]>:
> This add dts support for mt8127 and mt8135 SOC UART
>
> Signed-off-by: Eddie Huang <[email protected]>
> ---
> arch/arm/boot/dts/mt8127.dtsi | 34 ++++++++++++++++++++++++++++++++++
> arch/arm/boot/dts/mt8135.dtsi | 36 ++++++++++++++++++++++++++++++++++++
> 2 files changed, 70 insertions(+)
>
> diff --git a/arch/arm/boot/dts/mt8127.dtsi b/arch/arm/boot/dts/mt8127.dtsi
> index 25c9f69..249c218 100644
> --- a/arch/arm/boot/dts/mt8127.dtsi
> +++ b/arch/arm/boot/dts/mt8127.dtsi
> @@ -64,6 +64,12 @@
> clock-frequency = <32000>;
> #clock-cells = <0>;
> };
> +
> + uart_clk: dummy26m {
> + compatible = "fixed-clock";
> + clock-frequency = <26000000>;
> + #clock-cells = <0>;
> + };
> };
>
> soc {
> @@ -89,5 +95,33 @@
> <0 0x10214000 0 0x2000>,
> <0 0x10216000 0 0x2000>;
> };
> +
> + uart0: serial@11006000 {
> + compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
> + reg = <0 0x11002000 0 0x400>;
> + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
As long as the interrupt polarity patches from Joe are not
merged,IRQ_TYPE_LEVEL_LOW triggers won't work as the GIC does not
support them.
> + clocks = <&uart_clk>;
> + };
> +
> + uart1: serial@11007000 {
> + compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
> + reg = <0 0x11003000 0 0x400>;
> + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&uart_clk>;
> + };
> +
> + uart2: serial@11008000 {
> + compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
> + reg = <0 0x11004000 0 0x400>;
> + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&uart_clk>;
> + };
> +
> + uart3: serial@11009000 {
> + compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
> + reg = <0 0x11005000 0 0x400>;
> + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&uart_clk>;
> + };
> };
> };
> diff --git a/arch/arm/boot/dts/mt8135.dtsi b/arch/arm/boot/dts/mt8135.dtsi
> index 90a56ad..683b761 100644
> --- a/arch/arm/boot/dts/mt8135.dtsi
> +++ b/arch/arm/boot/dts/mt8135.dtsi
> @@ -86,6 +86,13 @@
> clock-frequency = <32000>;
> #clock-cells = <0>;
> };
> +
> + uart_clk: dummy26m {
> + compatible = "fixed-clock";
> + clock-frequency = <26000000>;
> + #clock-cells = <0>;
> + };
> +
> };
>
> soc {
> @@ -111,5 +118,34 @@
> <0 0x10214000 0 0x2000>,
> <0 0x10216000 0 0x2000>;
> };
> +
> + uart0: serial@11006000 {
> + compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
> + reg = <0 0x11006000 0 0x400>;
> + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&uart_clk>;
> + };
> +
> + uart1: serial@11007000 {
> + compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
> + reg = <0 0x11007000 0 0x400>;
> + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&uart_clk>;
> + };
> +
> + uart2: serial@11008000 {
> + compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
> + reg = <0 0x11008000 0 0x400>;
> + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&uart_clk>;
> + };
> +
> + uart3: serial@11009000 {
> + compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
> + reg = <0 0x11009000 0 0x400>;
> + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&uart_clk>;
> + };
> +
> };
> };
> --
> 1.8.1.1.dirty
>
--
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