2014-11-05 06:09:28

by Wan Zongshun

Subject: [PATCH v3 1/3] mmc:sdhci: Add a quirk for AMD SDHC transfer mode register need to be cleared for cmd without data

SDHC controller in AMD chipsets require SDHC transfer mode
register to be cleared for commands without data. The issue was
uncovered during testing eMMC cards on KB/ML based platforms

Signed-off-by: Vincent Wan <[email protected]>
Signed-off-by: Wan Zongshun <[email protected]>
Signed-off-by: Arindam Nath <[email protected]>
Tested-by: Vikram B <[email protected]>
Tested-by: Raghavendra Swamy <[email protected]>
---
drivers/mmc/host/sdhci.c | 9 +++++++--
include/linux/mmc/sdhci.h | 2 ++
2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index f895ab0..a743d52 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -915,10 +915,15 @@ static void sdhci_set_transfer_mode(struct sdhci_host *host,
struct mmc_data *data = cmd->data;

if (data == NULL) {
+ if (host->quirks2 &
+ SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
+ sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
+ } else {
/* clear Auto CMD settings for no data CMDs */
- mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
- sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
+ mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
+ sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
+ }
return;
}

diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h
index 931ac5e..ae7f357 100644
--- a/include/linux/mmc/sdhci.h
+++ b/include/linux/mmc/sdhci.h
@@ -102,6 +102,8 @@ struct sdhci_host {
#define SDHCI_QUIRK2_STOP_WITH_TC (1<<8)
/* Controller does not support 64-bit DMA */
#define SDHCI_QUIRK2_BROKEN_64_BIT_DMA (1<<9)
+/* need clear transfer mode register before send cmd */
+#define SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD (1<<10)

int irq; /* Device IRQ */
void __iomem *ioaddr; /* Mapped address */
--
1.8.1.2

2014-11-05 10:57:54

by Ulf Hansson

Subject: Re: [PATCH v3 1/3] mmc:sdhci: Add a quirk for AMD SDHC transfer mode register need to be cleared for cmd without data

On 5 November 2014 07:09, Vincent Wan <[email protected]> wrote:
> SDHC controller in AMD chipsets require SDHC transfer mode
> register to be cleared for commands without data. The issue was
> uncovered during testing eMMC cards on KB/ML based platforms
>
> Signed-off-by: Vincent Wan <[email protected]>
> Signed-off-by: Wan Zongshun <[email protected]>
> Signed-off-by: Arindam Nath <[email protected]>
> Tested-by: Vikram B <[email protected]>
> Tested-by: Raghavendra Swamy <[email protected]>

Thanks! Applied for next.

Kind regards
Uffe

> ---
> drivers/mmc/host/sdhci.c | 9 +++++++--
> include/linux/mmc/sdhci.h | 2 ++
> 2 files changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
> index f895ab0..a743d52 100644
> --- a/drivers/mmc/host/sdhci.c
> +++ b/drivers/mmc/host/sdhci.c
> @@ -915,10 +915,15 @@ static void sdhci_set_transfer_mode(struct sdhci_host *host,
> struct mmc_data *data = cmd->data;
>
> if (data == NULL) {
> + if (host->quirks2 &
> + SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
> + sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
> + } else {
> /* clear Auto CMD settings for no data CMDs */
> - mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
> - sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
> + mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
> + sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
> SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
> + }
> return;
> }
>
> diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h
> index 931ac5e..ae7f357 100644
> --- a/include/linux/mmc/sdhci.h
> +++ b/include/linux/mmc/sdhci.h
> @@ -102,6 +102,8 @@ struct sdhci_host {
> #define SDHCI_QUIRK2_STOP_WITH_TC (1<<8)
> /* Controller does not support 64-bit DMA */
> #define SDHCI_QUIRK2_BROKEN_64_BIT_DMA (1<<9)
> +/* need clear transfer mode register before send cmd */
> +#define SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD (1<<10)
>
> int irq; /* Device IRQ */
> void __iomem *ioaddr; /* Mapped address */
> --
> 1.8.1.2
>