by Chanwoo Choi

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Subject: Re: [PATCH 03/19] clk: samsung: exynos5433: Add clocks for CMU_PERIC domain

On 12/09/2014 03:13 PM, Pankaj Dubey wrote:
>
>
> On Tuesday 09 December 2014 06:42 AM, Chanwoo Choi wrote:
>> Hi Pankaj,
>>
>> On 12/08/2014 08:31 PM, Pankaj Dubey wrote:
>>> Hi Chanwoo,
>>>
>>> On Tuesday 02 December 2014 02:19 PM, Chanwoo Choi wrote:
>>>> This patch adds missing divider/gate clocks of CMU_PERIC domain
>>>> which includes I2S/PCM/SPDIF/PWM/SLIMBUS IPs. The SPI/I2S may use
>>>> external input clock which has 'ioclk_*' prefix.
>>>>
>>>> Cc: Sylwester Nawrocki <[email protected]>
>>>> Cc: Tomasz Figa <[email protected]>
>>>> Signed-off-by: Chanwoo Choi <[email protected]>
>>>> [ideal.song: Change clk flags of to pclk_gpio_* clk, pclk_gpio_* should be always on.]
>>>> Signed-off-by: Inha Song <[email protected]>
>>>> Acked-by: Inki Dae <[email protected]>
>>>> Acked-by: Geunsik Lim <[email protected]>
>>>> ---
>>>> drivers/clk/samsung/clk-exynos5433.c | 80 +++++++++++++++++++++++++++++++++-
>>>> include/dt-bindings/clock/exynos5433.h | 34 ++++++++++++++-
>>>> 2 files changed, 112 insertions(+), 2 deletions(-)
>>>>
>>>> diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
>>>> index 88e8cac..a48b36c 100644
>>>> --- a/drivers/clk/samsung/clk-exynos5433.c
>>>> +++ b/drivers/clk/samsung/clk-exynos5433.c
>>>> @@ -256,6 +256,14 @@ static struct samsung_fixed_rate_clock top_fixed_clks[] __initdata = {
>>>> FRATE(0, "ioclk_audiocdclk0", NULL, CLK_IS_ROOT, 100000000),
>>>> /* Xi2s1SDI input clock for SPDIF */
>>>> FRATE(0, "ioclk_spdif_extclk", NULL, CLK_IS_ROOT, 100000000),
>>>> + /* XspiCLK[4:0] input clock for SPI */
>>>> + FRATE(0, "ioclk_spi4_clk_in", NULL, CLK_IS_ROOT, 50000000),
>>>> + FRATE(0, "ioclk_spi3_clk_in", NULL, CLK_IS_ROOT, 50000000),
>>>> + FRATE(0, "ioclk_spi2_clk_in", NULL, CLK_IS_ROOT, 50000000),
>>>> + FRATE(0, "ioclk_spi1_clk_in", NULL, CLK_IS_ROOT, 50000000),
>>>> + FRATE(0, "ioclk_spi0_clk_in", NULL, CLK_IS_ROOT, 50000000),
>>>> + /* Xi2s1SCLK input clock for I2S1_BCLK */
>>>> + FRATE(0, "ioclk_i2s1_bclk_in", NULL, CLK_IS_ROOT, 12288000),
>>>> };
>>>>
>>>> static struct samsung_mux_clock top_mux_clks[] __initdata = {
>>>> @@ -760,6 +768,7 @@ CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif",
>>>> * Register offset definitions for CMU_PERIC
>>>> */
>>>> #define DIV_PERIC 0x0600
>>>> +#define DIV_STAT_PERIC 0x0700
>>>> #define ENABLE_ACLK_PERIC 0x0800
>>>> #define ENABLE_PCLK_PERIC0 0x0900
>>>> #define ENABLE_PCLK_PERIC1 0x0904
>>>> @@ -770,6 +779,7 @@ CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif",
>>>>
>>>> static unsigned long peric_clk_regs[] __initdata = {
>>>> DIV_PERIC,
>>>> + DIV_STAT_PERIC,
>>>
>>> IMO, this line should have been added in first place itself when you added peric_clk_regs.
>>
>> Why? I want to locate it according to address base.
>
> Since DIV_PERIC and DIV_STAT_PERIC both has same address base, why not to add DIV_STAT_PERIC at the same place when you added DIV_PERIC?

I mean the register offset instead of address base.
DIV_PERIC(0x0600) is less than DIV_STAT_PERIC(0x0700).
So, I want to locate DIV_STAT_PERIC on behind DIV_PERIC in ascending order.

But, It is just minor issue.

Best Regards,
Chanwoo Choi

>
> Anyways, this was just my opinion as I don't see any dependency why we should add it here? I left this up to you.
>
>>
>>>
>>>> ENABLE_ACLK_PERIC,
>>>> ENABLE_PCLK_PERIC0,
>>>> ENABLE_PCLK_PERIC1,
>>>> @@ -779,14 +789,57 @@ static unsigned long peric_clk_regs[] __initdata = {
>>>> ENABLE_IP_PERIC2,
>>>> };
>>>>
>>>> +static struct samsung_div_clock peric_div_clks[] __initdata = {
>>>> + /* DIV_PERIC */
>>>> + DIV(CLK_DIV_SCLK_SCI, "div_sclk_sci", "fin_pll", DIV_PERIC, 4, 8),
>>>
>>> As per UM I have DIV_SCLK_SCI has 4 bit wide as [7:4] please cross verify.
>>
>> You're right. It is my mistake. I'll fix it.
>>
>> Best Regards,
>> Chanwoo Choi
>>
> Thanks,
> Pankaj Dubey
>

2014-12-09 07:48:20

by Pankaj Dubey

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Subject: Re: [PATCH 12/19] clk: samsung: exynos5433: Add clocks for CMU_GSCL domain

Hi Chanwoo,

On Tuesday 02 December 2014 02:19 PM, Chanwoo Choi wrote:
> This patch adds the divider/gate of CMU_GSCL domain which contains gscaler
> clocks.
>
> Cc: Sylwester Nawrocki <[email protected]>
> Cc: Tomasz Figa <[email protected]>
> Signed-off-by: Chanwoo Choi <[email protected]>
> Acked-by: Inki Dae <[email protected]>
> Acked-by: Geunsik Lim <[email protected]>
> ---
> .../devicetree/bindings/clock/exynos5433-clock.txt | 8 ++
> drivers/clk/samsung/clk-exynos5433.c | 144 +++++++++++++++++++++
> include/dt-bindings/clock/exynos5433.h | 37 +++++-
> 3 files changed, 188 insertions(+), 1 deletion(-)
>

[snip]

> }
> CLK_OF_DECLARE(exynos5433_cmu_g3d, "samsung,exynos5433-cmu-g3d",
> exynos5433_cmu_g3d_init);
> +
> +/*
> + * Register offset definitions for CMU_GSCL
> + */
> +#define MUX_SEL_GSCL 0x0200
> +#define MUX_ENABLE_GSCL 0x0300
> +#define MUX_STAT_GSCL 0x0400
> +#define ENABLE_ACLK_GSCL 0x0800
> +#define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 0x0804
> +#define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 0x0808
> +#define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 0x080c
> +#define ENABLE_PCLK_GSCL 0x0900
> +#define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 0x0904
> +#define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 0x0908
> +#define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 0x090c
> +#define ENABLE_IP_GSCL0 0x0b00
> +#define ENABLE_IP_GSCL1 0x0b04
> +#define ENABLE_IP_GSCL_SECURE_SMMU_GSCL0 0x0b08
> +#define ENABLE_IP_GSCL_SECURE_SMMU_GSCL1 0x0b0c
> +#define ENABLE_IP_GSCL_SECURE_SMMU_GSCL2 0x0b10
> +

nit: tabspace after #define should be changed to one whitespace.

> +static unsigned long gscl_clk_regs[] __initdata = {
> + MUX_SEL_GSCL,
> + MUX_ENABLE_GSCL,
> + MUX_STAT_GSCL,
> + ENABLE_ACLK_GSCL,
> + ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0,
> + ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1,
> + ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2,
> + ENABLE_PCLK_GSCL,
> + ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0,
> + ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1,
> + ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2,
> + ENABLE_IP_GSCL0,
> + ENABLE_IP_GSCL1,
> + ENABLE_IP_GSCL_SECURE_SMMU_GSCL0,
> + ENABLE_IP_GSCL_SECURE_SMMU_GSCL1,
> + ENABLE_IP_GSCL_SECURE_SMMU_GSCL2,
> +};
> +
> +/* list of all parent clock list */
> +PNAME(aclk_gscl_111_user_p) = { "fin_pll", "aclk_gscl_111", };
> +PNAME(aclk_gscl_333_user_p) = { "fin_pll", "aclk_gscl_333", };
> +
> +static struct samsung_mux_clock gscl_mux_clks[] __initdata = {
> + /* MUX_SEL_GSCL */
> + MUX(CLK_MOUT_ACLK_GSCL_111_USER, "mout_aclk_gscl_111_user",
> + aclk_gscl_111_user_p, MUX_SEL_GSCL, 4, 1),
> + MUX(CLK_MOUT_ACLK_GSCL_333_USER, "mout_aclk_gscl_333_user",
> + aclk_gscl_333_user_p, MUX_SEL_GSCL, 4, 1),

aclk_gscl_333_user mux clock has a shift of '0'.

> +};
> +

Thanks,
Pankaj Dubey