Update hardware ephy parameter to improve pcie compatibility.
These series of patch include the ephy update of following adapters.
rtl8168g
rtl8168gu
rtl8411b
rtl8411
rtl8168fb
rtl8168e-vl
rtl8168dp
rtl8105
rtl8402
Chunhao Lin (9):
r8169:update rtl8168g ephy parameter
r8169:update rtl8168gu ephy parameter
r8169:update rtl8411b ephy parameter
r8169:update rtl8411 ephy parameter
r8169:update rtl8168fb ephy parameter
r8169:update rtl8168e-vl ephy parameter
r8169:update rtl8168dp ephy parameter
r8169:update rtl8105e ephy parameter
r8169:update rtl8402 ephy parameter
drivers/net/ethernet/realtek/r8169.c | 127 +++++++++++++++++++++--------------
1 file changed, 78 insertions(+), 49 deletions(-)
--
1.9.1
Update rtl8168g ephy parameter to improve pcie compatibility.
Signed-off-by: Chunhao Lin <[email protected]>
---
drivers/net/ethernet/realtek/r8169.c | 24 +++++++++++++++++++++---
1 file changed, 21 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ethernet/realtek/r8169.c b/drivers/net/ethernet/realtek/r8169.c
index b9c2f33..b77efcb 100644
--- a/drivers/net/ethernet/realtek/r8169.c
+++ b/drivers/net/ethernet/realtek/r8169.c
@@ -5919,7 +5919,7 @@ static void rtl_hw_start_8411(struct rtl8169_private *tp)
rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
}
-static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
+static void rtl_hw_start_8168g(struct rtl8169_private *tp)
{
void __iomem *ioaddr = tp->mmio_addr;
struct pci_dev *pdev = tp->pci_dev;
@@ -5954,6 +5954,24 @@ static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
rtl_pcie_state_l2l3_enable(tp, false);
}
+static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
+{
+ void __iomem *ioaddr = tp->mmio_addr;
+ static const struct ephy_info e_info_8168g_1[] = {
+ { 0x00, 0x0000, 0x0008 },
+ { 0x0c, 0x37d0, 0x0820 },
+ { 0x1e, 0x0000, 0x0001 },
+ { 0x19, 0x8000, 0x0000 }
+ };
+
+ rtl_hw_start_8168g(tp);
+
+ /* disable aspm and clock request before access ephy */
+ RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
+ RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
+ rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
+}
+
static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
{
void __iomem *ioaddr = tp->mmio_addr;
@@ -5964,7 +5982,7 @@ static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
{ 0x1e, 0xffff, 0x20eb }
};
- rtl_hw_start_8168g_1(tp);
+ rtl_hw_start_8168g(tp);
/* disable aspm and clock request before access ephy */
RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
@@ -5983,7 +6001,7 @@ static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
{ 0x1e, 0x0000, 0x2000 }
};
- rtl_hw_start_8168g_1(tp);
+ rtl_hw_start_8168g(tp);
/* disable aspm and clock request before access ephy */
RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
--
1.9.1
Update rtl8105e ephy parameter to improve pcie compatibility.
Signed-off-by: Chunhao Lin <[email protected]>
---
drivers/net/ethernet/realtek/r8169.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/realtek/r8169.c b/drivers/net/ethernet/realtek/r8169.c
index 42eda35..56bcd96 100644
--- a/drivers/net/ethernet/realtek/r8169.c
+++ b/drivers/net/ethernet/realtek/r8169.c
@@ -6450,7 +6450,8 @@ static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
{ 0x03, 0, 0x0001 },
{ 0x19, 0, 0x0100 },
{ 0x19, 0, 0x0004 },
- { 0x0a, 0, 0x0020 }
+ { 0x0a, 0, 0x0020 },
+ { 0x05, 0, 0x2000 }
};
/* Force LAN exit from ASPM if Rx/Tx are not idle */
--
1.9.1
Update rtl8411b ephy parameter to improve pcie compatibility.
Signed-off-by: Chunhao Lin <[email protected]>
---
drivers/net/ethernet/realtek/r8169.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/realtek/r8169.c b/drivers/net/ethernet/realtek/r8169.c
index 10aa0b1..9c946df 100644
--- a/drivers/net/ethernet/realtek/r8169.c
+++ b/drivers/net/ethernet/realtek/r8169.c
@@ -6000,10 +6000,11 @@ static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
void __iomem *ioaddr = tp->mmio_addr;
static const struct ephy_info e_info_8411_2[] = {
{ 0x00, 0x0000, 0x0008 },
- { 0x0c, 0x3df0, 0x0200 },
+ { 0x0c, 0x3bf0, 0x0400 },
{ 0x0f, 0xffff, 0x5200 },
{ 0x19, 0x0020, 0x0000 },
- { 0x1e, 0x0000, 0x2000 }
+ { 0x1e, 0x0000, 0x2000 },
+ { 0x06, 0x0000, 0x0010 }
};
rtl_hw_start_8168g(tp);
--
1.9.1
Update rtl8402 ephy parameter to improve pcie compatibility.
Signed-off-by: Chunhao Lin <[email protected]>
---
drivers/net/ethernet/realtek/r8169.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/realtek/r8169.c b/drivers/net/ethernet/realtek/r8169.c
index 56bcd96..d6b64f5 100644
--- a/drivers/net/ethernet/realtek/r8169.c
+++ b/drivers/net/ethernet/realtek/r8169.c
@@ -6478,8 +6478,7 @@ static void rtl_hw_start_8402(struct rtl8169_private *tp)
{
void __iomem *ioaddr = tp->mmio_addr;
static const struct ephy_info e_info_8402[] = {
- { 0x19, 0xffff, 0xff64 },
- { 0x1e, 0, 0x4000 }
+ { 0x19, 0xffff, 0xff64 }
};
rtl_csi_access_enable_2(tp);
--
1.9.1
Update rtl8168dp ephy parameter to improve pcie compatibility.
Signed-off-by: Chunhao Lin <[email protected]>
---
drivers/net/ethernet/realtek/r8169.c | 39 ++++++++----------------------------
1 file changed, 8 insertions(+), 31 deletions(-)
diff --git a/drivers/net/ethernet/realtek/r8169.c b/drivers/net/ethernet/realtek/r8169.c
index a979519..42eda35 100644
--- a/drivers/net/ethernet/realtek/r8169.c
+++ b/drivers/net/ethernet/realtek/r8169.c
@@ -5730,45 +5730,25 @@ static void rtl_hw_start_8168d(struct rtl8169_private *tp)
RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
}
-static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
-{
- void __iomem *ioaddr = tp->mmio_addr;
- struct pci_dev *pdev = tp->pci_dev;
-
- rtl_csi_access_enable_1(tp);
-
- if (tp->dev->mtu <= ETH_DATA_LEN)
- rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
-
- RTL_W8(MaxTxPacketSize, TxPacketMax);
-
- rtl_disable_clock_request(pdev);
-}
-
static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
{
void __iomem *ioaddr = tp->mmio_addr;
struct pci_dev *pdev = tp->pci_dev;
static const struct ephy_info e_info_8168d_4[] = {
- { 0x0b, ~0, 0x48 },
- { 0x19, 0x20, 0x50 },
- { 0x0c, ~0, 0x20 }
+ { 0x0b, 0x0000, 0x0048 },
+ { 0x19, 0x0020, 0x0050 },
+ { 0x0c, 0x0100, 0x0020 },
+ { 0x10, 0x0004, 0x0000 }
};
- int i;
rtl_csi_access_enable_1(tp);
- rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
+ if (tp->dev->mtu <= ETH_DATA_LEN)
+ rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
RTL_W8(MaxTxPacketSize, TxPacketMax);
- for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
- const struct ephy_info *e = e_info_8168d_4 + i;
- u16 w;
-
- w = rtl_ephy_read(tp, e->offset);
- rtl_ephy_write(tp, 0x03, (w & e->mask) | e->bits);
- }
+ rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4));
rtl_enable_clock_request(pdev);
}
@@ -6328,11 +6308,8 @@ static void rtl_hw_start_8168(struct net_device *dev)
break;
case RTL_GIGA_MAC_VER_28:
- rtl_hw_start_8168d_4(tp);
- break;
-
case RTL_GIGA_MAC_VER_31:
- rtl_hw_start_8168dp(tp);
+ rtl_hw_start_8168d_4(tp);
break;
case RTL_GIGA_MAC_VER_32:
--
1.9.1
Update rtl8168e-vl ephy parameter to improve pcie compatibility.
Signed-off-by: Chunhao Lin <[email protected]>
---
drivers/net/ethernet/realtek/r8169.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/realtek/r8169.c b/drivers/net/ethernet/realtek/r8169.c
index 2ff8b73..a979519 100644
--- a/drivers/net/ethernet/realtek/r8169.c
+++ b/drivers/net/ethernet/realtek/r8169.c
@@ -5817,7 +5817,9 @@ static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
struct pci_dev *pdev = tp->pci_dev;
static const struct ephy_info e_info_8168e_2[] = {
{ 0x09, 0x0000, 0x0080 },
- { 0x19, 0x0000, 0x0224 }
+ { 0x19, 0x0000, 0x0224 },
+ { 0x00, 0x0000, 0x0008 },
+ { 0x0c, 0x3df0, 0x0200 }
};
rtl_csi_access_enable_1(tp);
--
1.9.1
Update rtl8411 ephy parameter to improve pcie compatibility.
Signed-off-by: Chunhao Lin <[email protected]>
---
drivers/net/ethernet/realtek/r8169.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ethernet/realtek/r8169.c b/drivers/net/ethernet/realtek/r8169.c
index 9c946df..bb5a3ba 100644
--- a/drivers/net/ethernet/realtek/r8169.c
+++ b/drivers/net/ethernet/realtek/r8169.c
@@ -5904,17 +5904,19 @@ static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
static void rtl_hw_start_8411(struct rtl8169_private *tp)
{
- static const struct ephy_info e_info_8168f_1[] = {
+ static const struct ephy_info e_info_8411[] = {
{ 0x06, 0x00c0, 0x0020 },
{ 0x0f, 0xffff, 0x5200 },
{ 0x1e, 0x0000, 0x4000 },
- { 0x19, 0x0000, 0x0224 }
+ { 0x19, 0x0000, 0x0224 },
+ { 0x00, 0x0000, 0x0008 },
+ { 0x0c, 0x3df0, 0x0200 }
};
rtl_hw_start_8168f(tp);
rtl_pcie_state_l2l3_enable(tp, false);
- rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
+ rtl_ephy_init(tp, e_info_8411, ARRAY_SIZE(e_info_8411));
rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
}
--
1.9.1
Update rtl8168fb ephy parameter to improve pcie compatibility.
Signed-off-by: Chunhao Lin <[email protected]>
---
drivers/net/ethernet/realtek/r8169.c | 28 ++++++++++++++++++++++++++--
1 file changed, 26 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/realtek/r8169.c b/drivers/net/ethernet/realtek/r8169.c
index bb5a3ba..2ff8b73 100644
--- a/drivers/net/ethernet/realtek/r8169.c
+++ b/drivers/net/ethernet/realtek/r8169.c
@@ -5889,7 +5889,9 @@ static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
{ 0x06, 0x00c0, 0x0020 },
{ 0x08, 0x0001, 0x0002 },
{ 0x09, 0x0000, 0x0080 },
- { 0x19, 0x0000, 0x0224 }
+ { 0x19, 0x0000, 0x0224 },
+ { 0x00, 0x0000, 0x0008 },
+ { 0x0c, 0x3df0, 0x0200 }
};
rtl_hw_start_8168f(tp);
@@ -5902,6 +5904,26 @@ static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
}
+static void rtl_hw_start_8168f_2(struct rtl8169_private *tp)
+{
+ void __iomem *ioaddr = tp->mmio_addr;
+ static const struct ephy_info e_info_8168f_2[] = {
+ { 0x09, 0x0000, 0x0080 },
+ { 0x19, 0x0000, 0x0224 },
+ { 0x00, 0x0000, 0x0008 },
+ { 0x0c, 0x3df0, 0x0200 }
+ };
+
+ rtl_hw_start_8168f(tp);
+
+ rtl_ephy_init(tp, e_info_8168f_2, ARRAY_SIZE(e_info_8168f_2));
+
+ rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
+
+ /* Adjust EEE LED frequency */
+ RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
+}
+
static void rtl_hw_start_8411(struct rtl8169_private *tp)
{
static const struct ephy_info e_info_8411[] = {
@@ -6320,9 +6342,11 @@ static void rtl_hw_start_8168(struct net_device *dev)
break;
case RTL_GIGA_MAC_VER_35:
- case RTL_GIGA_MAC_VER_36:
rtl_hw_start_8168f_1(tp);
break;
+ case RTL_GIGA_MAC_VER_36:
+ rtl_hw_start_8168f_2(tp);
+ break;
case RTL_GIGA_MAC_VER_38:
rtl_hw_start_8411(tp);
--
1.9.1
Update rtl8168gu ephy parameter to improve pcie compatibility.
Signed-off-by: Chunhao Lin <[email protected]>
---
drivers/net/ethernet/realtek/r8169.c | 13 +++++++++----
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ethernet/realtek/r8169.c b/drivers/net/ethernet/realtek/r8169.c
index b77efcb..10aa0b1 100644
--- a/drivers/net/ethernet/realtek/r8169.c
+++ b/drivers/net/ethernet/realtek/r8169.c
@@ -5976,10 +5976,15 @@ static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
{
void __iomem *ioaddr = tp->mmio_addr;
static const struct ephy_info e_info_8168g_2[] = {
- { 0x00, 0x0000, 0x0008 },
- { 0x0c, 0x3df0, 0x0200 },
- { 0x19, 0xffff, 0xfc00 },
- { 0x1e, 0xffff, 0x20eb }
+ { 0x00, 0x0008, 0x0000 },
+ { 0x0c, 0x37d0, 0x0820 },
+ { 0x1e, 0x0000, 0x0001 },
+ { 0x19, 0x8000, 0x0000 },
+ { 0x19, 0xffff, 0x7c00 },
+ { 0x1e, 0xffff, 0x20eb },
+ { 0x0d, 0xffff, 0x1666 },
+ { 0x00, 0x0000, 0x0080 },
+ { 0x06, 0xffff, 0xf050 }
};
rtl_hw_start_8168g(tp);
--
1.9.1
From: Chunhao Lin <[email protected]>
Date: Wed, 10 Dec 2014 00:45:54 +0800
> Update hardware ephy parameter to improve pcie compatibility.
This really doesn't tell me anything, I really dislike patch
series like this one.
All of the programming is magic values to magic offsets.
You aren't even trying to describe in the commit log message exactly
what kind of settings are being changed, and exactly how those changes
achieve the stated goal.
Furthermore, the commit description makes no sense at all to me.
How can programming the ethernet MAC PHY have any influence on PCI-E
bus compatability? Or are you programming the PCI bus interface's
PHY?
In what way are you adjusting which settings and in what way do those
adjustments help improve PCI-E bus behavior?
You absolutely must describe exactly what the new programming
is actually doing, precisely, and in detail. I want to know
if some kind of timings are being adjusted, and in what way.
Are some fifo limits being changes? If so, in what way, and
why does that help.
You have to describe what you are doing. Short and non-informative
commit log messages alongside random changes to undocumented magic
constant registers is simply unacceptable.
Chunhao Lin <[email protected]> :
[rtl_hw_start_8168f_1 and rtl_hw_start_8168f_2 changes]
Different ephy_info data, same code. You may consider factoring it out.
--
Ueimor
Chunhao Lin <[email protected]> :
> Update hardware ephy parameter to improve pcie compatibility.
Neither the code nor the commit message helps to figure which
kind of behavioral change should/could be expected.
Bandwidth ? Latency ? Power management ? Compliance ? Stability ?
--
Ueimor
Chunhao Lin <[email protected]> :
[...]
> diff --git a/drivers/net/ethernet/realtek/r8169.c b/drivers/net/ethernet/realtek/r8169.c
> index a979519..42eda35 100644
> --- a/drivers/net/ethernet/realtek/r8169.c
> +++ b/drivers/net/ethernet/realtek/r8169.c
[...]
> static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
> {
> void __iomem *ioaddr = tp->mmio_addr;
> struct pci_dev *pdev = tp->pci_dev;
> static const struct ephy_info e_info_8168d_4[] = {
> - { 0x0b, ~0, 0x48 },
> - { 0x19, 0x20, 0x50 },
> - { 0x0c, ~0, 0x20 }
> + { 0x0b, 0x0000, 0x0048 },
> + { 0x19, 0x0020, 0x0050 },
> + { 0x0c, 0x0100, 0x0020 },
> + { 0x10, 0x0004, 0x0000 }
> };
> - int i;
>
> rtl_csi_access_enable_1(tp);
>
> - rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
> + if (tp->dev->mtu <= ETH_DATA_LEN)
> + rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
[...]
> @@ -6328,11 +6308,8 @@ static void rtl_hw_start_8168(struct net_device *dev)
> break;
>
> case RTL_GIGA_MAC_VER_28:
> - rtl_hw_start_8168d_4(tp);
> - break;
> -
> case RTL_GIGA_MAC_VER_31:
> - rtl_hw_start_8168dp(tp);
> + rtl_hw_start_8168d_4(tp);
RTL_GIGA_MAC_VER_28 would thus use a mtu dependant rtl_tx_performance_tweak
in its hw_start handler but would not include one in its jumbo_ops helpers.
It does not seem completely right.
--
Ueimor
> From: David Miller [mailto:[email protected]]
> Sent: Wednesday, December 10, 2014 7:36 AM
> To: Hau
> Cc: [email protected]; nic_swsd; [email protected]
> Subject: Re: [PATCH net-next 0/9] r8169:update hardware ephy parameter
>
> From: Chunhao Lin <[email protected]>
> Date: Wed, 10 Dec 2014 00:45:54 +0800
>
> > Update hardware ephy parameter to improve pcie compatibility.
>
> This really doesn't tell me anything, I really dislike patch series like this one.
>
> All of the programming is magic values to magic offsets.
>
> You aren't even trying to describe in the commit log message exactly what
> kind of settings are being changed, and exactly how those changes achieve
> the stated goal.
>
> Furthermore, the commit description makes no sense at all to me.
>
> How can programming the ethernet MAC PHY have any influence on PCI-E
> bus compatability? Or are you programming the PCI bus interface's PHY?
>
> In what way are you adjusting which settings and in what way do those
> adjustments help improve PCI-E bus behavior?
>
> You absolutely must describe exactly what the new programming is actually
> doing, precisely, and in detail. I want to know if some kind of timings are
> being adjusted, and in what way.
> Are some fifo limits being changes? If so, in what way, and why does that
> help.
>
> You have to describe what you are doing. Short and non-informative commit
> log messages alongside random changes to undocumented magic constant
> registers is simply unacceptable.
>
These series patch is an alignment with our latest hardware pcie ephy parameters. I will try to explain more on my next patch.
Thanks.