Hi, Xu Wei
This series patch enable Hisilicon HiP01 SoC. The HiP01 SoC series
chip is designed for networking product, it integrates a rich peripheral
interfaces to support network applications and supports both one
core or dual cores and quad cores. The core is Cortex A9.
This series patch rebased on Linux 3.19-rc1.
Best Regards
Wang Long (7):
ARM: debug: add HiP01 debug uart
ARM: hisi: enable HiP01 SoC
ARM: dts: Add hip01-ca9x2 dts file
ARM: config: enable ARCH_HIP01
ARM: hisi: add a common smp_prepares_cpus function
ARM: hisi: rename secondary_startup function
ARM: hisi: enable smp for HiP01
.../bindings/arm/hisilicon/hisilicon.txt | 25 +++++
arch/arm/Kconfig.debug | 10 ++
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/hip01-ca9x2.dts | 51 ++++++++++
arch/arm/boot/dts/hip01.dtsi | 110 +++++++++++++++++++++
arch/arm/configs/hisi_defconfig | 1 +
arch/arm/configs/multi_v7_defconfig | 1 +
arch/arm/mach-hisi/Kconfig | 8 ++
arch/arm/mach-hisi/core.h | 5 +-
arch/arm/mach-hisi/headsmp.S | 2 +-
arch/arm/mach-hisi/hisilicon.c | 10 ++
arch/arm/mach-hisi/hotplug.c | 31 ++++++
arch/arm/mach-hisi/platsmp.c | 56 ++++++++++-
13 files changed, 306 insertions(+), 5 deletions(-)
create mode 100644 arch/arm/boot/dts/hip01-ca9x2.dts
create mode 100644 arch/arm/boot/dts/hip01.dtsi
--
1.8.3.4
As hix5hd2 and hip01 has the same secondary_startup
so rename hix5hd2_secondary_startup to
to hisi_secondary_startup.
the hip01 will use hisi_secondary_startup for the
secondary core boot.
Signed-off-by: Wang Long <[email protected]>
---
arch/arm/mach-hisi/core.h | 2 +-
arch/arm/mach-hisi/headsmp.S | 2 +-
arch/arm/mach-hisi/platsmp.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-hisi/core.h b/arch/arm/mach-hisi/core.h
index 88b1f48..75520b0 100644
--- a/arch/arm/mach-hisi/core.h
+++ b/arch/arm/mach-hisi/core.h
@@ -12,7 +12,7 @@ extern void hi3xxx_cpu_die(unsigned int cpu);
extern int hi3xxx_cpu_kill(unsigned int cpu);
extern void hi3xxx_set_cpu(int cpu, bool enable);
-extern void hix5hd2_secondary_startup(void);
+extern void hisi_secondary_startup(void);
extern struct smp_operations hix5hd2_smp_ops;
extern void hix5hd2_set_cpu(int cpu, bool enable);
extern void hix5hd2_cpu_die(unsigned int cpu);
diff --git a/arch/arm/mach-hisi/headsmp.S b/arch/arm/mach-hisi/headsmp.S
index 278889c..81e35b1 100644
--- a/arch/arm/mach-hisi/headsmp.S
+++ b/arch/arm/mach-hisi/headsmp.S
@@ -11,6 +11,6 @@
__CPUINIT
-ENTRY(hix5hd2_secondary_startup)
+ENTRY(hisi_secondary_startup)
bl v7_invalidate_l1
b secondary_startup
diff --git a/arch/arm/mach-hisi/platsmp.c b/arch/arm/mach-hisi/platsmp.c
index b3c3a58..4a70f56 100644
--- a/arch/arm/mach-hisi/platsmp.c
+++ b/arch/arm/mach-hisi/platsmp.c
@@ -116,7 +116,7 @@ static int hix5hd2_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
phys_addr_t jumpaddr;
- jumpaddr = virt_to_phys(hix5hd2_secondary_startup);
+ jumpaddr = virt_to_phys(hisi_secondary_startup);
hix5hd2_set_scu_boot_addr(HIX5HD2_BOOT_ADDRESS, jumpaddr);
hix5hd2_set_cpu(cpu, true);
arch_send_wakeup_ipi_mask(cpumask_of(cpu));
--
1.8.3.4
As hix5hd2 and hip01 has the same .smp_prepare_cpus
in struct smp_operations, so rename hix5hd2_smp_prepare_cpus
to hisi_common_smp_prepare_cpus.
the hip01 will use hisi_common_smp_prepare_cpus in its
struct smp_operations.
Signed-off-by: Wang Long <[email protected]>
---
arch/arm/mach-hisi/platsmp.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-hisi/platsmp.c b/arch/arm/mach-hisi/platsmp.c
index 575dd82..b3c3a58 100644
--- a/arch/arm/mach-hisi/platsmp.c
+++ b/arch/arm/mach-hisi/platsmp.c
@@ -96,7 +96,7 @@ struct smp_operations hi3xxx_smp_ops __initdata = {
#endif
};
-static void __init hix5hd2_smp_prepare_cpus(unsigned int max_cpus)
+static void __init hisi_common_smp_prepare_cpus(unsigned int max_cpus)
{
hisi_enable_scu_a9();
}
@@ -125,7 +125,7 @@ static int hix5hd2_boot_secondary(unsigned int cpu, struct task_struct *idle)
struct smp_operations hix5hd2_smp_ops __initdata = {
- .smp_prepare_cpus = hix5hd2_smp_prepare_cpus,
+ .smp_prepare_cpus = hisi_common_smp_prepare_cpus,
.smp_boot_secondary = hix5hd2_boot_secondary,
#ifdef CONFIG_HOTPLUG_CPU
.cpu_die = hix5hd2_cpu_die,
--
1.8.3.4
Enable Hisilicon HiP01 SoC. This HiP01 SoC series support both
one core or dual cores and quad cores. The core is Cortex A9.
Signed-off-by: Wang Long <[email protected]>
---
arch/arm/mach-hisi/Kconfig | 8 ++++++++
arch/arm/mach-hisi/hisilicon.c | 10 ++++++++++
2 files changed, 18 insertions(+)
diff --git a/arch/arm/mach-hisi/Kconfig b/arch/arm/mach-hisi/Kconfig
index cd19433..83061ad 100644
--- a/arch/arm/mach-hisi/Kconfig
+++ b/arch/arm/mach-hisi/Kconfig
@@ -22,6 +22,14 @@ config ARCH_HI3xxx
help
Support for Hisilicon Hi36xx SoC family
+config ARCH_HIP01
+ bool "Hisilicon HIP01 family" if ARCH_MULTI_V7
+ select HAVE_ARM_SCU if SMP
+ select HAVE_ARM_TWD if SMP
+ select ARM_GLOBAL_TIMER
+ help
+ Support for Hisilicon HIP01 SoC family
+
config ARCH_HIP04
bool "Hisilicon HiP04 Cortex A15 family" if ARCH_MULTI_V7
select ARM_ERRATA_798181 if SMP
diff --git a/arch/arm/mach-hisi/hisilicon.c b/arch/arm/mach-hisi/hisilicon.c
index 7744c35..76b9070 100644
--- a/arch/arm/mach-hisi/hisilicon.c
+++ b/arch/arm/mach-hisi/hisilicon.c
@@ -72,3 +72,13 @@ static const char *hip04_compat[] __initconst = {
DT_MACHINE_START(HIP04, "Hisilicon HiP04 (Flattened Device Tree)")
.dt_compat = hip04_compat,
MACHINE_END
+
+static const char *hip01_compat[] __initconst = {
+ "hisilicon,hip01",
+ "hisilicon,hip01-ca9x2",
+ NULL,
+};
+
+DT_MACHINE_START(HIP01, "Hisilicon HIP01 (Flattened Device Tree)")
+ .dt_compat = hip01_compat,
+MACHINE_END
--
1.8.3.4
Add dts file for Hisilicon hip01 ca9x2 board
Signed-off-by: Wang Long <[email protected]>
---
.../bindings/arm/hisilicon/hisilicon.txt | 25 +++++
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/hip01-ca9x2.dts | 50 ++++++++++
arch/arm/boot/dts/hip01.dtsi | 110 +++++++++++++++++++++
4 files changed, 186 insertions(+)
create mode 100644 arch/arm/boot/dts/hip01-ca9x2.dts
create mode 100644 arch/arm/boot/dts/hip01.dtsi
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
index f717c7b..35b1bd4 100644
--- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
+++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
@@ -9,6 +9,10 @@ HiP04 D01 Board
Required root node properties:
- compatible = "hisilicon,hip04-d01";
+HiP01 ca9x2 Board
+Required root node properties:
+ - compatible = "hisilicon,hip01-ca9x2";
+
Hisilicon system controller
@@ -37,6 +41,27 @@ Example:
};
-----------------------------------------------------------------------
+Hisilicon HiP01 system controller
+
+Required properties:
+- compatible : "hisilicon,hip01-sysctrl"
+- reg : Register address and size
+
+The HiP01 system controller is mostly compatible with hisilicon
+system controller,but it has some specific control registers for
+HIP01 SoC family, such as slave core boot, and also some same
+registers located at different offset.
+
+Example:
+
+ /* for hip01-ca9x2 */
+ sysctrl: system-controller@10000000 {
+ compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl";
+ reg = <0x10000000 0x1000>;
+ reboot-offset = <0x4>;
+ };
+
+-----------------------------------------------------------------------
Hisilicon CPU controller
Required properties:
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 91bd5bd..70c2fd0 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -105,6 +105,7 @@ dtb-$(CONFIG_ARCH_HI3xxx) += hi3620-hi4511.dtb
dtb-$(CONFIG_ARCH_HIX5HD2) += hisi-x5hd2-dkb.dtb
dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \
ecx-2000.dtb
+dtb-$(CONFIG_ARCH_HIP01) += hip01-ca9x2.dtb
dtb-$(CONFIG_ARCH_HIP04) += hip04-d01.dtb
dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \
integratorcp.dtb
diff --git a/arch/arm/boot/dts/hip01-ca9x2.dts b/arch/arm/boot/dts/hip01-ca9x2.dts
new file mode 100644
index 0000000..3f157ae
--- /dev/null
+++ b/arch/arm/boot/dts/hip01-ca9x2.dts
@@ -0,0 +1,50 @@
+/*
+ * Hisilicon Ltd. HiP01 SoC
+ *
+ * Copyright (C) 2014 Hisilicon Ltd.
+ * Copyright (C) 2014 Huawei Ltd.
+ *
+ * Author: Wang Long <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+/* First 8KB reserved for secondary core boot */
+/memreserve/ 0x80000000 0x00002000;
+
+#include "hip01.dtsi"
+
+/ {
+ model = "Hisilicon HIP01 Development Board";
+ compatible = "hisilicon,hip01-ca9x2", "hisilicon,hip01";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <0>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <1>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x80000000>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/hip01.dtsi b/arch/arm/boot/dts/hip01.dtsi
new file mode 100644
index 0000000..33130f8
--- /dev/null
+++ b/arch/arm/boot/dts/hip01.dtsi
@@ -0,0 +1,110 @@
+/*
+ * Hisilicon Ltd. HiP01 SoC
+ *
+ * Copyright (c) 2014 Hisilicon Ltd.
+ * Copyright (c) 2014 Huawei Ltd.
+ *
+ * Author: Wang Long <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "skeleton.dtsi"
+
+/ {
+ interrupt-parent = <&gic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ gic: interrupt-controller@1e001000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x1a001000 0x1000>, <0x1a000100 0x1000>;
+ };
+
+ hisi_refclk144mhz: refclk144mkhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <144000000>;
+ clock-output-names = "hisi:refclk144khz";
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ ranges = <0 0x10000000 0x20000000>;
+
+ amba {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "arm,amba-bus";
+ ranges;
+
+ uart0: uart@10001000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x10001000 0x1000>;
+ clocks = <&hisi_refclk144mhz>;
+ clock-names = "apb_pclk";
+ reg-shift = <2>;
+ interrupts = <0 32 4>;
+ status = "disabled";
+ };
+
+ uart1: uart@10002000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x10002000 0x1000>;
+ clocks = <&hisi_refclk144mhz>;
+ clock-names = "apb_pclk";
+ reg-shift = <2>;
+ interrupts = <0 33 4>;
+ status = "disabled";
+ };
+
+ uart2: uart@10003000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x10003000 0x1000>;
+ clocks = <&hisi_refclk144mhz>;
+ clock-names = "apb_pclk";
+ reg-shift = <2>;
+ interrupts = <0 34 4>;
+ status = "disabled";
+ };
+
+ uart3: uart@10006000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x10006000 0x1000>;
+ clocks = <&hisi_refclk144mhz>;
+ clock-names = "apb_pclk";
+ reg-shift = <2>;
+ interrupts = <0 4 4>;
+ status = "disabled";
+ };
+ };
+
+ system-controller@10000000 {
+ compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl";
+ reg = <0x10000000 0x1000>;
+ reboot-offset = <0x4>;
+ };
+
+ global_timer@0a000200 {
+ compatible = "arm,cortex-a9-global-timer";
+ reg = <0x0a000200 0x100>;
+ interrupts = <1 11 0xf04>;
+ clocks = <&hisi_refclk144mhz>;
+ };
+
+ local_timer@0a000600 {
+ compatible = "arm,cortex-a9-twd-timer";
+ reg = <0x0a000600 0x100>;
+ interrupts = <1 13 0xf04>;
+ clocks = <&hisi_refclk144mhz>;
+ };
+ };
+};
--
1.8.3.4
enable smp for HiP01 board.
Signed-off-by: Wang Long <[email protected]>
---
arch/arm/boot/dts/hip01-ca9x2.dts | 1 +
arch/arm/mach-hisi/core.h | 3 +++
arch/arm/mach-hisi/hotplug.c | 31 ++++++++++++++++++++++++
arch/arm/mach-hisi/platsmp.c | 50 +++++++++++++++++++++++++++++++++++++++
4 files changed, 85 insertions(+)
diff --git a/arch/arm/boot/dts/hip01-ca9x2.dts b/arch/arm/boot/dts/hip01-ca9x2.dts
index 3f157ae..eca5e42 100644
--- a/arch/arm/boot/dts/hip01-ca9x2.dts
+++ b/arch/arm/boot/dts/hip01-ca9x2.dts
@@ -25,6 +25,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ enable-method = "hisilicon,hip01-smp";
cpu@0 {
device_type = "cpu";
diff --git a/arch/arm/mach-hisi/core.h b/arch/arm/mach-hisi/core.h
index 75520b0..92a682d 100644
--- a/arch/arm/mach-hisi/core.h
+++ b/arch/arm/mach-hisi/core.h
@@ -17,4 +17,7 @@ extern struct smp_operations hix5hd2_smp_ops;
extern void hix5hd2_set_cpu(int cpu, bool enable);
extern void hix5hd2_cpu_die(unsigned int cpu);
+extern struct smp_operations hip01_smp_ops;
+extern void hip01_set_cpu(int cpu, bool enable);
+extern void hip01_cpu_die(unsigned int cpu);
#endif
diff --git a/arch/arm/mach-hisi/hotplug.c b/arch/arm/mach-hisi/hotplug.c
index 84e6919..a129aae 100644
--- a/arch/arm/mach-hisi/hotplug.c
+++ b/arch/arm/mach-hisi/hotplug.c
@@ -65,6 +65,9 @@
#define PMC0_CPU1_PMC_ENABLE (1 << 7)
#define PMC0_CPU1_POWERDOWN (1 << 3)
+#define HIP01_PERI9 0x50
+#define PERI9_CPU1_RESET (1 << 1)
+
enum {
HI3620_CTRL,
ERROR_CTRL,
@@ -209,6 +212,34 @@ void hix5hd2_set_cpu(int cpu, bool enable)
}
}
+void hip01_set_cpu(int cpu, bool enable)
+{
+ unsigned int temp;
+ struct device_node *np;
+
+ if (!ctrl_base) {
+ np = of_find_compatible_node(NULL, NULL, "hisilicon,hip01-sysctrl");
+ if (np)
+ ctrl_base = of_iomap(np, 0);
+ else
+ BUG();
+ }
+
+ if (enable) {
+ /* reset on CPU1 */
+ temp = readl_relaxed(ctrl_base + HIP01_PERI9);
+ temp |= PERI9_CPU1_RESET;
+ writel_relaxed(temp, ctrl_base + HIP01_PERI9);
+
+ udelay(50);
+
+ /* unreset on CPU1 */
+ temp = readl_relaxed(ctrl_base + HIP01_PERI9);
+ temp &= ~PERI9_CPU1_RESET;
+ writel_relaxed(temp, ctrl_base + HIP01_PERI9);
+ }
+}
+
static inline void cpu_enter_lowpower(void)
{
unsigned int v;
diff --git a/arch/arm/mach-hisi/platsmp.c b/arch/arm/mach-hisi/platsmp.c
index 4a70f56..8880c8e 100644
--- a/arch/arm/mach-hisi/platsmp.c
+++ b/arch/arm/mach-hisi/platsmp.c
@@ -10,10 +10,12 @@
#include <linux/smp.h>
#include <linux/io.h>
#include <linux/of_address.h>
+#include <linux/delay.h>
#include <asm/cacheflush.h>
#include <asm/smp_plat.h>
#include <asm/smp_scu.h>
+#include <asm/mach/map.h>
#include "core.h"
@@ -132,5 +134,53 @@ struct smp_operations hix5hd2_smp_ops __initdata = {
#endif
};
+
+#define SC_SCTL_REMAP_CLR 0x00000100
+#define HIP01_BOOT_ADDRESS 0x80000000
+#define REG_SC_CTRL 0x000
+
+void hip01_set_boot_addr(phys_addr_t start_addr, phys_addr_t jump_addr)
+{
+ void __iomem *virt;
+
+ virt = phys_to_virt(start_addr);
+
+ writel_relaxed(0xe51ff004, virt);
+ writel_relaxed(jump_addr, virt + 4);
+}
+
+static int hip01_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+ phys_addr_t jumpaddr;
+ unsigned int remap_reg_value = 0;
+ struct device_node *node;
+
+
+ jumpaddr = virt_to_phys(hisi_secondary_startup);
+ hip01_set_boot_addr(HIP01_BOOT_ADDRESS, jumpaddr);
+
+ node = of_find_compatible_node(NULL, NULL, "hisilicon,hip01-sysctrl");
+ if (WARN_ON(!node))
+ return -1;
+ ctrl_base = of_iomap(node, 0);
+
+ /* set the secondary core boot from DDR */
+ remap_reg_value = readl_relaxed(ctrl_base + REG_SC_CTRL);
+ barrier();
+ remap_reg_value |= SC_SCTL_REMAP_CLR;
+ barrier();
+ writel_relaxed(remap_reg_value, ctrl_base + REG_SC_CTRL);
+
+ hip01_set_cpu(cpu, true);
+
+ return 0;
+}
+
+struct smp_operations hip01_smp_ops __initdata = {
+ .smp_prepare_cpus = hisi_common_smp_prepare_cpus,
+ .smp_boot_secondary = hip01_boot_secondary,
+};
+
CPU_METHOD_OF_DECLARE(hi3xxx_smp, "hisilicon,hi3620-smp", &hi3xxx_smp_ops);
CPU_METHOD_OF_DECLARE(hix5hd2_smp, "hisilicon,hix5hd2-smp", &hix5hd2_smp_ops);
+CPU_METHOD_OF_DECLARE(hip01_smp, "hisilicon,hip01-smp", &hip01_smp_ops);
--
1.8.3.4
Make hip01 share the hisi_defconfig.
And add it into multi_v7_defconfig too.
Signed-off-by: Wang Long <[email protected]>
---
arch/arm/configs/hisi_defconfig | 1 +
arch/arm/configs/multi_v7_defconfig | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/arm/configs/hisi_defconfig b/arch/arm/configs/hisi_defconfig
index 1125436..c34da58 100644
--- a/arch/arm/configs/hisi_defconfig
+++ b/arch/arm/configs/hisi_defconfig
@@ -8,6 +8,7 @@ CONFIG_ARCH_HI3xxx=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_CMDLINE_PARTITION=y
CONFIG_ARCH_HIX5HD2=y
+CONFIG_ARCH_HIP01=y
CONFIG_ARCH_HIP04=y
CONFIG_SMP=y
CONFIG_NR_CPUS=16
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 2328fe7..23523ed 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -32,6 +32,7 @@ CONFIG_ARCH_HIGHBANK=y
CONFIG_ARCH_HISI=y
CONFIG_ARCH_HI3xxx=y
CONFIG_ARCH_HIX5HD2=y
+CONFIG_ARCH_HIP01=y
CONFIG_ARCH_HIP04=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_ARCH_MESON=y
--
1.8.3.4
Add the support of Hisilicon HiP01 debug uart.
The uart of hip01 is 8250 compatible.
Signed-off-by: Wang Long <[email protected]>
---
arch/arm/Kconfig.debug | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 5ddd490..e0cf6ce 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -272,6 +272,14 @@ choice
Say Y here if you want the debug print routines to direct
their output to the UART on Highbank based devices.
+ config DEBUG_HIP01_UART
+ bool "Hisilicon Hip01 Debug UART"
+ depends on ARCH_HIP01
+ select DEBUG_UART_8250
+ help
+ Say Y here if you want kernel low-level debugging support
+ on HIP01 UART.
+
config DEBUG_HIP04_UART
bool "Hisilicon HiP04 Debug UART"
depends on ARCH_HIP04
@@ -1252,6 +1260,7 @@ config DEBUG_UART_PHYS
default 0x16000000 if ARCH_INTEGRATOR
default 0x18000300 if DEBUG_BCM_5301X
default 0x1c090000 if DEBUG_VEXPRESS_UART0_RS1
+ default 0x20001000 if DEBUG_HIP01_UART
default 0x20060000 if DEBUG_RK29_UART0
default 0x20064000 if DEBUG_RK29_UART1 || DEBUG_RK3X_UART2
default 0x20068000 if DEBUG_RK29_UART2 || DEBUG_RK3X_UART3
@@ -1394,6 +1403,7 @@ config DEBUG_UART_VIRT
default 0xfef36000 if DEBUG_HIGHBANK_UART
default 0xfefff700 if ARCH_IOP33X
default 0xff003000 if DEBUG_U300_UART
+ default 0xffd01000 if DEBUG_HIP01_UART
default DEBUG_UART_PHYS if !MMU
depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \
DEBUG_UART_8250 || DEBUG_UART_PL01X || DEBUG_MESON_UARTAO || \
--
1.8.3.4
On 2014/12/24 11:09, Wang Long wrote:
> Hi, Xu Wei
>
> This series patch enable Hisilicon HiP01 SoC. The HiP01 SoC series
> chip is designed for networking product, it integrates a rich peripheral
> interfaces to support network applications and supports both one
> core or dual cores and quad cores. The core is Cortex A9.
Hi Wang Long,
> This series patch rebased on Linux 3.19-rc1.
Thanks!
I will pick up these patch set and sent a pull request to [email protected].
Best Regards,
Wei
> Best Regards
>
> Wang Long (7):
> ARM: debug: add HiP01 debug uart
> ARM: hisi: enable HiP01 SoC
> ARM: dts: Add hip01-ca9x2 dts file
> ARM: config: enable ARCH_HIP01
> ARM: hisi: add a common smp_prepares_cpus function
> ARM: hisi: rename secondary_startup function
> ARM: hisi: enable smp for HiP01
>
> .../bindings/arm/hisilicon/hisilicon.txt | 25 +++++
> arch/arm/Kconfig.debug | 10 ++
> arch/arm/boot/dts/Makefile | 1 +
> arch/arm/boot/dts/hip01-ca9x2.dts | 51 ++++++++++
> arch/arm/boot/dts/hip01.dtsi | 110 +++++++++++++++++++++
> arch/arm/configs/hisi_defconfig | 1 +
> arch/arm/configs/multi_v7_defconfig | 1 +
> arch/arm/mach-hisi/Kconfig | 8 ++
> arch/arm/mach-hisi/core.h | 5 +-
> arch/arm/mach-hisi/headsmp.S | 2 +-
> arch/arm/mach-hisi/hisilicon.c | 10 ++
> arch/arm/mach-hisi/hotplug.c | 31 ++++++
> arch/arm/mach-hisi/platsmp.c | 56 ++++++++++-
> 13 files changed, 306 insertions(+), 5 deletions(-)
> create mode 100644 arch/arm/boot/dts/hip01-ca9x2.dts
> create mode 100644 arch/arm/boot/dts/hip01.dtsi
>