LinuxLists.cc - [Patch v3 0/6] GSBI CRCI Autoconfiguration Support

2015-02-09 22:13:47

Subject: [Patch v3 0/6] GSBI CRCI Autoconfiguration Support

This patch set adds support for automatic configuration of GSBI DMA CRCI values.

DMA operations require that the ADM CRCI mux values be properly configured in
the TCSR (Top Control and Status Register) block. During probing of a GSBI
device, the client mode must be declared and this can be used to lookup the
correct TCSR ADM CRCI MUX settings and then program them so that they are
correct before any clients are populated.

These patches add the TCSR as a syscon device and that allows the GSBI to
access and manipulate the ADM CRCI MUX registers to correctly configure the
values based on the GSBI port configuration.

Changes since v2:
- Use cell-index instead of alias to denote GSBI instance

Changes since v1:
- Fixed various review comments

Andy Gross (6):
soc: qcom: gsbi: Add support for ADM CRCI muxing
mfd: qcom,tcsr: Add device tree binding for TCSR
ARM: DT: apq8064: Add TCSR support
ARM: DT: ipq8064: Add TCSR support
ARM: DT: msm8660: Add TCSR support
ARM: DT: msm8960: Add TCSR support

.../devicetree/bindings/mfd/qcom,tcsr.txt | 22 +++
.../devicetree/bindings/soc/qcom/qcom,gsbi.txt | 14 +-
arch/arm/boot/dts/qcom-apq8064.dtsi | 14 ++
arch/arm/boot/dts/qcom-ipq8064.dtsi | 14 ++
arch/arm/boot/dts/qcom-msm8660.dtsi | 8 ++
arch/arm/boot/dts/qcom-msm8960.dtsi | 8 ++
drivers/soc/qcom/Kconfig | 1 +
drivers/soc/qcom/qcom_gsbi.c | 152 ++++++++++++++++++++
8 files changed, 232 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/mfd/qcom,tcsr.txt

--
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2015-02-09 22:15:17

by Andy Gross

[permalink] [raw]

Subject: [Patch v3 1/6] soc: qcom: gsbi: Add support for ADM CRCI muxing

This patch adds automatic configuration for the ADM CRCI muxing required to
support DMA operations for GSBI clients. The GSBI mode and instance determine
the correct TCSR ADM CRCI MUX value that must be programmed so that the DMA
works properly.

Signed-off-by: Andy Gross <[email protected]>
---
.../devicetree/bindings/soc/qcom/qcom,gsbi.txt | 14 +-
drivers/soc/qcom/Kconfig | 1 +
drivers/soc/qcom/qcom_gsbi.c | 152 ++++++++++++++++++++
3 files changed, 166 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt
index 4ce24d4..186e5f4 100644
--- a/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt
@@ -6,7 +6,8 @@ configuration settings. The mode setting will govern the input/output mode of
the 4 GSBI IOs.

Required properties:
-- compatible: must contain "qcom,gsbi-v1.0.0" for APQ8064/IPQ8064
+- compatible: Should contain "qcom,gsbi-v1.0.0"
+- cell-index: Should contain the GSBI index
- reg: Address range for GSBI registers
- clocks: required clock
- clock-names: must contain "iface" entry
@@ -16,6 +17,8 @@ Required properties:
Optional properties:
- qcom,crci : indicates CRCI MUX value for QUP CRCI ports. Please reference
dt-bindings/soc/qcom,gsbi.h for valid CRCI mux values.
+- syscon-tcsr: indicates phandle of TCSR syscon node. Required if child uses
+ dma.

Required properties if child node exists:
- #address-cells: Must be 1
@@ -39,6 +42,7 @@ Example for APQ8064:

gsbi4@16300000 {
compatible = "qcom,gsbi-v1.0.0";
+ cell-index = <4>;
reg = <0x16300000 0x100>;
clocks = <&gcc GSBI4_H_CLK>;
clock-names = "iface";
@@ -48,6 +52,8 @@ Example for APQ8064:
qcom,mode = <GSBI_PROT_I2C_UART>;
qcom,crci = <GSBI_CRCI_QUP>;

+ syscon-tcsr = <&tcsr>;
+
/* child nodes go under here */

i2c_qup4: i2c@16380000 {
@@ -76,3 +82,9 @@ Example for APQ8064:
};
};

+ tcsr: syscon@1a400000 {
+ compatible = "qcom,apq8064-tcsr", "syscon";
+ reg = <0x1a400000 0x100>;
+ };
+
+
diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig
index 7bd2c94..460b2db 100644
--- a/drivers/soc/qcom/Kconfig
+++ b/drivers/soc/qcom/Kconfig
@@ -4,6 +4,7 @@
config QCOM_GSBI
tristate "QCOM General Serial Bus Interface"
depends on ARCH_QCOM
+ select MFD_SYSCON
help
Say y here to enable GSBI support. The GSBI provides control
functions for connecting the underlying serial UART, SPI, and I2C
diff --git a/drivers/soc/qcom/qcom_gsbi.c b/drivers/soc/qcom/qcom_gsbi.c
index 729425d..09c669e 100644
--- a/drivers/soc/qcom/qcom_gsbi.c
+++ b/drivers/soc/qcom/qcom_gsbi.c
@@ -18,22 +18,129 @@
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
+#include <dt-bindings/soc/qcom,gsbi.h>

#define GSBI_CTRL_REG 0x0000
#define GSBI_PROTOCOL_SHIFT 4
+#define MAX_GSBI 12
+
+#define TCSR_ADM_CRCI_BASE 0x70
+
+struct crci_config {
+ u32 num_rows;
+ const u32 (*array)[MAX_GSBI];
+};
+
+static const u32 crci_ipq8064[][MAX_GSBI] = {
+ {
+ 0x000003, 0x00000c, 0x000030, 0x0000c0,
+ 0x000300, 0x000c00, 0x003000, 0x00c000,
+ 0x030000, 0x0c0000, 0x300000, 0xc00000
+ },
+ {
+ 0x000003, 0x00000c, 0x000030, 0x0000c0,
+ 0x000300, 0x000c00, 0x003000, 0x00c000,
+ 0x030000, 0x0c0000, 0x300000, 0xc00000
+ },
+};
+
+static const struct crci_config config_ipq8064 = {
+ .num_rows = ARRAY_SIZE(crci_ipq8064),
+ .array = crci_ipq8064,
+};
+
+static const unsigned int crci_apq8064[][MAX_GSBI] = {
+ {
+ 0x001800, 0x006000, 0x000030, 0x0000c0,
+ 0x000300, 0x000400, 0x000000, 0x000000,
+ 0x000000, 0x000000, 0x000000, 0x000000
+ },
+ {
+ 0x000000, 0x000000, 0x000000, 0x000000,
+ 0x000000, 0x000020, 0x0000c0, 0x000000,
+ 0x000000, 0x000000, 0x000000, 0x000000
+ },
+};
+
+static const struct crci_config config_apq8064 = {
+ .num_rows = ARRAY_SIZE(crci_apq8064),
+ .array = crci_apq8064,
+};
+
+static const unsigned int crci_msm8960[][MAX_GSBI] = {
+ {
+ 0x000003, 0x00000c, 0x000030, 0x0000c0,
+ 0x000300, 0x000400, 0x000000, 0x000000,
+ 0x000000, 0x000000, 0x000000, 0x000000
+ },
+ {
+ 0x000000, 0x000000, 0x000000, 0x000000,
+ 0x000000, 0x000020, 0x0000c0, 0x000300,
+ 0x001800, 0x006000, 0x000000, 0x000000
+ },
+};
+
+static const struct crci_config config_msm8960 = {
+ .num_rows = ARRAY_SIZE(crci_msm8960),
+ .array = crci_msm8960,
+};
+
+static const unsigned int crci_msm8660[][MAX_GSBI] = {
+ { /* ADM 0 - B */
+ 0x000003, 0x00000c, 0x000030, 0x0000c0,
+ 0x000300, 0x000c00, 0x003000, 0x00c000,
+ 0x030000, 0x0c0000, 0x300000, 0xc00000
+ },
+ { /* ADM 0 - B */
+ 0x000003, 0x00000c, 0x000030, 0x0000c0,
+ 0x000300, 0x000c00, 0x003000, 0x00c000,
+ 0x030000, 0x0c0000, 0x300000, 0xc00000
+ },
+ { /* ADM 1 - A */
+ 0x000003, 0x00000c, 0x000030, 0x0000c0,
+ 0x000300, 0x000c00, 0x003000, 0x00c000,
+ 0x030000, 0x0c0000, 0x300000, 0xc00000
+ },
+ { /* ADM 1 - B */
+ 0x000003, 0x00000c, 0x000030, 0x0000c0,
+ 0x000300, 0x000c00, 0x003000, 0x00c000,
+ 0x030000, 0x0c0000, 0x300000, 0xc00000
+ },
+};
+
+static const struct crci_config config_msm8660 = {
+ .num_rows = ARRAY_SIZE(crci_msm8660),
+ .array = crci_msm8660,
+};

struct gsbi_info {
struct clk *hclk;
u32 mode;
u32 crci;
+ struct regmap *tcsr;
+};
+
+static const struct of_device_id tcsr_dt_match[] = {
+ { .compatible = "qcom,tcsr-ipq8064", .data = &config_ipq8064},
+ { .compatible = "qcom,tcsr-apq8064", .data = &config_apq8064},
+ { .compatible = "qcom,tcsr-msm8960", .data = &config_msm8960},
+ { .compatible = "qcom,tcsr-msm8660", .data = &config_msm8660},
+ { },
};

static int gsbi_probe(struct platform_device *pdev)
{
struct device_node *node = pdev->dev.of_node;
+ struct device_node *tcsr_node;
+ const struct of_device_id *match;
struct resource *res;
void __iomem *base;
struct gsbi_info *gsbi;
+ int i;
+ u32 mask, gsbi_num;
+ const struct crci_config *config = NULL;

gsbi = devm_kzalloc(&pdev->dev, sizeof(*gsbi), GFP_KERNEL);

@@ -45,6 +152,32 @@ static int gsbi_probe(struct platform_device *pdev)
if (IS_ERR(base))
return PTR_ERR(base);

+ /* get the tcsr node and setup the config and regmap */
+ gsbi->tcsr = syscon_regmap_lookup_by_phandle(node, "syscon-tcsr");
+
+ if (!IS_ERR(gsbi->tcsr)) {
+ tcsr_node = of_parse_phandle(node, "syscon-tcsr", 0);
+ if (tcsr_node) {
+ match = of_match_node(tcsr_dt_match, tcsr_node);
+ if (match)
+ config = match->data;
+ else
+ dev_warn(&pdev->dev, "no matching TCSR\n");
+
+ of_node_put(tcsr_node);
+ }
+ }
+
+ if (of_property_read_u32(node, "cell-index", &gsbi_num)) {
+ dev_err(&pdev->dev, "missing cell-index\n");
+ return -EINVAL;
+ }
+
+ if (gsbi_num < 1 || gsbi_num > MAX_GSBI) {
+ dev_err(&pdev->dev, "invalid cell-index\n");
+ return -EINVAL;
+ }
+
if (of_property_read_u32(node, "qcom,mode", &gsbi->mode)) {
dev_err(&pdev->dev, "missing mode configuration\n");
return -EINVAL;
@@ -64,6 +197,25 @@ static int gsbi_probe(struct platform_device *pdev)
writel_relaxed((gsbi->mode << GSBI_PROTOCOL_SHIFT) | gsbi->crci,
base + GSBI_CTRL_REG);

+ /*
+ * modify tcsr to reflect mode and ADM CRCI mux
+ * Each gsbi contains a pair of bits, one for RX and one for TX
+ * SPI mode requires both bits cleared, otherwise they are set
+ */
+ if (config) {
+ for (i = 0; i < config->num_rows; i++) {
+ mask = config->array[i][gsbi_num - 1];
+
+ if (gsbi->mode == GSBI_PROT_SPI)
+ regmap_update_bits(gsbi->tcsr,
+ TCSR_ADM_CRCI_BASE + 4 * i, mask, 0);
+ else
+ regmap_update_bits(gsbi->tcsr,
+ TCSR_ADM_CRCI_BASE + 4 * i, mask, mask);
+
+ }
+ }
+
/* make sure the gsbi control write is not reordered */
wmb();

--
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hosted by The Linux Foundation

2015-02-09 22:13:44

by Andy Gross

[permalink] [raw]

Subject: [Patch v3 2/6] mfd: qcom,tcsr: Add device tree binding for TCSR

This patch adds the device tree binding for the Qualcomm Top Control and
Status Register device. The TCSR is comprised of a set of registers that
provide various control and status functions for attached peripherals.

Signed-off-by: Andy Gross <[email protected]>
---
.../devicetree/bindings/mfd/qcom,tcsr.txt | 22 ++++++++++++++++++++
1 file changed, 22 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mfd/qcom,tcsr.txt

diff --git a/Documentation/devicetree/bindings/mfd/qcom,tcsr.txt b/Documentation/devicetree/bindings/mfd/qcom,tcsr.txt
new file mode 100644
index 0000000..e90519d
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/qcom,tcsr.txt
@@ -0,0 +1,22 @@
+QCOM Top Control and Status Register
+
+Qualcomm devices have a set of registers that provide various control and status
+functions for their peripherals. This node is intended to allow access to these
+registers via syscon.
+
+Required properties:
+- compatible: Should contain:
+ "qcom,tcsr-ipq8064", "syscon" for IPQ8064
+ "qcom,tcsr-apq8064", "syscon" for APQ8064
+ "qcom,tcsr-msm8660", "syscon" for MSM8660
+ "qcom,tcsr-msm8960", "syscon" for MSM8960
+ "qcom,tcsr-msm8974", "syscon" for MSM8974
+ "qcom,tcsr-apq8084", "syscon" for APQ8084
+ "qcom,tcsr-msm8916", "syscon" for MSM8916
+- reg: Address range for TCSR registers
+
+Example:
+ tcsr: syscon@1a400000 {
+ compatible = "qcom,tcsr-msm8960", "syscon";
+ reg = <0x1a400000 0x100>;
+ };
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

2015-02-09 22:13:40

by Andy Gross

[permalink] [raw]

Subject: [Patch v3 3/6] ARM: DT: apq8064: Add TCSR support

This patch adds TCSR support for use by the GSBI to automatically configure ADM
CRCI values based on the GSBI port configuration.

Signed-off-by: Andy Gross <[email protected]>
---
arch/arm/boot/dts/qcom-apq8064.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index b3154c0..f607900 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -166,6 +166,7 @@
gsbi1: gsbi@12440000 {
status = "disabled";
compatible = "qcom,gsbi-v1.0.0";
+ cell-index = <1>;
reg = <0x12440000 0x100>;
clocks = <&gcc GSBI1_H_CLK>;
clock-names = "iface";
@@ -173,6 +174,8 @@
#size-cells = <1>;
ranges;

+ syscon-tcsr = <&tcsr>;
+
i2c1: i2c@12460000 {
compatible = "qcom,i2c-qup-v1.1.1";
reg = <0x12460000 0x1000>;
@@ -187,6 +190,7 @@
gsbi2: gsbi@12480000 {
status = "disabled";
compatible = "qcom,gsbi-v1.0.0";
+ cell-index = <2>;
reg = <0x12480000 0x100>;
clocks = <&gcc GSBI2_H_CLK>;
clock-names = "iface";
@@ -194,6 +198,8 @@
#size-cells = <1>;
ranges;

+ syscon-tcsr = <&tcsr>;
+
i2c2: i2c@124a0000 {
compatible = "qcom,i2c-qup-v1.1.1";
reg = <0x124a0000 0x1000>;
@@ -208,6 +214,7 @@
gsbi7: gsbi@16600000 {
status = "disabled";
compatible = "qcom,gsbi-v1.0.0";
+ cell-index = <7>;
reg = <0x16600000 0x100>;
clocks = <&gcc GSBI7_H_CLK>;
clock-names = "iface";
@@ -215,6 +222,8 @@
#size-cells = <1>;
ranges;

+ syscon-tcsr = <&tcsr>;
+
serial@16640000 {
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
reg = <0x16640000 0x1000>,
@@ -349,5 +358,10 @@
pinctrl-0 = <&sdc4_gpios>;
};
};
+
+ tcsr: syscon@1a400000 {
+ compatible = "qcom,tcsr-apq8064", "syscon";
+ reg = <0x1a400000 0x100>;
+ };
};
};
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

2015-02-09 22:13:41

by Andy Gross

[permalink] [raw]

Subject: [Patch v3 4/6] ARM: DT: ipq8064: Add TCSR support

This patch adds TCSR support for use by the GSBI to automatically configure ADM
CRCI values based on the GSBI port configuration.

Signed-off-by: Andy Gross <[email protected]>
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 63b2146..d3643fe 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -120,6 +120,7 @@

gsbi2: gsbi@12480000 {
compatible = "qcom,gsbi-v1.0.0";
+ cell-index = <2>;
reg = <0x12480000 0x100>;
clocks = <&gcc GSBI2_H_CLK>;
clock-names = "iface";
@@ -128,6 +129,8 @@
ranges;
status = "disabled";

+ syscon-tcsr = <&tcsr>;
+
serial@12490000 {
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
reg = <0x12490000 0x1000>,
@@ -155,6 +158,7 @@

gsbi4: gsbi@16300000 {
compatible = "qcom,gsbi-v1.0.0";
+ cell-index = <4>;
reg = <0x16300000 0x100>;
clocks = <&gcc GSBI4_H_CLK>;
clock-names = "iface";
@@ -163,6 +167,8 @@
ranges;
status = "disabled";

+ syscon-tcsr = <&tcsr>;
+
serial@16340000 {
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
reg = <0x16340000 0x1000>,
@@ -189,6 +195,7 @@

gsbi5: gsbi@1a200000 {
compatible = "qcom,gsbi-v1.0.0";
+ cell-index = <5>;
reg = <0x1a200000 0x100>;
clocks = <&gcc GSBI5_H_CLK>;
clock-names = "iface";
@@ -197,6 +204,8 @@
ranges;
status = "disabled";

+ syscon-tcsr = <&tcsr>;
+
serial@1a240000 {
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
reg = <0x1a240000 0x1000>,
@@ -279,5 +288,10 @@
#clock-cells = <1>;
#reset-cells = <1>;
};
+
+ tcsr: syscon@1a400000 {
+ compatible = "qcom,tcsr-ipq8064", "syscon";
+ reg = <0x1a400000 0x100>;
+ };
};
};
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

2015-02-09 22:13:45

by Andy Gross

[permalink] [raw]

Subject: [Patch v3 5/6] ARM: DT: msm8660: Add TCSR support

2015-02-09 22:13:43

by Andy Gross

[permalink] [raw]

Subject: [Patch v3 6/6] ARM: DT: msm8960: Add TCSR support

2015-02-10 17:57:35

by Kumar Gala

[permalink] [raw]

Subject: Re: [Patch v3 0/6] GSBI CRCI Autoconfiguration Support

On Feb 9, 2015, at 4:01 PM, Andy Gross <[email protected]> wrote:

> This patch set adds support for automatic configuration of GSBI DMA CRCI values.
>
> DMA operations require that the ADM CRCI mux values be properly configured in
> the TCSR (Top Control and Status Register) block. During probing of a GSBI
> device, the client mode must be declared and this can be used to lookup the
> correct TCSR ADM CRCI MUX settings and then program them so that they are
> correct before any clients are populated.
>
> These patches add the TCSR as a syscon device and that allows the GSBI to
> access and manipulate the ADM CRCI MUX registers to correctly configure the
> values based on the GSBI port configuration.
>
> Changes since v2:
> - Use cell-index instead of alias to denote GSBI instance
>
> Changes since v1:
> - Fixed various review comments
>
> Andy Gross (6):
> soc: qcom: gsbi: Add support for ADM CRCI muxing
> mfd: qcom,tcsr: Add device tree binding for TCSR
> ARM: DT: apq8064: Add TCSR support
> ARM: DT: ipq8064: Add TCSR support
> ARM: DT: msm8660: Add TCSR support
> ARM: DT: msm8960: Add TCSR support
>
> .../devicetree/bindings/mfd/qcom,tcsr.txt | 22 +++
> .../devicetree/bindings/soc/qcom/qcom,gsbi.txt | 14 +-
> arch/arm/boot/dts/qcom-apq8064.dtsi | 14 ++
> arch/arm/boot/dts/qcom-ipq8064.dtsi | 14 ++
> arch/arm/boot/dts/qcom-msm8660.dtsi | 8 ++
> arch/arm/boot/dts/qcom-msm8960.dtsi | 8 ++
> drivers/soc/qcom/Kconfig | 1 +
> drivers/soc/qcom/qcom_gsbi.c | 152 ++++++++++++++++++++
> 8 files changed, 232 insertions(+), 1 deletion(-)
> create mode 100644 Documentation/devicetree/bindings/mfd/qcom,tcsr.txt

Series looks good, do we need a qcom_defconfig update to enable anything new for this?

- k

--
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

2015-02-10 18:59:40

by Andy Gross

[permalink] [raw]

Subject: Re: [Patch v3 0/6] GSBI CRCI Autoconfiguration Support

On Tue, Feb 10, 2015 at 11:57:27AM -0600, Kumar Gala wrote:
>
> On Feb 9, 2015, at 4:01 PM, Andy Gross <[email protected]> wrote:
>
> > This patch set adds support for automatic configuration of GSBI DMA CRCI values.
> >
> > DMA operations require that the ADM CRCI mux values be properly configured in
> > the TCSR (Top Control and Status Register) block. During probing of a GSBI
> > device, the client mode must be declared and this can be used to lookup the
> > correct TCSR ADM CRCI MUX settings and then program them so that they are
> > correct before any clients are populated.
> >
> > These patches add the TCSR as a syscon device and that allows the GSBI to
> > access and manipulate the ADM CRCI MUX registers to correctly configure the
> > values based on the GSBI port configuration.
> >
> > Changes since v2:
> > - Use cell-index instead of alias to denote GSBI instance
> >
> > Changes since v1:
> > - Fixed various review comments
> >
> > Andy Gross (6):
> > soc: qcom: gsbi: Add support for ADM CRCI muxing
> > mfd: qcom,tcsr: Add device tree binding for TCSR
> > ARM: DT: apq8064: Add TCSR support
> > ARM: DT: ipq8064: Add TCSR support
> > ARM: DT: msm8660: Add TCSR support
> > ARM: DT: msm8960: Add TCSR support
> >
> > .../devicetree/bindings/mfd/qcom,tcsr.txt | 22 +++
> > .../devicetree/bindings/soc/qcom/qcom,gsbi.txt | 14 +-
> > arch/arm/boot/dts/qcom-apq8064.dtsi | 14 ++
> > arch/arm/boot/dts/qcom-ipq8064.dtsi | 14 ++
> > arch/arm/boot/dts/qcom-msm8660.dtsi | 8 ++
> > arch/arm/boot/dts/qcom-msm8960.dtsi | 8 ++
> > drivers/soc/qcom/Kconfig | 1 +
> > drivers/soc/qcom/qcom_gsbi.c | 152 ++++++++++++++++++++
> > 8 files changed, 232 insertions(+), 1 deletion(-)
> > create mode 100644 Documentation/devicetree/bindings/mfd/qcom,tcsr.txt
>
> Series looks good, do we need a qcom_defconfig update to enable anything new for this?
>
> - k

I'll send a followup to enable qcom_defconfig.

--
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

2015-02-10 20:25:48

by Andy Gross

[permalink] [raw]

Subject: Re: [Patch v3 0/6] GSBI CRCI Autoconfiguration Support

<snip>

> >
> > Series looks good, do we need a qcom_defconfig update to enable anything new for this?
> >
> > - k
>
> I'll send a followup to enable qcom_defconfig.
>

Correction:
Since I use a 'selects MFD_SYSCON' in the Kconfig we shouldn't need anything.

--
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project