Split out the 32-bit SCM implementation into its own file to prep for
supporting a 64-bit/ARM64 implementation as well. We create a simple shim
to ensure both versions conform to the same interface.
Signed-off-by: Kumar Gala <[email protected]>
---
v5:
Split out error defines in common qcom_scm.h
drivers/firmware/Makefile | 3 +-
drivers/firmware/{qcom_scm.c => qcom_scm-32.c} | 22 +-
drivers/firmware/qcom_scm.c | 442 +------------------------
drivers/firmware/qcom_scm.h | 38 +++
4 files changed, 51 insertions(+), 454 deletions(-)
copy drivers/firmware/{qcom_scm.c => qcom_scm-32.c} (95%)
create mode 100644 drivers/firmware/qcom_scm.h
diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile
index 3fdd391..3001f1a 100644
--- a/drivers/firmware/Makefile
+++ b/drivers/firmware/Makefile
@@ -12,7 +12,8 @@ obj-$(CONFIG_ISCSI_IBFT_FIND) += iscsi_ibft_find.o
obj-$(CONFIG_ISCSI_IBFT) += iscsi_ibft.o
obj-$(CONFIG_FIRMWARE_MEMMAP) += memmap.o
obj-$(CONFIG_QCOM_SCM) += qcom_scm.o
-CFLAGS_qcom_scm.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
+obj-$(CONFIG_QCOM_SCM) += qcom_scm-32.o
+CFLAGS_qcom_scm-32.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
obj-$(CONFIG_GOOGLE_FIRMWARE) += google/
obj-$(CONFIG_EFI) += efi/
diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm-32.c
similarity index 95%
copy from drivers/firmware/qcom_scm.c
copy to drivers/firmware/qcom_scm-32.c
index 994b50f..b08b822 100644
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm-32.c
@@ -27,13 +27,7 @@
#include <asm/outercache.h>
#include <asm/cacheflush.h>
-
-#define QCOM_SCM_ENOMEM -5
-#define QCOM_SCM_EOPNOTSUPP -4
-#define QCOM_SCM_EINVAL_ADDR -3
-#define QCOM_SCM_EINVAL_ARG -2
-#define QCOM_SCM_ERROR -1
-#define QCOM_SCM_INTERRUPTED 1
+#include "qcom_scm.h"
#define QCOM_SCM_FLAG_COLDBOOT_CPU0 0x00
#define QCOM_SCM_FLAG_COLDBOOT_CPU1 0x01
@@ -386,8 +380,6 @@ u32 qcom_scm_get_version(void)
}
EXPORT_SYMBOL(qcom_scm_get_version);
-#define QCOM_SCM_SVC_BOOT 0x1
-#define QCOM_SCM_BOOT_ADDR 0x1
/*
* Set the cold/warm boot address for one of the CPU cores.
*/
@@ -412,7 +404,7 @@ static int qcom_scm_set_boot_addr(u32 addr, int flags)
* Set the cold boot address of the cpus. Any cpu outside the supported
* range would be removed from the cpu present mask.
*/
-int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
+int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
{
int flags = 0;
int cpu;
@@ -435,7 +427,6 @@ int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
return qcom_scm_set_boot_addr(virt_to_phys(entry), flags);
}
-EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr);
/**
* qcom_scm_set_warm_boot_addr() - Set the warm boot address for cpus
@@ -445,7 +436,7 @@ EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr);
* Set the Linux entry point for the SCM to transfer control to when coming
* out of a power down. CPU power down may be executed on cpuidle or hotplug.
*/
-int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
+int __qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
{
int ret;
int flags = 0;
@@ -473,10 +464,6 @@ int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
return ret;
}
-EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr);
-
-#define QCOM_SCM_CMD_TERMINATE_PC 0x2
-#define QCOM_SCM_FLUSH_FLAG_MASK 0x3
/**
* qcom_scm_cpu_power_down() - Power down the cpu
@@ -486,9 +473,8 @@ EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr);
* the control would return from this function, otherwise, the cpu jumps to the
* warm boot entry point set for this cpu upon reset.
*/
-void qcom_scm_cpu_power_down(u32 flags)
+void __qcom_scm_cpu_power_down(u32 flags)
{
qcom_scm_call_atomic1(QCOM_SCM_SVC_BOOT, QCOM_SCM_CMD_TERMINATE_PC,
flags & QCOM_SCM_FLUSH_FLAG_MASK);
}
-EXPORT_SYMBOL(qcom_scm_cpu_power_down);
diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c
index 994b50f..9989241 100644
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm.c
@@ -16,393 +16,12 @@
* 02110-1301, USA.
*/
-#include <linux/slab.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/mutex.h>
-#include <linux/errno.h>
-#include <linux/err.h>
+#include <linux/cpumask.h>
+#include <linux/export.h>
+#include <linux/types.h>
#include <linux/qcom_scm.h>
-#include <asm/outercache.h>
-#include <asm/cacheflush.h>
-
-
-#define QCOM_SCM_ENOMEM -5
-#define QCOM_SCM_EOPNOTSUPP -4
-#define QCOM_SCM_EINVAL_ADDR -3
-#define QCOM_SCM_EINVAL_ARG -2
-#define QCOM_SCM_ERROR -1
-#define QCOM_SCM_INTERRUPTED 1
-
-#define QCOM_SCM_FLAG_COLDBOOT_CPU0 0x00
-#define QCOM_SCM_FLAG_COLDBOOT_CPU1 0x01
-#define QCOM_SCM_FLAG_COLDBOOT_CPU2 0x08
-#define QCOM_SCM_FLAG_COLDBOOT_CPU3 0x20
-
-#define QCOM_SCM_FLAG_WARMBOOT_CPU0 0x04
-#define QCOM_SCM_FLAG_WARMBOOT_CPU1 0x02
-#define QCOM_SCM_FLAG_WARMBOOT_CPU2 0x10
-#define QCOM_SCM_FLAG_WARMBOOT_CPU3 0x40
-
-struct qcom_scm_entry {
- int flag;
- void *entry;
-};
-
-static struct qcom_scm_entry qcom_scm_wb[] = {
- { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU0 },
- { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU1 },
- { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU2 },
- { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU3 },
-};
-
-static DEFINE_MUTEX(qcom_scm_lock);
-
-/**
- * struct qcom_scm_command - one SCM command buffer
- * @len: total available memory for command and response
- * @buf_offset: start of command buffer
- * @resp_hdr_offset: start of response buffer
- * @id: command to be executed
- * @buf: buffer returned from qcom_scm_get_command_buffer()
- *
- * An SCM command is laid out in memory as follows:
- *
- * ------------------- <--- struct qcom_scm_command
- * | command header |
- * ------------------- <--- qcom_scm_get_command_buffer()
- * | command buffer |
- * ------------------- <--- struct qcom_scm_response and
- * | response header | qcom_scm_command_to_response()
- * ------------------- <--- qcom_scm_get_response_buffer()
- * | response buffer |
- * -------------------
- *
- * There can be arbitrary padding between the headers and buffers so
- * you should always use the appropriate qcom_scm_get_*_buffer() routines
- * to access the buffers in a safe manner.
- */
-struct qcom_scm_command {
- __le32 len;
- __le32 buf_offset;
- __le32 resp_hdr_offset;
- __le32 id;
- __le32 buf[0];
-};
-
-/**
- * struct qcom_scm_response - one SCM response buffer
- * @len: total available memory for response
- * @buf_offset: start of response data relative to start of qcom_scm_response
- * @is_complete: indicates if the command has finished processing
- */
-struct qcom_scm_response {
- __le32 len;
- __le32 buf_offset;
- __le32 is_complete;
-};
-
-/**
- * alloc_qcom_scm_command() - Allocate an SCM command
- * @cmd_size: size of the command buffer
- * @resp_size: size of the response buffer
- *
- * Allocate an SCM command, including enough room for the command
- * and response headers as well as the command and response buffers.
- *
- * Returns a valid &qcom_scm_command on success or %NULL if the allocation fails.
- */
-static struct qcom_scm_command *alloc_qcom_scm_command(size_t cmd_size, size_t resp_size)
-{
- struct qcom_scm_command *cmd;
- size_t len = sizeof(*cmd) + sizeof(struct qcom_scm_response) + cmd_size +
- resp_size;
- u32 offset;
-
- cmd = kzalloc(PAGE_ALIGN(len), GFP_KERNEL);
- if (cmd) {
- cmd->len = cpu_to_le32(len);
- offset = offsetof(struct qcom_scm_command, buf);
- cmd->buf_offset = cpu_to_le32(offset);
- cmd->resp_hdr_offset = cpu_to_le32(offset + cmd_size);
- }
- return cmd;
-}
-
-/**
- * free_qcom_scm_command() - Free an SCM command
- * @cmd: command to free
- *
- * Free an SCM command.
- */
-static inline void free_qcom_scm_command(struct qcom_scm_command *cmd)
-{
- kfree(cmd);
-}
-
-/**
- * qcom_scm_command_to_response() - Get a pointer to a qcom_scm_response
- * @cmd: command
- *
- * Returns a pointer to a response for a command.
- */
-static inline struct qcom_scm_response *qcom_scm_command_to_response(
- const struct qcom_scm_command *cmd)
-{
- return (void *)cmd + le32_to_cpu(cmd->resp_hdr_offset);
-}
-
-/**
- * qcom_scm_get_command_buffer() - Get a pointer to a command buffer
- * @cmd: command
- *
- * Returns a pointer to the command buffer of a command.
- */
-static inline void *qcom_scm_get_command_buffer(const struct qcom_scm_command *cmd)
-{
- return (void *)cmd->buf;
-}
-
-/**
- * qcom_scm_get_response_buffer() - Get a pointer to a response buffer
- * @rsp: response
- *
- * Returns a pointer to a response buffer of a response.
- */
-static inline void *qcom_scm_get_response_buffer(const struct qcom_scm_response *rsp)
-{
- return (void *)rsp + le32_to_cpu(rsp->buf_offset);
-}
-
-static int qcom_scm_remap_error(int err)
-{
- pr_err("qcom_scm_call failed with error code %d\n", err);
- switch (err) {
- case QCOM_SCM_ERROR:
- return -EIO;
- case QCOM_SCM_EINVAL_ADDR:
- case QCOM_SCM_EINVAL_ARG:
- return -EINVAL;
- case QCOM_SCM_EOPNOTSUPP:
- return -EOPNOTSUPP;
- case QCOM_SCM_ENOMEM:
- return -ENOMEM;
- }
- return -EINVAL;
-}
-
-static u32 smc(u32 cmd_addr)
-{
- int context_id;
- register u32 r0 asm("r0") = 1;
- register u32 r1 asm("r1") = (u32)&context_id;
- register u32 r2 asm("r2") = cmd_addr;
- do {
- asm volatile(
- __asmeq("%0", "r0")
- __asmeq("%1", "r0")
- __asmeq("%2", "r1")
- __asmeq("%3", "r2")
-#ifdef REQUIRES_SEC
- ".arch_extension sec\n"
-#endif
- "smc #0 @ switch to secure world\n"
- : "=r" (r0)
- : "r" (r0), "r" (r1), "r" (r2)
- : "r3");
- } while (r0 == QCOM_SCM_INTERRUPTED);
-
- return r0;
-}
-
-static int __qcom_scm_call(const struct qcom_scm_command *cmd)
-{
- int ret;
- u32 cmd_addr = virt_to_phys(cmd);
-
- /*
- * Flush the command buffer so that the secure world sees
- * the correct data.
- */
- __cpuc_flush_dcache_area((void *)cmd, cmd->len);
- outer_flush_range(cmd_addr, cmd_addr + cmd->len);
-
- ret = smc(cmd_addr);
- if (ret < 0)
- ret = qcom_scm_remap_error(ret);
-
- return ret;
-}
-
-static void qcom_scm_inv_range(unsigned long start, unsigned long end)
-{
- u32 cacheline_size, ctr;
-
- asm volatile("mrc p15, 0, %0, c0, c0, 1" : "=r" (ctr));
- cacheline_size = 4 << ((ctr >> 16) & 0xf);
-
- start = round_down(start, cacheline_size);
- end = round_up(end, cacheline_size);
- outer_inv_range(start, end);
- while (start < end) {
- asm ("mcr p15, 0, %0, c7, c6, 1" : : "r" (start)
- : "memory");
- start += cacheline_size;
- }
- dsb();
- isb();
-}
-
-/**
- * qcom_scm_call() - Send an SCM command
- * @svc_id: service identifier
- * @cmd_id: command identifier
- * @cmd_buf: command buffer
- * @cmd_len: length of the command buffer
- * @resp_buf: response buffer
- * @resp_len: length of the response buffer
- *
- * Sends a command to the SCM and waits for the command to finish processing.
- *
- * A note on cache maintenance:
- * Note that any buffers that are expected to be accessed by the secure world
- * must be flushed before invoking qcom_scm_call and invalidated in the cache
- * immediately after qcom_scm_call returns. Cache maintenance on the command
- * and response buffers is taken care of by qcom_scm_call; however, callers are
- * responsible for any other cached buffers passed over to the secure world.
- */
-static int qcom_scm_call(u32 svc_id, u32 cmd_id, const void *cmd_buf,
- size_t cmd_len, void *resp_buf, size_t resp_len)
-{
- int ret;
- struct qcom_scm_command *cmd;
- struct qcom_scm_response *rsp;
- unsigned long start, end;
-
- cmd = alloc_qcom_scm_command(cmd_len, resp_len);
- if (!cmd)
- return -ENOMEM;
-
- cmd->id = cpu_to_le32((svc_id << 10) | cmd_id);
- if (cmd_buf)
- memcpy(qcom_scm_get_command_buffer(cmd), cmd_buf, cmd_len);
-
- mutex_lock(&qcom_scm_lock);
- ret = __qcom_scm_call(cmd);
- mutex_unlock(&qcom_scm_lock);
- if (ret)
- goto out;
-
- rsp = qcom_scm_command_to_response(cmd);
- start = (unsigned long)rsp;
-
- do {
- qcom_scm_inv_range(start, start + sizeof(*rsp));
- } while (!rsp->is_complete);
-
- end = (unsigned long)qcom_scm_get_response_buffer(rsp) + resp_len;
- qcom_scm_inv_range(start, end);
-
- if (resp_buf)
- memcpy(resp_buf, qcom_scm_get_response_buffer(rsp), resp_len);
-out:
- free_qcom_scm_command(cmd);
- return ret;
-}
-
-#define SCM_CLASS_REGISTER (0x2 << 8)
-#define SCM_MASK_IRQS BIT(5)
-#define SCM_ATOMIC(svc, cmd, n) (((((svc) << 10)|((cmd) & 0x3ff)) << 12) | \
- SCM_CLASS_REGISTER | \
- SCM_MASK_IRQS | \
- (n & 0xf))
-
-/**
- * qcom_scm_call_atomic1() - Send an atomic SCM command with one argument
- * @svc_id: service identifier
- * @cmd_id: command identifier
- * @arg1: first argument
- *
- * This shall only be used with commands that are guaranteed to be
- * uninterruptable, atomic and SMP safe.
- */
-static s32 qcom_scm_call_atomic1(u32 svc, u32 cmd, u32 arg1)
-{
- int context_id;
-
- register u32 r0 asm("r0") = SCM_ATOMIC(svc, cmd, 1);
- register u32 r1 asm("r1") = (u32)&context_id;
- register u32 r2 asm("r2") = arg1;
-
- asm volatile(
- __asmeq("%0", "r0")
- __asmeq("%1", "r0")
- __asmeq("%2", "r1")
- __asmeq("%3", "r2")
-#ifdef REQUIRES_SEC
- ".arch_extension sec\n"
-#endif
- "smc #0 @ switch to secure world\n"
- : "=r" (r0)
- : "r" (r0), "r" (r1), "r" (r2)
- : "r3");
- return r0;
-}
-
-u32 qcom_scm_get_version(void)
-{
- int context_id;
- static u32 version = -1;
- register u32 r0 asm("r0");
- register u32 r1 asm("r1");
-
- if (version != -1)
- return version;
-
- mutex_lock(&qcom_scm_lock);
-
- r0 = 0x1 << 8;
- r1 = (u32)&context_id;
- do {
- asm volatile(
- __asmeq("%0", "r0")
- __asmeq("%1", "r1")
- __asmeq("%2", "r0")
- __asmeq("%3", "r1")
-#ifdef REQUIRES_SEC
- ".arch_extension sec\n"
-#endif
- "smc #0 @ switch to secure world\n"
- : "=r" (r0), "=r" (r1)
- : "r" (r0), "r" (r1)
- : "r2", "r3");
- } while (r0 == QCOM_SCM_INTERRUPTED);
-
- version = r1;
- mutex_unlock(&qcom_scm_lock);
-
- return version;
-}
-EXPORT_SYMBOL(qcom_scm_get_version);
-
-#define QCOM_SCM_SVC_BOOT 0x1
-#define QCOM_SCM_BOOT_ADDR 0x1
-/*
- * Set the cold/warm boot address for one of the CPU cores.
- */
-static int qcom_scm_set_boot_addr(u32 addr, int flags)
-{
- struct {
- __le32 flags;
- __le32 addr;
- } cmd;
-
- cmd.addr = cpu_to_le32(addr);
- cmd.flags = cpu_to_le32(flags);
- return qcom_scm_call(QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_ADDR,
- &cmd, sizeof(cmd), NULL, 0);
-}
+#include "qcom_scm.h"
/**
* qcom_scm_set_cold_boot_addr() - Set the cold boot address for cpus
@@ -414,26 +33,7 @@ static int qcom_scm_set_boot_addr(u32 addr, int flags)
*/
int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
{
- int flags = 0;
- int cpu;
- int scm_cb_flags[] = {
- QCOM_SCM_FLAG_COLDBOOT_CPU0,
- QCOM_SCM_FLAG_COLDBOOT_CPU1,
- QCOM_SCM_FLAG_COLDBOOT_CPU2,
- QCOM_SCM_FLAG_COLDBOOT_CPU3,
- };
-
- if (!cpus || (cpus && cpumask_empty(cpus)))
- return -EINVAL;
-
- for_each_cpu(cpu, cpus) {
- if (cpu < ARRAY_SIZE(scm_cb_flags))
- flags |= scm_cb_flags[cpu];
- else
- set_cpu_present(cpu, false);
- }
-
- return qcom_scm_set_boot_addr(virt_to_phys(entry), flags);
+ return __qcom_scm_set_cold_boot_addr(entry, cpus);
}
EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr);
@@ -447,37 +47,10 @@ EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr);
*/
int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
{
- int ret;
- int flags = 0;
- int cpu;
-
- /*
- * Reassign only if we are switching from hotplug entry point
- * to cpuidle entry point or vice versa.
- */
- for_each_cpu(cpu, cpus) {
- if (entry == qcom_scm_wb[cpu].entry)
- continue;
- flags |= qcom_scm_wb[cpu].flag;
- }
-
- /* No change in entry function */
- if (!flags)
- return 0;
-
- ret = qcom_scm_set_boot_addr(virt_to_phys(entry), flags);
- if (!ret) {
- for_each_cpu(cpu, cpus)
- qcom_scm_wb[cpu].entry = entry;
- }
-
- return ret;
+ return __qcom_scm_set_warm_boot_addr(entry, cpus);
}
EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr);
-#define QCOM_SCM_CMD_TERMINATE_PC 0x2
-#define QCOM_SCM_FLUSH_FLAG_MASK 0x3
-
/**
* qcom_scm_cpu_power_down() - Power down the cpu
* @flags - Flags to flush cache
@@ -488,7 +61,6 @@ EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr);
*/
void qcom_scm_cpu_power_down(u32 flags)
{
- qcom_scm_call_atomic1(QCOM_SCM_SVC_BOOT, QCOM_SCM_CMD_TERMINATE_PC,
- flags & QCOM_SCM_FLUSH_FLAG_MASK);
+ __qcom_scm_cpu_power_down(flags);
}
EXPORT_SYMBOL(qcom_scm_cpu_power_down);
diff --git a/drivers/firmware/qcom_scm.h b/drivers/firmware/qcom_scm.h
new file mode 100644
index 0000000..1172be9
--- /dev/null
+++ b/drivers/firmware/qcom_scm.h
@@ -0,0 +1,38 @@
+/* Copyright (c) 2010-2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef __QCOM_SCM_INT_H
+#define __QCOM_SCM_INT_H
+
+#define QCOM_SCM_SVC_BOOT 0x1
+#define QCOM_SCM_BOOT_ADDR 0x1
+#define QCOM_SCM_BOOT_ADDR_MC 0x11
+
+#define QCOM_SCM_FLAG_HLOS 0x01
+#define QCOM_SCM_FLAG_COLDBOOT_MC 0x02
+#define QCOM_SCM_FLAG_WARMBOOT_MC 0x04
+extern int __qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus);
+extern int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus);
+
+#define QCOM_SCM_CMD_TERMINATE_PC 0x2
+#define QCOM_SCM_FLUSH_FLAG_MASK 0x3
+#define QCOM_SCM_CMD_CORE_HOTPLUGGED 0x10
+extern void __qcom_scm_cpu_power_down(u32 flags);
+
+/* common error codes */
+#define QCOM_SCM_ENOMEM -5
+#define QCOM_SCM_EOPNOTSUPP -4
+#define QCOM_SCM_EINVAL_ADDR -3
+#define QCOM_SCM_EINVAL_ARG -2
+#define QCOM_SCM_ERROR -1
+#define QCOM_SCM_INTERRUPTED 1
+
+#endif
--
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
Add an implementation of the SCM interface that works on ARM64/64-bit SoCs
Signed-off-by: Kumar Gala <[email protected]>
Signed-off-by: Lina Iyer <[email protected]>
---
* v5:
- use common error defines from qcom_scm.h
- removed R*_STR defines
* v4:
- Folded in change to qcom_scm_cpu_power_down to remove HOTPLUG flag
from Lina.
arch/arm64/Kconfig | 1 +
drivers/firmware/Makefile | 4 +
drivers/firmware/qcom_scm-64.c | 452 +++++++++++++++++++++++++++++++++++++++++
3 files changed, 457 insertions(+)
create mode 100644 drivers/firmware/qcom_scm-64.c
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 4269dba..8878800 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -190,6 +190,7 @@ config ARCH_MEDIATEK
config ARCH_QCOM
bool "Qualcomm Platforms"
select PINCTRL
+ select QCOM_SCM
help
This enables support for the ARMv8 based Qualcomm chipsets.
diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile
index 3001f1a..c79751a 100644
--- a/drivers/firmware/Makefile
+++ b/drivers/firmware/Makefile
@@ -12,7 +12,11 @@ obj-$(CONFIG_ISCSI_IBFT_FIND) += iscsi_ibft_find.o
obj-$(CONFIG_ISCSI_IBFT) += iscsi_ibft.o
obj-$(CONFIG_FIRMWARE_MEMMAP) += memmap.o
obj-$(CONFIG_QCOM_SCM) += qcom_scm.o
+ifdef CONFIG_64BIT
+obj-$(CONFIG_QCOM_SCM) += qcom_scm-64.o
+else
obj-$(CONFIG_QCOM_SCM) += qcom_scm-32.o
+endif
CFLAGS_qcom_scm-32.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
obj-$(CONFIG_GOOGLE_FIRMWARE) += google/
diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-64.c
new file mode 100644
index 0000000..a95fd9b
--- /dev/null
+++ b/drivers/firmware/qcom_scm-64.c
@@ -0,0 +1,452 @@
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+
+#include <linux/cpumask.h>
+#include <linux/delay.h>
+#include <linux/mutex.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+#include <linux/qcom_scm.h>
+
+#include <asm/cacheflush.h>
+#include <asm/compiler.h>
+#include <asm/smp_plat.h>
+
+#include "qcom_scm.h"
+
+#define QCOM_SCM_SIP_FNID(s, c) (((((s) & 0xFF) << 8) | ((c) & 0xFF)) | 0x02000000)
+
+#define MAX_QCOM_SCM_ARGS 10
+#define MAX_QCOM_SCM_RETS 3
+
+#define QCOM_SCM_ARGS_IMPL(num, a, b, c, d, e, f, g, h, i, j, ...) (\
+ (((a) & 0xff) << 4) | \
+ (((b) & 0xff) << 6) | \
+ (((c) & 0xff) << 8) | \
+ (((d) & 0xff) << 10) | \
+ (((e) & 0xff) << 12) | \
+ (((f) & 0xff) << 14) | \
+ (((g) & 0xff) << 16) | \
+ (((h) & 0xff) << 18) | \
+ (((i) & 0xff) << 20) | \
+ (((j) & 0xff) << 22) | \
+ (num & 0xffff))
+
+#define QCOM_SCM_ARGS(...) QCOM_SCM_ARGS_IMPL(__VA_ARGS__, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
+
+/**
+ * struct qcom_scm_desc
+ * @arginfo: Metadata describing the arguments in args[]
+ * @args: The array of arguments for the secure syscall
+ * @ret: The values returned by the secure syscall
+ * @extra_arg_buf: The buffer containing extra arguments
+ (that don't fit in available registers)
+ * @x5: The 4rd argument to the secure syscall or physical address of
+ extra_arg_buf
+ */
+struct qcom_scm_desc {
+ u32 arginfo;
+ u64 args[MAX_QCOM_SCM_ARGS];
+ u64 ret[MAX_QCOM_SCM_RETS];
+
+ /* private */
+ void *extra_arg_buf;
+ u64 x5;
+};
+
+
+#define QCOM_SCM_EBUSY -55
+#define QCOM_SCM_V2_EBUSY -12
+
+static DEFINE_MUTEX(qcom_scm_lock);
+
+#define QCOM_SCM_EBUSY_WAIT_MS 30
+#define QCOM_SCM_EBUSY_MAX_RETRY 20
+
+#define N_EXT_QCOM_SCM_ARGS 7
+#define FIRST_EXT_ARG_IDX 3
+#define SMC_ATOMIC_SYSCALL 31
+#define N_REGISTER_ARGS (MAX_QCOM_SCM_ARGS - N_EXT_QCOM_SCM_ARGS + 1)
+#define SMC64_MASK 0x40000000
+#define SMC_ATOMIC_MASK 0x80000000
+#define IS_CALL_AVAIL_CMD 1
+
+static int qcom_scm_remap_error(int err)
+{
+ switch (err) {
+ case QCOM_SCM_ERROR:
+ return -EIO;
+ case QCOM_SCM_EINVAL_ADDR:
+ case QCOM_SCM_EINVAL_ARG:
+ return -EINVAL;
+ case QCOM_SCM_EOPNOTSUPP:
+ return -EOPNOTSUPP;
+ case QCOM_SCM_ENOMEM:
+ return -ENOMEM;
+ case QCOM_SCM_EBUSY:
+ return QCOM_SCM_EBUSY;
+ case QCOM_SCM_V2_EBUSY:
+ return QCOM_SCM_V2_EBUSY;
+ }
+ return -EINVAL;
+}
+
+int __qcom_scm_call_armv8_64(u64 x0, u64 x1, u64 x2, u64 x3, u64 x4, u64 x5,
+ u64 *ret1, u64 *ret2, u64 *ret3)
+{
+ register u64 r0 asm("r0") = x0;
+ register u64 r1 asm("r1") = x1;
+ register u64 r2 asm("r2") = x2;
+ register u64 r3 asm("r3") = x3;
+ register u64 r4 asm("r4") = x4;
+ register u64 r5 asm("r5") = x5;
+
+ do {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ __asmeq("%2", "x2")
+ __asmeq("%3", "x3")
+ __asmeq("%4", "x0")
+ __asmeq("%5", "x1")
+ __asmeq("%6", "x2")
+ __asmeq("%7", "x3")
+ __asmeq("%8", "x4")
+ __asmeq("%9", "x5")
+#ifdef REQUIRES_SEC
+ ".arch_extension sec\n"
+#endif
+ "smc #0\n"
+ : "=r" (r0), "=r" (r1), "=r" (r2), "=r" (r3)
+ : "r" (r0), "r" (r1), "r" (r2), "r" (r3), "r" (r4),
+ "r" (r5)
+ : "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13",
+ "x14", "x15", "x16", "x17");
+ } while (r0 == QCOM_SCM_INTERRUPTED);
+
+ if (ret1)
+ *ret1 = r1;
+ if (ret2)
+ *ret2 = r2;
+ if (ret3)
+ *ret3 = r3;
+
+ return r0;
+}
+
+int __qcom_scm_call_armv8_32(u32 w0, u32 w1, u32 w2, u32 w3, u32 w4, u32 w5,
+ u64 *ret1, u64 *ret2, u64 *ret3)
+{
+ register u32 r0 asm("r0") = w0;
+ register u32 r1 asm("r1") = w1;
+ register u32 r2 asm("r2") = w2;
+ register u32 r3 asm("r3") = w3;
+ register u32 r4 asm("r4") = w4;
+ register u32 r5 asm("r5") = w5;
+
+ do {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ __asmeq("%2", "x2")
+ __asmeq("%3", "x3")
+ __asmeq("%4", "x0")
+ __asmeq("%5", "x1")
+ __asmeq("%6", "x2")
+ __asmeq("%7", "x3")
+ __asmeq("%8", "x4")
+ __asmeq("%9", "x5")
+#ifdef REQUIRES_SEC
+ ".arch_extension sec\n"
+#endif
+ "smc #0\n"
+ : "=r" (r0), "=r" (r1), "=r" (r2), "=r" (r3)
+ : "r" (r0), "r" (r1), "r" (r2), "r" (r3), "r" (r4),
+ "r" (r5)
+ : "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13",
+ "x14", "x15", "x16", "x17");
+
+ } while (r0 == QCOM_SCM_INTERRUPTED);
+
+ if (ret1)
+ *ret1 = r1;
+ if (ret2)
+ *ret2 = r2;
+ if (ret3)
+ *ret3 = r3;
+
+ return r0;
+}
+
+struct qcom_scm_extra_arg {
+ union {
+ u32 args32[N_EXT_QCOM_SCM_ARGS];
+ u64 args64[N_EXT_QCOM_SCM_ARGS];
+ };
+};
+
+static enum qcom_scm_interface_version {
+ QCOM_SCM_UNKNOWN,
+ QCOM_SCM_LEGACY,
+ QCOM_SCM_ARMV8_32,
+ QCOM_SCM_ARMV8_64,
+} qcom_scm_version = QCOM_SCM_UNKNOWN;
+
+/* This will be set to specify SMC32 or SMC64 */
+static u32 qcom_scm_version_mask;
+
+/*
+ * If there are more than N_REGISTER_ARGS, allocate a buffer and place
+ * the additional arguments in it. The extra argument buffer will be
+ * pointed to by X5.
+ */
+static int allocate_extra_arg_buffer(struct qcom_scm_desc *desc, gfp_t flags)
+{
+ int i, j;
+ struct qcom_scm_extra_arg *argbuf;
+ int arglen = desc->arginfo & 0xf;
+ size_t argbuflen = PAGE_ALIGN(sizeof(struct qcom_scm_extra_arg));
+
+ desc->x5 = desc->args[FIRST_EXT_ARG_IDX];
+
+ if (likely(arglen <= N_REGISTER_ARGS)) {
+ desc->extra_arg_buf = NULL;
+ return 0;
+ }
+
+ argbuf = kzalloc(argbuflen, flags);
+ if (!argbuf) {
+ pr_err("qcom_scm_call: failed to alloc mem for extended argument buffer\n");
+ return -ENOMEM;
+ }
+
+ desc->extra_arg_buf = argbuf;
+
+ j = FIRST_EXT_ARG_IDX;
+ if (qcom_scm_version == QCOM_SCM_ARMV8_64)
+ for (i = 0; i < N_EXT_QCOM_SCM_ARGS; i++)
+ argbuf->args64[i] = desc->args[j++];
+ else
+ for (i = 0; i < N_EXT_QCOM_SCM_ARGS; i++)
+ argbuf->args32[i] = desc->args[j++];
+ desc->x5 = virt_to_phys(argbuf);
+ __flush_dcache_area(argbuf, argbuflen);
+
+ return 0;
+}
+
+/**
+ * qcom_scm_call() - Invoke a syscall in the secure world
+ * @svc_id: service identifier
+ * @cmd_id: command identifier
+ * @fn_id: The function ID for this syscall
+ * @desc: Descriptor structure containing arguments and return values
+ *
+ * Sends a command to the SCM and waits for the command to finish processing.
+ * This should *only* be called in pre-emptible context.
+ *
+ * A note on cache maintenance:
+ * Note that any buffers that are expected to be accessed by the secure world
+ * must be flushed before invoking qcom_scm_call and invalidated in the cache
+ * immediately after qcom_scm_call returns. An important point that must be noted
+ * is that on ARMV8 architectures, invalidation actually also causes a dirty
+ * cache line to be cleaned (flushed + unset-dirty-bit). Therefore it is of
+ * paramount importance that the buffer be flushed before invoking qcom_scm_call,
+ * even if you don't care about the contents of that buffer.
+ *
+ * Note that cache maintenance on the argument buffer (desc->args) is taken care
+ * of by qcom_scm_call; however, callers are responsible for any other cached
+ * buffers passed over to the secure world.
+*/
+static int qcom_scm_call(u32 svc_id, u32 cmd_id, struct qcom_scm_desc *desc)
+{
+ int arglen = desc->arginfo & 0xf;
+ int ret, retry_count = 0;
+ u32 fn_id = QCOM_SCM_SIP_FNID(svc_id, cmd_id);
+ u64 x0;
+
+ ret = allocate_extra_arg_buffer(desc, GFP_KERNEL);
+ if (ret)
+ return ret;
+
+ x0 = fn_id | qcom_scm_version_mask;
+
+ do {
+ mutex_lock(&qcom_scm_lock);
+
+ desc->ret[0] = desc->ret[1] = desc->ret[2] = 0;
+
+ pr_debug("qcom_scm_call: func id %#llx, args: %#x, %#llx, %#llx, %#llx, %#llx\n",
+ x0, desc->arginfo, desc->args[0], desc->args[1],
+ desc->args[2], desc->x5);
+
+ if (qcom_scm_version == QCOM_SCM_ARMV8_64)
+ ret = __qcom_scm_call_armv8_64(x0, desc->arginfo,
+ desc->args[0], desc->args[1],
+ desc->args[2], desc->x5,
+ &desc->ret[0], &desc->ret[1],
+ &desc->ret[2]);
+ else
+ ret = __qcom_scm_call_armv8_32(x0, desc->arginfo,
+ desc->args[0], desc->args[1],
+ desc->args[2], desc->x5,
+ &desc->ret[0], &desc->ret[1],
+ &desc->ret[2]);
+ mutex_unlock(&qcom_scm_lock);
+
+ if (ret == QCOM_SCM_V2_EBUSY)
+ msleep(QCOM_SCM_EBUSY_WAIT_MS);
+ } while (ret == QCOM_SCM_V2_EBUSY && (retry_count++ < QCOM_SCM_EBUSY_MAX_RETRY));
+
+ if (ret < 0)
+ pr_err("qcom_scm_call failed: func id %#llx, arginfo: %#x, args: %#llx, %#llx, %#llx, %#llx, ret: %d, syscall returns: %#llx, %#llx, %#llx\n",
+ x0, desc->arginfo, desc->args[0], desc->args[1],
+ desc->args[2], desc->x5, ret, desc->ret[0],
+ desc->ret[1], desc->ret[2]);
+
+ if (arglen > N_REGISTER_ARGS)
+ kfree(desc->extra_arg_buf);
+ if (ret < 0)
+ return qcom_scm_remap_error(ret);
+ return 0;
+}
+
+/**
+ * qcom_scm_call_atomic() - Invoke a syscall in the secure world
+ *
+ * Similar to qcom_scm_call except that this can be invoked in atomic context.
+ * There is also no retry mechanism implemented. Please ensure that the
+ * secure world syscall can be executed in such a context and can complete
+ * in a timely manner.
+ */
+static int qcom_scm_call_atomic(u32 s, u32 c, struct qcom_scm_desc *desc)
+{
+ int arglen = desc->arginfo & 0xf;
+ int ret;
+ u32 fn_id = QCOM_SCM_SIP_FNID(s, c);
+ u64 x0;
+
+ ret = allocate_extra_arg_buffer(desc, GFP_ATOMIC);
+ if (ret)
+ return ret;
+
+ x0 = fn_id | BIT(SMC_ATOMIC_SYSCALL) | qcom_scm_version_mask;
+
+ pr_debug("qcom_scm_call: func id %#llx, args: %#x, %#llx, %#llx, %#llx, %#llx\n",
+ x0, desc->arginfo, desc->args[0], desc->args[1],
+ desc->args[2], desc->x5);
+
+ if (qcom_scm_version == QCOM_SCM_ARMV8_64)
+ ret = __qcom_scm_call_armv8_64(x0, desc->arginfo, desc->args[0],
+ desc->args[1], desc->args[2],
+ desc->x5, &desc->ret[0],
+ &desc->ret[1], &desc->ret[2]);
+ else
+ ret = __qcom_scm_call_armv8_32(x0, desc->arginfo, desc->args[0],
+ desc->args[1], desc->args[2],
+ desc->x5, &desc->ret[0],
+ &desc->ret[1], &desc->ret[2]);
+ if (ret < 0)
+ pr_err("qcom_scm_call failed: func id %#llx, arginfo: %#x, args: %#llx, %#llx, %#llx, %#llx, ret: %d, syscall returns: %#llx, %#llx, %#llx\n",
+ x0, desc->arginfo, desc->args[0], desc->args[1],
+ desc->args[2], desc->x5, ret, desc->ret[0],
+ desc->ret[1], desc->ret[2]);
+
+ if (arglen > N_REGISTER_ARGS)
+ kfree(desc->extra_arg_buf);
+ if (ret < 0)
+ return qcom_scm_remap_error(ret);
+ return ret;
+}
+
+static int qcom_scm_set_boot_addr(void *entry, const cpumask_t *cpus, int flags)
+{
+ struct qcom_scm_desc desc = {0};
+ unsigned int cpu = cpumask_first(cpus);
+ u64 mpidr_el1 = cpu_logical_map(cpu);
+
+ /* For now we assume only a single cpu is set in the mask */
+ WARN_ON(cpumask_weight(cpus) != 1);
+
+ if (mpidr_el1 & ~MPIDR_HWID_BITMASK) {
+ pr_err("CPU%d:Failed to set boot address\n", cpu);
+ return -ENOSYS;
+ }
+
+ desc.args[0] = virt_to_phys(entry);
+ desc.args[1] = BIT(MPIDR_AFFINITY_LEVEL(mpidr_el1, 0));
+ desc.args[2] = BIT(MPIDR_AFFINITY_LEVEL(mpidr_el1, 1));
+ desc.args[3] = BIT(MPIDR_AFFINITY_LEVEL(mpidr_el1, 2));
+ desc.args[4] = ~0ULL;
+ desc.args[5] = QCOM_SCM_FLAG_HLOS | flags;
+ desc.arginfo = QCOM_SCM_ARGS(6);
+
+ return qcom_scm_call(QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_ADDR_MC, &desc);
+}
+
+int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
+{
+ int flags = QCOM_SCM_FLAG_COLDBOOT_MC;
+
+ return qcom_scm_set_boot_addr(entry, cpus, flags);
+}
+
+int __qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
+{
+ int flags = QCOM_SCM_FLAG_WARMBOOT_MC;
+
+ return qcom_scm_set_boot_addr(entry, cpus, flags);
+}
+
+void __qcom_scm_cpu_power_down(u32 flags)
+{
+ struct qcom_scm_desc desc = {0};
+ desc.args[0] = flags & QCOM_SCM_FLUSH_FLAG_MASK;
+ desc.arginfo = QCOM_SCM_ARGS(1);
+
+ qcom_scm_call_atomic(QCOM_SCM_SVC_BOOT, QCOM_SCM_CMD_TERMINATE_PC, &desc);
+}
+
+#define QCOM_SCM_SVC_INFO 0x6
+static int __init qcom_scm_init(void)
+{
+ int ret;
+ u64 ret1 = 0, x0;
+
+ /* First try a SMC64 call */
+ qcom_scm_version = QCOM_SCM_ARMV8_64;
+ x0 = QCOM_SCM_SIP_FNID(QCOM_SCM_SVC_INFO, IS_CALL_AVAIL_CMD) | SMC_ATOMIC_MASK;
+ ret = __qcom_scm_call_armv8_64(x0 | SMC64_MASK, QCOM_SCM_ARGS(1), x0, 0, 0, 0,
+ &ret1, NULL, NULL);
+ if (ret || !ret1) {
+ /* Try SMC32 call */
+ ret1 = 0;
+ ret = __qcom_scm_call_armv8_32(x0, QCOM_SCM_ARGS(1), x0, 0, 0,
+ 0, &ret1, NULL, NULL);
+ if (ret || !ret1)
+ qcom_scm_version = QCOM_SCM_LEGACY;
+ else
+ qcom_scm_version = QCOM_SCM_ARMV8_32;
+ } else
+ qcom_scm_version_mask = SMC64_MASK;
+
+ pr_debug("qcom_scm_call: qcom_scm version is %x, mask is %x\n",
+ qcom_scm_version, qcom_scm_version_mask);
+
+ return 0;
+}
+early_initcall(qcom_scm_init);
--
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
Hi Kumar,
On Tue, Apr 28, 2015 at 08:23:58PM +0100, Kumar Gala wrote:
> Add an implementation of the SCM interface that works on ARM64/64-bit SoCs
What is the intended use of this on arm64 SoCs?
Given the negative reaction to the SMP bringup [1] code that seems to be
the only user, I'm somewhat confused as to why this is being pushed as a
non-RFC in the mean time.
Are there other users of this interface code? If so, could you please
mention that in the commit message. I'd also ask that you would Cc me on
future postings of this series.
[...]
> +static int qcom_scm_set_boot_addr(void *entry, const cpumask_t *cpus, int flags)
> +{
> + struct qcom_scm_desc desc = {0};
> + unsigned int cpu = cpumask_first(cpus);
> + u64 mpidr_el1 = cpu_logical_map(cpu);
> +
> + /* For now we assume only a single cpu is set in the mask */
> + WARN_ON(cpumask_weight(cpus) != 1);
> +
> + if (mpidr_el1 & ~MPIDR_HWID_BITMASK) {
> + pr_err("CPU%d:Failed to set boot address\n", cpu);
> + return -ENOSYS;
> + }
> +
> + desc.args[0] = virt_to_phys(entry);
> + desc.args[1] = BIT(MPIDR_AFFINITY_LEVEL(mpidr_el1, 0));
> + desc.args[2] = BIT(MPIDR_AFFINITY_LEVEL(mpidr_el1, 1));
> + desc.args[3] = BIT(MPIDR_AFFINITY_LEVEL(mpidr_el1, 2));
> + desc.args[4] = ~0ULL;
> + desc.args[5] = QCOM_SCM_FLAG_HLOS | flags;
> + desc.arginfo = QCOM_SCM_ARGS(6);
> +
> + return qcom_scm_call(QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_ADDR_MC, &desc);
> +}
> +
> +int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
> +{
> + int flags = QCOM_SCM_FLAG_COLDBOOT_MC;
> +
> + return qcom_scm_set_boot_addr(entry, cpus, flags);
> +}
> +
> +int __qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
> +{
> + int flags = QCOM_SCM_FLAG_WARMBOOT_MC;
> +
> + return qcom_scm_set_boot_addr(entry, cpus, flags);
> +}
> +
> +void __qcom_scm_cpu_power_down(u32 flags)
> +{
> + struct qcom_scm_desc desc = {0};
> + desc.args[0] = flags & QCOM_SCM_FLUSH_FLAG_MASK;
> + desc.arginfo = QCOM_SCM_ARGS(1);
> +
> + qcom_scm_call_atomic(QCOM_SCM_SVC_BOOT, QCOM_SCM_CMD_TERMINATE_PC, &desc);
> +}
As mentioned in the other thread, I don't want to see this for arm64,
and must NAK this portion.
Thanks,
Mark.
[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-April/336534.html
> On Apr 29, 2015, at 10:42 AM, Mark Rutland <[email protected]> wrote:
>
> Hi Kumar,
>
> On Tue, Apr 28, 2015 at 08:23:58PM +0100, Kumar Gala wrote:
>> Add an implementation of the SCM interface that works on ARM64/64-bit SoCs
>
> What is the intended use of this on arm64 SoCs?
>
> Given the negative reaction to the SMP bringup [1] code that seems to be
> the only user, I'm somewhat confused as to why this is being pushed as a
> non-RFC in the mean time.
>
> Are there other users of this interface code? If so, could you please
> mention that in the commit message. I'd also ask that you would Cc me on
> future postings of this series.
>
> […]
The SCM interface is needed for other things like display:
https://patchwork.kernel.org/patch/6198691/
>
>> +static int qcom_scm_set_boot_addr(void *entry, const cpumask_t *cpus, int flags)
>> +{
>> + struct qcom_scm_desc desc = {0};
>> + unsigned int cpu = cpumask_first(cpus);
>> + u64 mpidr_el1 = cpu_logical_map(cpu);
>> +
>> + /* For now we assume only a single cpu is set in the mask */
>> + WARN_ON(cpumask_weight(cpus) != 1);
>> +
>> + if (mpidr_el1 & ~MPIDR_HWID_BITMASK) {
>> + pr_err("CPU%d:Failed to set boot address\n", cpu);
>> + return -ENOSYS;
>> + }
>> +
>> + desc.args[0] = virt_to_phys(entry);
>> + desc.args[1] = BIT(MPIDR_AFFINITY_LEVEL(mpidr_el1, 0));
>> + desc.args[2] = BIT(MPIDR_AFFINITY_LEVEL(mpidr_el1, 1));
>> + desc.args[3] = BIT(MPIDR_AFFINITY_LEVEL(mpidr_el1, 2));
>> + desc.args[4] = ~0ULL;
>> + desc.args[5] = QCOM_SCM_FLAG_HLOS | flags;
>> + desc.arginfo = QCOM_SCM_ARGS(6);
>> +
>> + return qcom_scm_call(QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_ADDR_MC, &desc);
>> +}
>> +
>> +int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
>> +{
>> + int flags = QCOM_SCM_FLAG_COLDBOOT_MC;
>> +
>> + return qcom_scm_set_boot_addr(entry, cpus, flags);
>> +}
>> +
>> +int __qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
>> +{
>> + int flags = QCOM_SCM_FLAG_WARMBOOT_MC;
>> +
>> + return qcom_scm_set_boot_addr(entry, cpus, flags);
>> +}
>> +
>> +void __qcom_scm_cpu_power_down(u32 flags)
>> +{
>> + struct qcom_scm_desc desc = {0};
>> + desc.args[0] = flags & QCOM_SCM_FLUSH_FLAG_MASK;
>> + desc.arginfo = QCOM_SCM_ARGS(1);
>> +
>> + qcom_scm_call_atomic(QCOM_SCM_SVC_BOOT, QCOM_SCM_CMD_TERMINATE_PC, &desc);
>> +}
>
> As mentioned in the other thread, I don't want to see this for arm64,
> and must NAK this portion.
I can have these return an error code, but we want to keep the interface the same between the 32-bit and 64-bit.
- k
--
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
On Wed, Apr 29, 2015 at 05:18:04PM +0100, Kumar Gala wrote:
>
> > On Apr 29, 2015, at 10:42 AM, Mark Rutland <[email protected]> wrote:
> >
> > Hi Kumar,
> >
> > On Tue, Apr 28, 2015 at 08:23:58PM +0100, Kumar Gala wrote:
> >> Add an implementation of the SCM interface that works on ARM64/64-bit SoCs
> >
> > What is the intended use of this on arm64 SoCs?
> >
> > Given the negative reaction to the SMP bringup [1] code that seems to be
> > the only user, I'm somewhat confused as to why this is being pushed as a
> > non-RFC in the mean time.
> >
> > Are there other users of this interface code? If so, could you please
> > mention that in the commit message. I'd also ask that you would Cc me on
> > future postings of this series.
> >
> > […]
>
> The SCM interface is needed for other things like display:
>
> https://patchwork.kernel.org/patch/6198691/
Thanks for the link. It would be good if you could mention some users in
the commit message.
> >> +static int qcom_scm_set_boot_addr(void *entry, const cpumask_t *cpus, int flags)
> >> +{
> >> + struct qcom_scm_desc desc = {0};
> >> + unsigned int cpu = cpumask_first(cpus);
> >> + u64 mpidr_el1 = cpu_logical_map(cpu);
> >> +
> >> + /* For now we assume only a single cpu is set in the mask */
> >> + WARN_ON(cpumask_weight(cpus) != 1);
> >> +
> >> + if (mpidr_el1 & ~MPIDR_HWID_BITMASK) {
> >> + pr_err("CPU%d:Failed to set boot address\n", cpu);
> >> + return -ENOSYS;
> >> + }
> >> +
> >> + desc.args[0] = virt_to_phys(entry);
> >> + desc.args[1] = BIT(MPIDR_AFFINITY_LEVEL(mpidr_el1, 0));
> >> + desc.args[2] = BIT(MPIDR_AFFINITY_LEVEL(mpidr_el1, 1));
> >> + desc.args[3] = BIT(MPIDR_AFFINITY_LEVEL(mpidr_el1, 2));
> >> + desc.args[4] = ~0ULL;
> >> + desc.args[5] = QCOM_SCM_FLAG_HLOS | flags;
> >> + desc.arginfo = QCOM_SCM_ARGS(6);
> >> +
> >> + return qcom_scm_call(QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_ADDR_MC, &desc);
> >> +}
> >> +
> >> +int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
> >> +{
> >> + int flags = QCOM_SCM_FLAG_COLDBOOT_MC;
> >> +
> >> + return qcom_scm_set_boot_addr(entry, cpus, flags);
> >> +}
> >> +
> >> +int __qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
> >> +{
> >> + int flags = QCOM_SCM_FLAG_WARMBOOT_MC;
> >> +
> >> + return qcom_scm_set_boot_addr(entry, cpus, flags);
> >> +}
> >> +
> >> +void __qcom_scm_cpu_power_down(u32 flags)
> >> +{
> >> + struct qcom_scm_desc desc = {0};
> >> + desc.args[0] = flags & QCOM_SCM_FLUSH_FLAG_MASK;
> >> + desc.arginfo = QCOM_SCM_ARGS(1);
> >> +
> >> + qcom_scm_call_atomic(QCOM_SCM_SVC_BOOT, QCOM_SCM_CMD_TERMINATE_PC, &desc);
> >> +}
> >
> > As mentioned in the other thread, I don't want to see this for arm64,
> > and must NAK this portion.
>
> I can have these return an error code, but we want to keep the interface the same between the 32-bit and 64-bit.
I don't follow. If nothing calls these on the 64-bit side, then there's
no interface they need to be there for.
Thanks,
Mark.
> On Apr 29, 2015, at 11:38 AM, Mark Rutland <[email protected]> wrote:
>
> On Wed, Apr 29, 2015 at 05:18:04PM +0100, Kumar Gala wrote:
>>
>>> On Apr 29, 2015, at 10:42 AM, Mark Rutland <[email protected]> wrote:
>>>
>>> Hi Kumar,
>>>
>>> On Tue, Apr 28, 2015 at 08:23:58PM +0100, Kumar Gala wrote:
>>>> Add an implementation of the SCM interface that works on ARM64/64-bit SoCs
>>>
>>> What is the intended use of this on arm64 SoCs?
>>>
>>> Given the negative reaction to the SMP bringup [1] code that seems to be
>>> the only user, I'm somewhat confused as to why this is being pushed as a
>>> non-RFC in the mean time.
>>>
>>> Are there other users of this interface code? If so, could you please
>>> mention that in the commit message. I'd also ask that you would Cc me on
>>> future postings of this series.
>>>
>>> […]
>>
>> The SCM interface is needed for other things like display:
>>
>> https://patchwork.kernel.org/patch/6198691/
>
> Thanks for the link. It would be good if you could mention some users in
> the commit message.
I’ll update the commit message
>
>>>> +static int qcom_scm_set_boot_addr(void *entry, const cpumask_t *cpus, int flags)
>>>> +{
>>>> + struct qcom_scm_desc desc = {0};
>>>> + unsigned int cpu = cpumask_first(cpus);
>>>> + u64 mpidr_el1 = cpu_logical_map(cpu);
>>>> +
>>>> + /* For now we assume only a single cpu is set in the mask */
>>>> + WARN_ON(cpumask_weight(cpus) != 1);
>>>> +
>>>> + if (mpidr_el1 & ~MPIDR_HWID_BITMASK) {
>>>> + pr_err("CPU%d:Failed to set boot address\n", cpu);
>>>> + return -ENOSYS;
>>>> + }
>>>> +
>>>> + desc.args[0] = virt_to_phys(entry);
>>>> + desc.args[1] = BIT(MPIDR_AFFINITY_LEVEL(mpidr_el1, 0));
>>>> + desc.args[2] = BIT(MPIDR_AFFINITY_LEVEL(mpidr_el1, 1));
>>>> + desc.args[3] = BIT(MPIDR_AFFINITY_LEVEL(mpidr_el1, 2));
>>>> + desc.args[4] = ~0ULL;
>>>> + desc.args[5] = QCOM_SCM_FLAG_HLOS | flags;
>>>> + desc.arginfo = QCOM_SCM_ARGS(6);
>>>> +
>>>> + return qcom_scm_call(QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_ADDR_MC, &desc);
>>>> +}
>>>> +
>>>> +int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
>>>> +{
>>>> + int flags = QCOM_SCM_FLAG_COLDBOOT_MC;
>>>> +
>>>> + return qcom_scm_set_boot_addr(entry, cpus, flags);
>>>> +}
>>>> +
>>>> +int __qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
>>>> +{
>>>> + int flags = QCOM_SCM_FLAG_WARMBOOT_MC;
>>>> +
>>>> + return qcom_scm_set_boot_addr(entry, cpus, flags);
>>>> +}
>>>> +
>>>> +void __qcom_scm_cpu_power_down(u32 flags)
>>>> +{
>>>> + struct qcom_scm_desc desc = {0};
>>>> + desc.args[0] = flags & QCOM_SCM_FLUSH_FLAG_MASK;
>>>> + desc.arginfo = QCOM_SCM_ARGS(1);
>>>> +
>>>> + qcom_scm_call_atomic(QCOM_SCM_SVC_BOOT, QCOM_SCM_CMD_TERMINATE_PC, &desc);
>>>> +}
>>>
>>> As mentioned in the other thread, I don't want to see this for arm64,
>>> and must NAK this portion.
>>
>> I can have these return an error code, but we want to keep the interface the same between the 32-bit and 64-bit.
>
> I don't follow. If nothing calls these on the 64-bit side, then there's
> no interface they need to be there for.
>
> Thanks,
> Mark.
While nothing may call them, its still easier to try and keep the interface the same between 32 and 64-bit side of things. Its the equivalent of when we have a CONFIG_ option disabled, but still allow things to build.
- k
--
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
On 04/28/2015 12:23 PM, Kumar Gala wrote:
> +
> +int __qcom_scm_call_armv8_64(u64 x0, u64 x1, u64 x2, u64 x3, u64 x4, u64 x5,
> + u64 *ret1, u64 *ret2, u64 *ret3)
> +{
> + register u64 r0 asm("r0") = x0;
> + register u64 r1 asm("r1") = x1;
> + register u64 r2 asm("r2") = x2;
> + register u64 r3 asm("r3") = x3;
> + register u64 r4 asm("r4") = x4;
> + register u64 r5 asm("r5") = x5;
This should set x6 to 0.
register u32 r6 asm("r6") = 0;
for example.
> +
> + do {
> + asm volatile(
> + __asmeq("%0", "x0")
> + __asmeq("%1", "x1")
> + __asmeq("%2", "x2")
> + __asmeq("%3", "x3")
> + __asmeq("%4", "x0")
> + __asmeq("%5", "x1")
> + __asmeq("%6", "x2")
> + __asmeq("%7", "x3")
> + __asmeq("%8", "x4")
> + __asmeq("%9", "x5")
And then the asmeq thing here for x6.
> +#ifdef REQUIRES_SEC
> + ".arch_extension sec\n"
> +#endif
> + "smc #0\n"
> + : "=r" (r0), "=r" (r1), "=r" (r2), "=r" (r3)
> + : "r" (r0), "r" (r1), "r" (r2), "r" (r3), "r" (r4),
> + "r" (r5)
And add x6 as an input here.
> + : "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13",
and remove x6 as a clobber.
> + "x14", "x15", "x16", "x17");
> + } while (r0 == QCOM_SCM_INTERRUPTED);
> +
> + if (ret1)
> + *ret1 = r1;
> + if (ret2)
> + *ret2 = r2;
> + if (ret3)
> + *ret3 = r3;
> +
> + return r0;
> +}
> +
> +int __qcom_scm_call_armv8_32(u32 w0, u32 w1, u32 w2, u32 w3, u32 w4, u32 w5,
> + u64 *ret1, u64 *ret2, u64 *ret3)
> +{
> + register u32 r0 asm("r0") = w0;
> + register u32 r1 asm("r1") = w1;
> + register u32 r2 asm("r2") = w2;
> + register u32 r3 asm("r3") = w3;
> + register u32 r4 asm("r4") = w4;
> + register u32 r5 asm("r5") = w5;
This needs to set r6 to 0 as well
register u32 r6 asm("r6") = 0;
for example.
> +
> + do {
> + asm volatile(
> + __asmeq("%0", "x0")
> + __asmeq("%1", "x1")
> + __asmeq("%2", "x2")
> + __asmeq("%3", "x3")
> + __asmeq("%4", "x0")
> + __asmeq("%5", "x1")
> + __asmeq("%6", "x2")
> + __asmeq("%7", "x3")
> + __asmeq("%8", "x4")
> + __asmeq("%9", "x5")
And then another asmeq thing here for x6.
> +#ifdef REQUIRES_SEC
> + ".arch_extension sec\n"
> +#endif
> + "smc #0\n"
> + : "=r" (r0), "=r" (r1), "=r" (r2), "=r" (r3)
> + : "r" (r0), "r" (r1), "r" (r2), "r" (r3), "r" (r4),
> + "r" (r5)
And then add r6 here as an input
> + : "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13",
And remove r6 from the clobber.
> + "x14", "x15", "x16", "x17");
> +
> + } while (r0 == QCOM_SCM_INTERRUPTED);
> +
> + if (ret1)
> + *ret1 = r1;
> + if (ret2)
> + *ret2 = r2;
> + if (ret3)
> + *ret3 = r3;
> +
> + return r0;
> +}
> +
>
Here's a totally untested patch for that.
Signed-off-by: Stephen Boyd <[email protected]>
----8<-----
diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-64.c
index a95fd9b5d576..8f7e65ff524c 100644
--- a/drivers/firmware/qcom_scm-64.c
+++ b/drivers/firmware/qcom_scm-64.c
@@ -114,6 +114,7 @@ int __qcom_scm_call_armv8_64(u64 x0, u64 x1, u64 x2, u64 x3, u64 x4, u64 x5,
register u64 r3 asm("r3") = x3;
register u64 r4 asm("r4") = x4;
register u64 r5 asm("r5") = x5;
+ register u64 r6 asm("r5") = 0;
do {
asm volatile(
@@ -127,14 +128,15 @@ int __qcom_scm_call_armv8_64(u64 x0, u64 x1, u64 x2, u64 x3, u64 x4, u64 x5,
__asmeq("%7", "x3")
__asmeq("%8", "x4")
__asmeq("%9", "x5")
+ __asmeq("%10", "x6")
#ifdef REQUIRES_SEC
".arch_extension sec\n"
#endif
"smc #0\n"
: "=r" (r0), "=r" (r1), "=r" (r2), "=r" (r3)
: "r" (r0), "r" (r1), "r" (r2), "r" (r3), "r" (r4),
- "r" (r5)
- : "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13",
+ "r" (r5), "r" (r6)
+ : "x7", "x8", "x9", "x10", "x11", "x12", "x13",
"x14", "x15", "x16", "x17");
} while (r0 == QCOM_SCM_INTERRUPTED);
@@ -157,6 +159,7 @@ int __qcom_scm_call_armv8_32(u32 w0, u32 w1, u32 w2, u32 w3, u32 w4, u32 w5,
register u32 r3 asm("r3") = w3;
register u32 r4 asm("r4") = w4;
register u32 r5 asm("r5") = w5;
+ register u32 r6 asm("r6") = 0;
do {
asm volatile(
@@ -170,14 +173,15 @@ int __qcom_scm_call_armv8_32(u32 w0, u32 w1, u32 w2, u32 w3, u32 w4, u32 w5,
__asmeq("%7", "x3")
__asmeq("%8", "x4")
__asmeq("%9", "x5")
+ __asmeq("%10", "x6")
#ifdef REQUIRES_SEC
".arch_extension sec\n"
#endif
"smc #0\n"
: "=r" (r0), "=r" (r1), "=r" (r2), "=r" (r3)
: "r" (r0), "r" (r1), "r" (r2), "r" (r3), "r" (r4),
- "r" (r5)
- : "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13",
+ "r" (r5), "r" (r6)
+ : "x7", "x8", "x9", "x10", "x11", "x12", "x13",
"x14", "x15", "x16", "x17");
} while (r0 == QCOM_SCM_INTERRUPTED);
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
On Wed, Aug 05, 2015 at 06:27:24PM -0700, Stephen Boyd wrote:
> On 04/28/2015 12:23 PM, Kumar Gala wrote:
> >+
> >+int __qcom_scm_call_armv8_64(u64 x0, u64 x1, u64 x2, u64 x3, u64 x4, u64 x5,
> >+ u64 *ret1, u64 *ret2, u64 *ret3)
> >+{
> >+ register u64 r0 asm("r0") = x0;
> >+ register u64 r1 asm("r1") = x1;
> >+ register u64 r2 asm("r2") = x2;
> >+ register u64 r3 asm("r3") = x3;
> >+ register u64 r4 asm("r4") = x4;
> >+ register u64 r5 asm("r5") = x5;
>
> This should set x6 to 0.
>
> register u32 r6 asm("r6") = 0;
>
> for example.
>
> >+
> >+ do {
> >+ asm volatile(
> >+ __asmeq("%0", "x0")
> >+ __asmeq("%1", "x1")
> >+ __asmeq("%2", "x2")
> >+ __asmeq("%3", "x3")
> >+ __asmeq("%4", "x0")
> >+ __asmeq("%5", "x1")
> >+ __asmeq("%6", "x2")
> >+ __asmeq("%7", "x3")
> >+ __asmeq("%8", "x4")
> >+ __asmeq("%9", "x5")
>
> And then the asmeq thing here for x6.
>
> >+#ifdef REQUIRES_SEC
> >+ ".arch_extension sec\n"
> >+#endif
> >+ "smc #0\n"
> >+ : "=r" (r0), "=r" (r1), "=r" (r2), "=r" (r3)
> >+ : "r" (r0), "r" (r1), "r" (r2), "r" (r3), "r" (r4),
> >+ "r" (r5)
>
> And add x6 as an input here.
>
> >+ : "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13",
>
> and remove x6 as a clobber.
>
> >+ "x14", "x15", "x16", "x17");
> >+ } while (r0 == QCOM_SCM_INTERRUPTED);
> >+
> >+ if (ret1)
> >+ *ret1 = r1;
> >+ if (ret2)
> >+ *ret2 = r2;
> >+ if (ret3)
> >+ *ret3 = r3;
> >+
> >+ return r0;
> >+}
> >+
> >+int __qcom_scm_call_armv8_32(u32 w0, u32 w1, u32 w2, u32 w3, u32 w4, u32 w5,
> >+ u64 *ret1, u64 *ret2, u64 *ret3)
> >+{
> >+ register u32 r0 asm("r0") = w0;
> >+ register u32 r1 asm("r1") = w1;
> >+ register u32 r2 asm("r2") = w2;
> >+ register u32 r3 asm("r3") = w3;
> >+ register u32 r4 asm("r4") = w4;
> >+ register u32 r5 asm("r5") = w5;
>
> This needs to set r6 to 0 as well
>
> register u32 r6 asm("r6") = 0;
>
> for example.
>
> >+
> >+ do {
> >+ asm volatile(
> >+ __asmeq("%0", "x0")
> >+ __asmeq("%1", "x1")
> >+ __asmeq("%2", "x2")
> >+ __asmeq("%3", "x3")
> >+ __asmeq("%4", "x0")
> >+ __asmeq("%5", "x1")
> >+ __asmeq("%6", "x2")
> >+ __asmeq("%7", "x3")
> >+ __asmeq("%8", "x4")
> >+ __asmeq("%9", "x5")
>
> And then another asmeq thing here for x6.
>
> >+#ifdef REQUIRES_SEC
> >+ ".arch_extension sec\n"
> >+#endif
> >+ "smc #0\n"
> >+ : "=r" (r0), "=r" (r1), "=r" (r2), "=r" (r3)
> >+ : "r" (r0), "r" (r1), "r" (r2), "r" (r3), "r" (r4),
> >+ "r" (r5)
>
> And then add r6 here as an input
>
> >+ : "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13",
>
> And remove r6 from the clobber.
>
> >+ "x14", "x15", "x16", "x17");
> >+
> >+ } while (r0 == QCOM_SCM_INTERRUPTED);
> >+
> >+ if (ret1)
> >+ *ret1 = r1;
> >+ if (ret2)
> >+ *ret2 = r2;
> >+ if (ret3)
> >+ *ret3 = r3;
> >+
> >+ return r0;
> >+}
> >+
> >
>
> Here's a totally untested patch for that.
>
> Signed-off-by: Stephen Boyd <[email protected]>
> ----8<-----
>
> diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-64.c
> index a95fd9b5d576..8f7e65ff524c 100644
> --- a/drivers/firmware/qcom_scm-64.c
> +++ b/drivers/firmware/qcom_scm-64.c
> @@ -114,6 +114,7 @@ int __qcom_scm_call_armv8_64(u64 x0, u64 x1, u64 x2, u64 x3, u64 x4, u64 x5,
> register u64 r3 asm("r3") = x3;
> register u64 r4 asm("r4") = x4;
> register u64 r5 asm("r5") = x5;
> + register u64 r6 asm("r5") = 0;
> do {
> asm volatile(
> @@ -127,14 +128,15 @@ int __qcom_scm_call_armv8_64(u64 x0, u64 x1, u64 x2, u64 x3, u64 x4, u64 x5,
> __asmeq("%7", "x3")
> __asmeq("%8", "x4")
> __asmeq("%9", "x5")
> + __asmeq("%10", "x6")
> #ifdef REQUIRES_SEC
> ".arch_extension sec\n"
> #endif
> "smc #0\n"
> : "=r" (r0), "=r" (r1), "=r" (r2), "=r" (r3)
> : "r" (r0), "r" (r1), "r" (r2), "r" (r3), "r" (r4),
> - "r" (r5)
> - : "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13",
> + "r" (r5), "r" (r6)
> + : "x7", "x8", "x9", "x10", "x11", "x12", "x13",
> "x14", "x15", "x16", "x17");
> } while (r0 == QCOM_SCM_INTERRUPTED);
> @@ -157,6 +159,7 @@ int __qcom_scm_call_armv8_32(u32 w0, u32 w1, u32 w2, u32 w3, u32 w4, u32 w5,
> register u32 r3 asm("r3") = w3;
> register u32 r4 asm("r4") = w4;
> register u32 r5 asm("r5") = w5;
> + register u32 r6 asm("r6") = 0;
> do {
> asm volatile(
> @@ -170,14 +173,15 @@ int __qcom_scm_call_armv8_32(u32 w0, u32 w1, u32 w2, u32 w3, u32 w4, u32 w5,
> __asmeq("%7", "x3")
> __asmeq("%8", "x4")
> __asmeq("%9", "x5")
> + __asmeq("%10", "x6")
> #ifdef REQUIRES_SEC
> ".arch_extension sec\n"
> #endif
> "smc #0\n"
> : "=r" (r0), "=r" (r1), "=r" (r2), "=r" (r3)
> : "r" (r0), "r" (r1), "r" (r2), "r" (r3), "r" (r4),
> - "r" (r5)
> - : "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13",
> + "r" (r5), "r" (r6)
> + : "x7", "x8", "x9", "x10", "x11", "x12", "x13",
> "x14", "x15", "x16", "x17");
> } while (r0 == QCOM_SCM_INTERRUPTED);
>
> --
Stephen, I'll incorporate this in the next version. Thanks!
--
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