These patches have all been on the list for some time now.
I've taken the liberty of collecting them all up to send
as a single batch.
Lee Jones (13):
ARM: STi: STiH407: Add DT nodes for for PWM
ARM: STi: STiH416: Add Pinctrl settings for PWM
ARM: STi: STiH416: Add DT nodes for PWM
ARM: STi: STiH416-b2020e: Enable PWM on the B2020 Rev-E
ARM: multi_v7_defconfig: Enable ST's PWM driver
ARM: STi: STiH407: Add Restart support for Cannes
ARM: STi: STiH416: Add Restart support for Orly2
ARM: multi_v7_defconfig: Enable ST's Power Reset driver
ARM: STi: STiH416: Enable Cortex-A9 PMU support
ARM: STi: STiH416: Enable PMU IRQs
ARM: STi: STiH407: Enable Cortex-A9 PMU support
ARM: STi: STiH407: Enable PMU IRQs
ARM: STi: Ensure requested STi's SysCfg Controlled IRQs are enabled at
boot
arch/arm/boot/dts/stih407-family.dtsi | 22 ++++++++++++
arch/arm/boot/dts/stih407.dtsi | 28 +++++++++++++++
arch/arm/boot/dts/stih416-b2020e.dts | 10 ++++++
arch/arm/boot/dts/stih416-pinctrl.dtsi | 50 ++++++++++++++++++++++++++
arch/arm/boot/dts/stih416.dtsi | 66 +++++++++++++++++++++++++++++++++-
arch/arm/configs/multi_v7_defconfig | 2 ++
arch/arm/mach-sti/Kconfig | 1 +
7 files changed, 178 insertions(+), 1 deletion(-)
--
1.9.1
Supply top level nodes for the STiH407 based development boards.
The Pinctrl configuration has already been applied, so the only
missing piece of the DT puzzle is for a board's DTB to enable
the nodes.
Signed-off-by: Ajit Pal Singh <[email protected]>
Signed-off-by: Lee Jones <[email protected]>
---
arch/arm/boot/dts/stih407.dtsi | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/arm/boot/dts/stih407.dtsi b/arch/arm/boot/dts/stih407.dtsi
index 3efa3b2..2c560fc3 100644
--- a/arch/arm/boot/dts/stih407.dtsi
+++ b/arch/arm/boot/dts/stih407.dtsi
@@ -147,5 +147,33 @@
};
};
};
+
+ /* COMMS PWM Module */
+ pwm0: pwm@9810000 {
+ compatible = "st,sti-pwm";
+ status = "disabled";
+ #pwm-cells = <2>;
+ reg = <0x9810000 0x68>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm0_chan0_default>;
+ clock-names = "pwm";
+ clocks = <&clk_sysin>;
+ };
+
+ /* SBC PWM Module */
+ pwm1: pwm@9510000 {
+ compatible = "st,sti-pwm";
+ status = "disabled";
+ #pwm-cells = <2>;
+ reg = <0x9510000 0x68>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm1_chan0_default
+ &pinctrl_pwm1_chan1_default
+ &pinctrl_pwm1_chan2_default
+ &pinctrl_pwm1_chan3_default>;
+ clock-names = "pwm";
+ clocks = <&clk_sysin>;
+ st,pwm-num-chan = <4>;
+ };
};
};
--
1.9.1
Supply the Pinctrl configuration to enable PWM{0,1} lines on STiH416
based development boards.
Signed-off-by: Ajit Pal Singh <[email protected]>
Signed-off-by: Lee Jones <[email protected]>
---
arch/arm/boot/dts/stih416-pinctrl.dtsi | 50 ++++++++++++++++++++++++++++++++++
1 file changed, 50 insertions(+)
diff --git a/arch/arm/boot/dts/stih416-pinctrl.dtsi b/arch/arm/boot/dts/stih416-pinctrl.dtsi
index 9cccf2d..051fc16 100644
--- a/arch/arm/boot/dts/stih416-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih416-pinctrl.dtsi
@@ -216,6 +216,29 @@
};
};
};
+
+ pwm1 {
+ pinctrl_pwm1_chan0_default: pwm1-0-default {
+ st,pins {
+ pwm-out = <&pio3 0 ALT1 OUT>;
+ };
+ };
+ pinctrl_pwm1_chan1_default: pwm1-1-default {
+ st,pins {
+ pwm-out = <&pio4 4 ALT1 OUT>;
+ };
+ };
+ pinctrl_pwm1_chan2_default: pwm1-2-default {
+ st,pins {
+ pwm-out = <&pio4 6 ALT3 OUT>;
+ };
+ };
+ pinctrl_pwm1_chan3_default: pwm1-3-default {
+ st,pins {
+ pwm-out = <&pio4 7 ALT3 OUT>;
+ };
+ };
+ };
};
pin-controller-front {
@@ -310,6 +333,14 @@
st,bank-name = "PIO31";
};
+ pwm0 {
+ pinctrl_pwm0_chan0_default: pwm0-0-default {
+ st,pins {
+ pwm-out = <&pio9 7 ALT2 OUT>;
+ };
+ };
+ };
+
serial2-oe {
pinctrl_serial2_oe: serial2-1 {
st,pins {
@@ -540,6 +571,25 @@
};
};
};
+
+ pwm0 {
+ pinctrl_pwm0_chan1_default: pwm0-1-default {
+ st,pins {
+ pwm-out = <&pio13 2 ALT2 OUT>;
+ };
+ };
+ pinctrl_pwm0_chan2_default: pwm0-2-default {
+ st,pins {
+ pwm-out = <&pio15 2 ALT4 OUT>;
+ };
+ };
+ pinctrl_pwm0_chan3_default: pwm0-3-default {
+ st,pins {
+ pwm-out = <&pio17 4 ALT1 OUT>;
+ };
+ };
+ };
+
};
pin-controller-fvdp-fe {
--
1.9.1
Supply top level nodes for the STiH416 based development boards.
The Pinctrl configuration has already been applied, so the only
missing piece of the DT puzzle is for a board's DTB to enable
the nodes.
Signed-off-by: Ajit Pal Singh <[email protected]>
Signed-off-by: Lee Jones <[email protected]>
---
arch/arm/boot/dts/stih416.dtsi | 44 +++++++++++++++++++++++++++++++++++++++++-
1 file changed, 43 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
index eeb7afe..9ead8bb 100644
--- a/arch/arm/boot/dts/stih416.dtsi
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -104,7 +104,7 @@
interrupts = <0 210 0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sbc_serial1>;
- clocks = <&clk_sysin>;
+ clocks = <&clk_sysin>;
};
i2c@fed40000 {
@@ -445,5 +445,47 @@
<&softreset STIH416_USB3_SOFTRESET>;
reset-names = "power", "softreset";
};
+
+ /* SAS PWM Module */
+ pwm0: pwm@fed10000 {
+ compatible = "st,sti-pwm";
+ status = "disabled";
+ #pwm-cells = <2>;
+ reg = <0xfed10000 0x68>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm0_chan0_default
+ &pinctrl_pwm0_chan1_default
+ &pinctrl_pwm0_chan2_default
+ &pinctrl_pwm0_chan3_default>;
+
+ clock-names = "pwm";
+ clocks = <&clk_sysin>;
+ st,pwm-num-chan = <4>;
+ };
+
+ /* SBC PWM Module */
+ pwm1: pwm@fe510000 {
+ compatible = "st,sti-pwm";
+ status = "disabled";
+ #pwm-cells = <2>;
+ reg = <0xfe510000 0x68>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm1_chan0_default
+ /*
+ * Shared with SBC_OBS_NOTRST. Don't
+ * enable unless you really know what
+ * you're doing.
+ *
+ * &pinctrl_pwm1_chan1_default
+ */
+ &pinctrl_pwm1_chan2_default
+ &pinctrl_pwm1_chan3_default>;
+
+ clock-names = "pwm";
+ clocks = <&clk_sysin>;
+ st,pwm-num-chan = <3>;
+ };
};
};
--
1.9.1
All the infrastructure is now in place for ST's PWM controller. This
patch takes the final step and enables the IP on the 2020 Rev-E
development platform.
Signed-off-by: Ajit Pal Singh <[email protected]>
Signed-off-by: Lee Jones <[email protected]>
---
arch/arm/boot/dts/stih416-b2020e.dts | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/stih416-b2020e.dts b/arch/arm/boot/dts/stih416-b2020e.dts
index 961799e..f1ceee1 100644
--- a/arch/arm/boot/dts/stih416-b2020e.dts
+++ b/arch/arm/boot/dts/stih416-b2020e.dts
@@ -51,5 +51,15 @@
sata0: sata@fe380000{
status = "okay";
};
+
+ /* SAS PWM Module */
+ pwm0: pwm@fed10000 {
+ status = "okay";
+ };
+
+ /* SBC PWM Module */
+ pwm1: pwm@fe510000 {
+ status = "okay";
+ };
};
};
--
1.9.1
Signed-off-by: Lee Jones <[email protected]>
---
arch/arm/configs/multi_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index a841847..5dc85db 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -556,6 +556,7 @@ CONFIG_PWM_RENESAS_TPU=y
CONFIG_PWM_TEGRA=y
CONFIG_PWM_VT8500=y
CONFIG_PHY_HIX5HD2_SATA=y
+CONFIG_PWM_STI=y
CONFIG_OMAP_USB2=y
CONFIG_TI_PIPE3=y
CONFIG_PHY_MIPHY28LP=y
--
1.9.1
Signed-off-by: Lee Jones <[email protected]>
---
arch/arm/boot/dts/stih407-family.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi
index 85159b8..46e6a38 100644
--- a/arch/arm/boot/dts/stih407-family.dtsi
+++ b/arch/arm/boot/dts/stih407-family.dtsi
@@ -65,6 +65,12 @@
ranges;
compatible = "simple-bus";
+ restart {
+ compatible = "st,stih407-restart";
+ st,syscfg = <&syscfg_sbc_reg>;
+ status = "okay";
+ };
+
powerdown: powerdown-controller {
compatible = "st,stih407-powerdown";
#reset-cells = <1>;
--
1.9.1
Signed-off-by: Lee Jones <[email protected]>
---
arch/arm/boot/dts/stih416.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
index 9ead8bb..6452d33 100644
--- a/arch/arm/boot/dts/stih416.dtsi
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -30,6 +30,12 @@
ranges;
compatible = "simple-bus";
+ restart {
+ compatible = "st,stih416-restart";
+ st,syscfg = <&syscfg_sbc>;
+ status = "okay";
+ };
+
powerdown: powerdown-controller {
#reset-cells = <1>;
compatible = "st,stih416-powerdown";
--
1.9.1
Signed-off-by: Lee Jones <[email protected]>
---
arch/arm/configs/multi_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 5dc85db..f632af0 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -321,6 +321,7 @@ CONFIG_POWER_RESET_GPIO_RESTART=y
CONFIG_POWER_RESET_KEYSTONE=y
CONFIG_POWER_RESET_SUN6I=y
CONFIG_POWER_RESET_RMOBILE=y
+CONFIG_POWER_RESET_ST=y
CONFIG_SENSORS_LM90=y
CONFIG_SENSORS_LM95245=y
CONFIG_THERMAL=y
--
1.9.1
This is ARM's generic Performance Monitoring Unit.
Signed-off-by: Lee Jones <[email protected]>
---
arch/arm/boot/dts/stih416.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
index 6452d33..cc5b78d 100644
--- a/arch/arm/boot/dts/stih416.dtsi
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -23,6 +23,12 @@
cache-level = <2>;
};
+ arm-pmu {
+ compatible = "arm,cortex-a9-pmu";
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
soc {
#address-cells = <1>;
#size-cells = <1>;
--
1.9.1
This driver is used to enable System Configuration Register controlled
External, CTI (Core Sight), PMU (Performance Management), and PL310 L2
Cache IRQs prior to use.
Here we are enabling PMU IRQs on both channels.
Signed-off-by: Lee Jones <[email protected]>
---
arch/arm/boot/dts/stih416.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
index cc5b78d..9dca173 100644
--- a/arch/arm/boot/dts/stih416.dtsi
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -13,6 +13,7 @@
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset-controller/stih416-resets.h>
+#include <dt-bindings/interrupt-controller/irq-st.h>
/ {
L2: cache-controller {
compatible = "arm,pl310-cache";
@@ -98,6 +99,15 @@
reg = <0xfe4b5100 0x8>;
};
+ irq-syscfg {
+ compatible = "st,stih416-irq-syscfg";
+ st,syscfg = <&syscfg_cpu>;
+ st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
+ <ST_IRQ_SYSCFG_PMU_1>;
+ st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,
+ <ST_IRQ_SYSCFG_DISABLED>;
+ };
+
serial2: serial@fed32000{
compatible = "st,asc";
status = "disabled";
--
1.9.1
This is ARM's generic Performance Monitoring Unit.
Signed-off-by: Lee Jones <[email protected]>
---
arch/arm/boot/dts/stih407-family.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi
index 46e6a38..412206e 100644
--- a/arch/arm/boot/dts/stih407-family.dtsi
+++ b/arch/arm/boot/dts/stih407-family.dtsi
@@ -58,6 +58,12 @@
cache-level = <2>;
};
+ arm-pmu {
+ interrupt-parent = <&intc>;
+ compatible = "arm,cortex-a9-pmu";
+ interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
soc {
#address-cells = <1>;
#size-cells = <1>;
--
1.9.1
This driver is used to enable System Configuration Register controlled
External, CTI (Core Sight), PMU (Performance Management), and PL310 L2
Cache IRQs prior to use.
Here we are enabling PMU IRQs on both channels.
Signed-off-by: Lee Jones <[email protected]>
---
arch/arm/boot/dts/stih407-family.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi
index 412206e..e096105 100644
--- a/arch/arm/boot/dts/stih407-family.dtsi
+++ b/arch/arm/boot/dts/stih407-family.dtsi
@@ -10,6 +10,7 @@
#include <dt-bindings/mfd/st-lpc.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/reset-controller/stih407-resets.h>
+#include <dt-bindings/interrupt-controller/irq-st.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
@@ -127,6 +128,15 @@
reg = <0x94b5100 0x1000>;
};
+ irq-syscfg {
+ compatible = "st,stih407-irq-syscfg";
+ st,syscfg = <&syscfg_core>;
+ st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
+ <ST_IRQ_SYSCFG_PMU_1>;
+ st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,
+ <ST_IRQ_SYSCFG_DISABLED>;
+ };
+
serial@9830000 {
compatible = "st,asc";
reg = <0x9830000 0x2c>;
--
1.9.1
This driver is used to enable System Configuration Register controlled
External, CTI (Core Sight), PMU (Performance Management), and PL310 L2
Cache IRQs prior to use.
Signed-off-by: Lee Jones <[email protected]>
---
arch/arm/mach-sti/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-sti/Kconfig b/arch/arm/mach-sti/Kconfig
index 3b1ac46..125865d 100644
--- a/arch/arm/mach-sti/Kconfig
+++ b/arch/arm/mach-sti/Kconfig
@@ -1,6 +1,7 @@
menuconfig ARCH_STI
bool "STMicroelectronics Consumer Electronics SOCs" if ARCH_MULTI_V7
select ARM_GIC
+ select ST_IRQCHIP
select ARM_GLOBAL_TIMER
select PINCTRL
select PINCTRL_ST
--
1.9.1
Hi Lee,
On 05/12/2015 02:51 PM, Lee Jones wrote:
> These patches have all been on the list for some time now.
> I've taken the liberty of collecting them all up to send
> as a single batch.
>
> Lee Jones (13):
> ARM: STi: STiH407: Add DT nodes for for PWM
> ARM: STi: STiH416: Add Pinctrl settings for PWM
> ARM: STi: STiH416: Add DT nodes for PWM
> ARM: STi: STiH416-b2020e: Enable PWM on the B2020 Rev-E
> ARM: multi_v7_defconfig: Enable ST's PWM driver
> ARM: STi: STiH407: Add Restart support for Cannes
> ARM: STi: STiH416: Add Restart support for Orly2
> ARM: multi_v7_defconfig: Enable ST's Power Reset driver
> ARM: STi: STiH416: Enable Cortex-A9 PMU support
> ARM: STi: STiH416: Enable PMU IRQs
> ARM: STi: STiH407: Enable Cortex-A9 PMU support
> ARM: STi: STiH407: Enable PMU IRQs
> ARM: STi: Ensure requested STi's SysCfg Controlled IRQs are enabled at
> boot
>
> arch/arm/boot/dts/stih407-family.dtsi | 22 ++++++++++++
> arch/arm/boot/dts/stih407.dtsi | 28 +++++++++++++++
> arch/arm/boot/dts/stih416-b2020e.dts | 10 ++++++
> arch/arm/boot/dts/stih416-pinctrl.dtsi | 50 ++++++++++++++++++++++++++
> arch/arm/boot/dts/stih416.dtsi | 66 +++++++++++++++++++++++++++++++++-
> arch/arm/configs/multi_v7_defconfig | 2 ++
> arch/arm/mach-sti/Kconfig | 1 +
> 7 files changed, 178 insertions(+), 1 deletion(-)
>
Series applied.
Note that I fixed patches 6 & 7 titles to use commercial product names.
Thanks!
Maxime