This series begins converting the MIPS Malta board to use device tree,
which is done with a few goals in mind:
- To modernise the Malta board support, providing a cleaner example to
people referencing it when bringing up new boards and reducing the
amount of code they need to write.
- To make the code at the board level more generic with the eventual
aim of sharing it between multiple boards & allowing for
multi-platform kernel binaries. Although this series doesn't result
in the kernel reaching those goals, it is a step in that direction.
- To result in a more maintainable kernel through a combination of the
above.
Paul Burton (15):
MIPS: define GCR_GIC_STATUS register fields
MIPS: include errno.h for ENODEV in mips-cm.h
MIPS: malta: basic DT plumbing
MIPS: i8259: DT support
irqchip: mips-gic: register IRQ domain with MIPS_GIC_IRQ_BASE
MIPS: malta: probe interrupt controllers via DT
MIPS: remove [SR]ocIt(2) IRQ handling code
of_serial: support for UARTs on I/O ports
MIPS: malta: probe UARTs using DT
MIPS: malta: probe RTC via DT
MIPS: malta: probe pflash via DT
MIPS: malta: remove fw_memblock_t abstraction
MIPS: malta: remove nonsense memory limit
MIPS: malta: setup RAM regions via DT
MIPS: malta: setup post-I/O hole RAM on non-EVA
arch/mips/Kconfig | 3 +
arch/mips/boot/dts/mti/Makefile | 1 +
arch/mips/boot/dts/mti/malta.dts | 150 +++++++++++++++
arch/mips/configs/malta_defconfig | 3 +-
arch/mips/configs/malta_kvm_defconfig | 3 +-
arch/mips/configs/malta_kvm_guest_defconfig | 3 +-
arch/mips/configs/malta_qemu_32r6_defconfig | 1 +
arch/mips/configs/maltaaprp_defconfig | 1 +
arch/mips/configs/maltasmvp_defconfig | 1 +
arch/mips/configs/maltasmvp_eva_defconfig | 1 +
arch/mips/configs/maltaup_defconfig | 1 +
arch/mips/configs/maltaup_xpa_defconfig | 3 +-
arch/mips/include/asm/fw/fw.h | 16 --
arch/mips/include/asm/i8259.h | 1 +
arch/mips/include/asm/mach-malta/malta-dtshim.h | 29 +++
arch/mips/include/asm/mips-cm.h | 5 +
arch/mips/include/asm/msc01_ic.h | 147 ---------------
arch/mips/kernel/Makefile | 1 -
arch/mips/kernel/i8259.c | 43 ++++-
arch/mips/kernel/irq-msc01.c | 159 ----------------
arch/mips/mti-malta/Makefile | 6 +-
arch/mips/mti-malta/malta-dt.c | 34 ++++
arch/mips/mti-malta/malta-dtshim.c | 238 ++++++++++++++++++++++++
arch/mips/mti-malta/malta-int.c | 130 +------------
arch/mips/mti-malta/malta-memory.c | 131 +------------
arch/mips/mti-malta/malta-platform.c | 147 ---------------
arch/mips/mti-malta/malta-setup.c | 7 +
arch/mips/mti-malta/malta-time.c | 1 -
drivers/irqchip/irq-mips-gic.c | 2 +-
drivers/tty/serial/of_serial.c | 7 +-
30 files changed, 542 insertions(+), 733 deletions(-)
create mode 100644 arch/mips/boot/dts/mti/malta.dts
create mode 100644 arch/mips/include/asm/mach-malta/malta-dtshim.h
delete mode 100644 arch/mips/include/asm/msc01_ic.h
delete mode 100644 arch/mips/kernel/irq-msc01.c
create mode 100644 arch/mips/mti-malta/malta-dt.c
create mode 100644 arch/mips/mti-malta/malta-dtshim.c
delete mode 100644 arch/mips/mti-malta/malta-platform.c
--
2.4.1
Add definitions for the GICEX field in the GCR_GIC_STATUS register to
mips-cm.h for use in a later patch.
Signed-off-by: Paul Burton <[email protected]>
---
arch/mips/include/asm/mips-cm.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/mips-cm.h
index 59c0901..1cb11fb 100644
--- a/arch/mips/include/asm/mips-cm.h
+++ b/arch/mips/include/asm/mips-cm.h
@@ -216,6 +216,10 @@ BUILD_CM_Cx_R_(tcid_8_priority, 0x80)
#define CM_GCR_CPC_BASE_CPCEN_SHF 0
#define CM_GCR_CPC_BASE_CPCEN_MSK (_ULCAST_(0x1) << 0)
+/* GCR_GIC_STATUS register fields */
+#define CM_GCR_GIC_STATUS_GICEX_SHF 0
+#define CM_GCR_GIC_STATUS_GICEX_MSK (_ULCAST_(0x1) << 0)
+
/* GCR_REGn_BASE register fields */
#define CM_GCR_REGn_BASE_BASEADDR_SHF 16
#define CM_GCR_REGn_BASE_BASEADDR_MSK (_ULCAST_(0xffff) << 16)
--
2.4.1
A later patch in this series will include mips-cm.h but does not require
errno.h. This leads to a build failure with ENODEV undeclared. Include
errno.h from mips-cm.h to pull in the appropriate definition and avoid
the build failure.
Signed-off-by: Paul Burton <[email protected]>
---
arch/mips/include/asm/mips-cm.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/mips-cm.h
index 1cb11fb..edc7ee9 100644
--- a/arch/mips/include/asm/mips-cm.h
+++ b/arch/mips/include/asm/mips-cm.h
@@ -11,6 +11,7 @@
#ifndef __MIPS_ASM_MIPS_CM_H__
#define __MIPS_ASM_MIPS_CM_H__
+#include <linux/errno.h>
#include <linux/io.h>
#include <linux/types.h>
--
2.4.1
Build a DT for the Malta platform into the kernel, load it & probe
devices from it. The DT is essentially empty at this point, devices
will be added in further patches.
Signed-off-by: Paul Burton <[email protected]>
---
arch/mips/Kconfig | 2 ++
arch/mips/boot/dts/mti/Makefile | 1 +
arch/mips/boot/dts/mti/malta.dts | 7 +++++++
arch/mips/mti-malta/Makefile | 2 +-
arch/mips/mti-malta/malta-dt.c | 34 ++++++++++++++++++++++++++++++++++
arch/mips/mti-malta/malta-setup.c | 4 ++++
6 files changed, 49 insertions(+), 1 deletion(-)
create mode 100644 arch/mips/boot/dts/mti/malta.dts
create mode 100644 arch/mips/mti-malta/malta-dt.c
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index f501665..75dd13d 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -434,6 +434,8 @@ config MIPS_MALTA
select SYS_SUPPORTS_MULTITHREADING
select SYS_SUPPORTS_SMARTMIPS
select SYS_SUPPORTS_ZBOOT
+ select USE_OF
+ select BUILTIN_DTB
help
This enables support for the MIPS Technologies Malta evaluation
board.
diff --git a/arch/mips/boot/dts/mti/Makefile b/arch/mips/boot/dts/mti/Makefile
index ef1f3db..144d776 100644
--- a/arch/mips/boot/dts/mti/Makefile
+++ b/arch/mips/boot/dts/mti/Makefile
@@ -1,3 +1,4 @@
+dtb-$(CONFIG_MIPS_MALTA) += malta.dtb
dtb-$(CONFIG_MIPS_SEAD3) += sead3.dtb
obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
diff --git a/arch/mips/boot/dts/mti/malta.dts b/arch/mips/boot/dts/mti/malta.dts
new file mode 100644
index 0000000..c678115
--- /dev/null
+++ b/arch/mips/boot/dts/mti/malta.dts
@@ -0,0 +1,7 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "mti,malta";
+};
diff --git a/arch/mips/mti-malta/Makefile b/arch/mips/mti-malta/Makefile
index 6510ace..ea35587 100644
--- a/arch/mips/mti-malta/Makefile
+++ b/arch/mips/mti-malta/Makefile
@@ -5,7 +5,7 @@
# Copyright (C) 2008 Wind River Systems, Inc.
# written by Ralf Baechle <[email protected]>
#
-obj-y := malta-display.o malta-init.o \
+obj-y := malta-display.o malta-dt.o malta-init.o \
malta-int.o malta-memory.o malta-platform.o \
malta-reset.o malta-setup.o malta-time.o
diff --git a/arch/mips/mti-malta/malta-dt.c b/arch/mips/mti-malta/malta-dt.c
new file mode 100644
index 0000000..47a2288
--- /dev/null
+++ b/arch/mips/mti-malta/malta-dt.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2015 Imagination Technologies
+ * Author: Paul Burton <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/init.h>
+#include <linux/of_fdt.h>
+#include <linux/of_platform.h>
+
+void __init device_tree_init(void)
+{
+ unflatten_and_copy_device_tree();
+}
+
+static const struct of_device_id bus_ids[] __initconst = {
+ { .compatible = "simple-bus", },
+ { .compatible = "isa", },
+ {},
+};
+
+static int __init publish_devices(void)
+{
+ if (!of_have_populated_dt())
+ return 0;
+
+ return of_platform_bus_probe(NULL, bus_ids, NULL);
+}
+device_initcall(publish_devices);
diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c
index db7c9e5..9d1e7f5 100644
--- a/arch/mips/mti-malta/malta-setup.c
+++ b/arch/mips/mti-malta/malta-setup.c
@@ -21,6 +21,7 @@
#include <linux/sched.h>
#include <linux/ioport.h>
#include <linux/irq.h>
+#include <linux/of_fdt.h>
#include <linux/pci.h>
#include <linux/screen_info.h>
#include <linux/time.h>
@@ -31,6 +32,7 @@
#include <asm/mips-boards/malta.h>
#include <asm/mips-boards/maltaint.h>
#include <asm/dma.h>
+#include <asm/prom.h>
#include <asm/traps.h>
#ifdef CONFIG_VT
#include <linux/console.h>
@@ -249,6 +251,8 @@ void __init plat_mem_setup(void)
{
unsigned int i;
+ __dt_setup_arch(__dtb_start);
+
if (config_enabled(CONFIG_EVA))
/* EVA has already been configured in mach-malta/kernel-init.h */
pr_info("Enhanced Virtual Addressing (EVA) activated\n");
--
2.4.1
Support probing the i8259 programmable interrupt controller, as found on
the Malta board, and using its interrupts via device tree.
Signed-off-by: Paul Burton <[email protected]>
---
arch/mips/include/asm/i8259.h | 1 +
arch/mips/kernel/i8259.c | 43 +++++++++++++++++++++++++++++++++++++++++--
2 files changed, 42 insertions(+), 2 deletions(-)
diff --git a/arch/mips/include/asm/i8259.h b/arch/mips/include/asm/i8259.h
index c7e2784..a7fbcd6 100644
--- a/arch/mips/include/asm/i8259.h
+++ b/arch/mips/include/asm/i8259.h
@@ -41,6 +41,7 @@ extern int i8259A_irq_pending(unsigned int irq);
extern void make_8259A_irq(unsigned int irq);
extern void init_i8259_irqs(void);
+extern int i8259_of_init(struct device_node *node, struct device_node *parent);
/*
* Do the traditional i8259 interrupt polling thing. This is for the few
diff --git a/arch/mips/kernel/i8259.c b/arch/mips/kernel/i8259.c
index a74ec3a..74f6752 100644
--- a/arch/mips/kernel/i8259.c
+++ b/arch/mips/kernel/i8259.c
@@ -14,6 +14,7 @@
#include <linux/interrupt.h>
#include <linux/irqdomain.h>
#include <linux/kernel.h>
+#include <linux/of_irq.h>
#include <linux/spinlock.h>
#include <linux/syscore_ops.h>
#include <linux/irq.h>
@@ -21,6 +22,8 @@
#include <asm/i8259.h>
#include <asm/io.h>
+#include "../../drivers/irqchip/irqchip.h"
+
/*
* This is the 'legacy' 8259A Programmable Interrupt Controller,
* present in the majority of PC/AT boxes.
@@ -327,7 +330,7 @@ static struct irq_domain_ops i8259A_ops = {
* driver compatibility reasons interrupts 0 - 15 to be the i8259
* interrupts even if the hardware uses a different interrupt numbering.
*/
-void __init init_i8259_irqs(void)
+struct irq_domain * __init __init_i8259_irqs(struct device_node *node)
{
struct irq_domain *domain;
@@ -336,10 +339,46 @@ void __init init_i8259_irqs(void)
init_8259A(0);
- domain = irq_domain_add_legacy(NULL, 16, I8259A_IRQ_BASE, 0,
+ domain = irq_domain_add_legacy(node, 16, I8259A_IRQ_BASE, 0,
&i8259A_ops, NULL);
if (!domain)
panic("Failed to add i8259 IRQ domain");
setup_irq(I8259A_IRQ_BASE + PIC_CASCADE_IR, &irq2);
+ return domain;
+}
+
+void __init init_i8259_irqs(void)
+{
+ __init_i8259_irqs(NULL);
+}
+
+static void i8259_irq_dispatch(unsigned int irq, struct irq_desc *desc)
+{
+ struct irq_domain *domain = irq_get_handler_data(irq);
+ int hwirq = i8259_irq();
+
+ if (hwirq < 0)
+ return;
+
+ irq = irq_linear_revmap(domain, hwirq);
+ generic_handle_irq(irq);
+}
+
+int __init i8259_of_init(struct device_node *node, struct device_node *parent)
+{
+ struct irq_domain *domain;
+ unsigned int parent_irq;
+
+ parent_irq = irq_of_parse_and_map(node, 0);
+ if (!parent_irq) {
+ pr_err("Failed to map i8259 parent IRQ\n");
+ return -ENODEV;
+ }
+
+ domain = __init_i8259_irqs(node);
+ irq_set_handler_data(parent_irq, domain);
+ irq_set_chained_handler(parent_irq, i8259_irq_dispatch);
+ return 0;
}
+IRQCHIP_DECLARE(i8259, "intel,i8259", i8259_of_init);
--
2.4.1
On Malta, some IRQs are still referenced by hardcoded numbers relative
to MIPS_GIC_IRQ_BASE. When gic_init is called to register the GIC
without using device tree the irqbase argument allows this base to be
used. When the GIC is probed using device tree however the base is not
specified. This leads to conflicts between the GIC interrupts and other
interrupt controllers.
TODO: convert Malta (& SEAD3) to drop the hardcoded numbers instead
Signed-off-by: Paul Burton <[email protected]>
---
drivers/irqchip/irq-mips-gic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
index 57f09cb..697f340 100644
--- a/drivers/irqchip/irq-mips-gic.c
+++ b/drivers/irqchip/irq-mips-gic.c
@@ -858,7 +858,7 @@ static int __init gic_of_init(struct device_node *node,
write_gcr_gic_base(gic_base | CM_GCR_GIC_BASE_GICEN_MSK);
gic_present = true;
- __gic_init(gic_base, gic_len, cpu_vec, 0, node);
+ __gic_init(gic_base, gic_len, cpu_vec, MIPS_GIC_IRQ_BASE, node);
return 0;
}
--
2.4.1
Probe the CPU, GIC & i8259 interrupt controllers present in the Malta
system using device tree. This enables interrupts to be provided to
devices using device tree as they are moved over to being probed using
it.
Since Malta is very configurable it's unknown whether a GIC will be
present at compile time. In order to support both cases the
malta_dt_shim code is added in order to detect whether a GIC is present,
adjusting the DT to route interrupts correctly and nop out the GIC node
if no GIC is found.
Signed-off-by: Paul Burton <[email protected]>
---
arch/mips/Kconfig | 1 +
arch/mips/boot/dts/mti/malta.dts | 55 ++++++++++
arch/mips/include/asm/mach-malta/malta-dtshim.h | 29 ++++++
arch/mips/mti-malta/Makefile | 4 +-
arch/mips/mti-malta/malta-dtshim.c | 128 ++++++++++++++++++++++++
arch/mips/mti-malta/malta-int.c | 77 ++------------
arch/mips/mti-malta/malta-setup.c | 5 +-
7 files changed, 227 insertions(+), 72 deletions(-)
create mode 100644 arch/mips/include/asm/mach-malta/malta-dtshim.h
create mode 100644 arch/mips/mti-malta/malta-dtshim.c
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 75dd13d..76cabdb 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -435,6 +435,7 @@ config MIPS_MALTA
select SYS_SUPPORTS_SMARTMIPS
select SYS_SUPPORTS_ZBOOT
select USE_OF
+ select LIBFDT
select BUILTIN_DTB
help
This enables support for the MIPS Technologies Malta evaluation
diff --git a/arch/mips/boot/dts/mti/malta.dts b/arch/mips/boot/dts/mti/malta.dts
index c678115..4bcdeb4 100644
--- a/arch/mips/boot/dts/mti/malta.dts
+++ b/arch/mips/boot/dts/mti/malta.dts
@@ -1,7 +1,62 @@
/dts-v1/;
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/mips-gic.h>
+
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "mti,malta";
+
+ corecard {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <>;
+
+ cpu_intc: interrupt-controller {
+ compatible = "mti,cpu-interrupt-controller";
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gic: interrupt-controller@1bdc0000 {
+ compatible = "mti,gic";
+ reg = <0x1bdc0000 0x20000>;
+
+ interrupt-controller;
+ #interrupt-cells = <3>;
+
+ /*
+ * Declare the interrupt-parent even though the mti,gic
+ * binding doesn't require it, such that the kernel can
+ * figure out that cpu_intc is the root interrupt
+ * controller & should be probed first.
+ */
+ interrupt-parent = <&cpu_intc>;
+
+ timer {
+ compatible = "mti,gic-timer";
+ interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
+ };
+ };
+ };
+
+ board {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <>;
+
+ i8259: interrupt-controller@20 {
+ compatible = "intel,i8259";
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
};
diff --git a/arch/mips/include/asm/mach-malta/malta-dtshim.h b/arch/mips/include/asm/mach-malta/malta-dtshim.h
new file mode 100644
index 0000000..cfd7776
--- /dev/null
+++ b/arch/mips/include/asm/mach-malta/malta-dtshim.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2015 Imagination Technologies
+ * Author: Paul Burton <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __MIPS_MALTA_DTSHIM_H__
+#define __MIPS_MALTA_DTSHIM_H__
+
+#include <linux/init.h>
+
+#ifdef CONFIG_MIPS_MALTA
+
+extern void __init *malta_dt_shim(void *fdt);
+
+#else /* !CONFIG_MIPS_MALTA */
+
+static inline void *malta_dt_shim(void *fdt)
+{
+ return fdt;
+}
+
+#endif /* !CONFIG_MIPS_MALTA */
+
+#endif /* __MIPS_MALTA_DTSHIM_H__ */
diff --git a/arch/mips/mti-malta/Makefile b/arch/mips/mti-malta/Makefile
index ea35587..1d633fe 100644
--- a/arch/mips/mti-malta/Makefile
+++ b/arch/mips/mti-malta/Makefile
@@ -5,9 +5,11 @@
# Copyright (C) 2008 Wind River Systems, Inc.
# written by Ralf Baechle <[email protected]>
#
-obj-y := malta-display.o malta-dt.o malta-init.o \
+obj-y := malta-display.o malta-dt.o malta-dtshim.o malta-init.o \
malta-int.o malta-memory.o malta-platform.o \
malta-reset.o malta-setup.o malta-time.o
obj-$(CONFIG_MIPS_CMP) += malta-amon.o
obj-$(CONFIG_MIPS_MALTA_PM) += malta-pm.o
+
+CFLAGS_malta-dtshim.o = -I$(src)/../../../scripts/dtc/libfdt
diff --git a/arch/mips/mti-malta/malta-dtshim.c b/arch/mips/mti-malta/malta-dtshim.c
new file mode 100644
index 0000000..ca33201
--- /dev/null
+++ b/arch/mips/mti-malta/malta-dtshim.c
@@ -0,0 +1,128 @@
+/*
+ * Copyright (C) 2015 Imagination Technologies
+ * Author: Paul Burton <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/bug.h>
+#include <linux/kernel.h>
+#include <linux/libfdt.h>
+#include <linux/of_fdt.h>
+#include <asm/bootinfo.h>
+#include <asm/fw/fw.h>
+#include <asm/mips-boards/generic.h>
+#include <asm/mips-boards/malta.h>
+#include <asm/mips-cm.h>
+
+static unsigned char fdt_buf[16 << 10] __initdata;
+
+static void __init remove_gic(void *fdt)
+{
+ int err, gic_off, i8259_off, cpu_off;
+ void __iomem *biu_base;
+ uint32_t cpu_phandle, sc_cfg;
+
+ /* if we have a CM which reports a GIC is present, leave the DT alone */
+ err = mips_cm_probe();
+ if (!err && (read_gcr_gic_status() & CM_GCR_GIC_STATUS_GICEX_MSK))
+ return;
+
+ if (MIPS_REVISION_SCONID == MIPS_REVISION_SCON_ROCIT) {
+ /*
+ * On systems using the RocIT system controller a GIC may be
+ * present without a CM. Detect whether that is the case.
+ */
+ biu_base = ioremap_nocache(MSC01_BIU_REG_BASE,
+ MSC01_BIU_ADDRSPACE_SZ);
+ sc_cfg = __raw_readl(biu_base + MSC01_SC_CFG_OFS);
+ if (sc_cfg & MSC01_SC_CFG_GICPRES_MSK) {
+ /* enable the GIC at the system controller level */
+ sc_cfg |= BIT(MSC01_SC_CFG_GICENA_SHF);
+ __raw_writel(sc_cfg, biu_base + MSC01_SC_CFG_OFS);
+ return;
+ }
+ }
+
+ gic_off = fdt_node_offset_by_compatible(fdt, -1, "mti,gic");
+ if (gic_off < 0) {
+ pr_warn("malta-dtshim: unable to find DT GIC node: %d\n",
+ gic_off);
+ return;
+ }
+
+ err = fdt_nop_node(fdt, gic_off);
+ if (err)
+ pr_warn("malta-dtshim: unable to nop GIC node\n");
+
+ i8259_off = fdt_node_offset_by_compatible(fdt, -1, "intel,i8259");
+ if (i8259_off < 0) {
+ pr_warn("malta-dtshim: unable to find DT i8259 node: %d\n",
+ i8259_off);
+ return;
+ }
+
+ cpu_off = fdt_node_offset_by_compatible(fdt, -1,
+ "mti,cpu-interrupt-controller");
+ if (cpu_off < 0) {
+ pr_warn("malta-dtshim: unable to find CPU intc node: %d\n",
+ cpu_off);
+ return;
+ }
+
+ cpu_phandle = fdt_get_phandle(fdt, cpu_off);
+ if (!cpu_phandle) {
+ pr_warn("malta-dtshim: unable to get CPU intc phandle\n");
+ return;
+ }
+
+ err = fdt_setprop_u32(fdt, i8259_off, "interrupt-parent", cpu_phandle);
+ if (err) {
+ pr_warn("malta-dtshim: unable to set i8259 interrupt-parent: %d\n",
+ err);
+ return;
+ }
+
+ err = fdt_setprop_u32(fdt, i8259_off, "interrupts", 2);
+ if (err) {
+ pr_warn("malta-dtshim: unable to set i8259 interrupts: %d\n",
+ err);
+ return;
+ }
+}
+
+void __init *malta_dt_shim(void *fdt)
+{
+ int root_off, len, err;
+ const char *compat;
+
+ if (fdt_check_header(fdt))
+ panic("Corrupt DT");
+
+ err = fdt_open_into(fdt, fdt_buf, sizeof(fdt_buf));
+ if (err)
+ panic("Unable to open FDT: %d", err);
+
+ root_off = fdt_path_offset(fdt_buf, "/");
+ if (root_off < 0)
+ panic("No / node in DT");
+
+ compat = fdt_getprop(fdt_buf, root_off, "compatible", &len);
+ if (!compat)
+ panic("No root compatible property in DT: %d", len);
+
+ /* if this isn't Malta, leave the DT alone */
+ if (strncmp(compat, "mti,malta", len))
+ return fdt;
+
+ remove_gic(fdt_buf);
+
+ err = fdt_pack(fdt_buf);
+ if (err)
+ panic("Unable to pack FDT: %d\n", err);
+
+ return fdt_buf;
+}
diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c
index d1392f8..3fe5c17 100644
--- a/arch/mips/mti-malta/malta-int.c
+++ b/arch/mips/mti-malta/malta-int.c
@@ -14,6 +14,7 @@
*/
#include <linux/init.h>
#include <linux/irq.h>
+#include <linux/irqchip.h>
#include <linux/sched.h>
#include <linux/smp.h>
#include <linux/interrupt.h>
@@ -21,6 +22,7 @@
#include <linux/irqchip/mips-gic.h>
#include <linux/kernel_stat.h>
#include <linux/kernel.h>
+#include <linux/of_irq.h>
#include <linux/random.h>
#include <asm/traps.h>
@@ -37,10 +39,11 @@
#include <asm/setup.h>
#include <asm/rtlx.h>
-static void __iomem *_msc01_biu_base;
-
static DEFINE_RAW_SPINLOCK(mips_irq_lock);
+OF_DECLARE_2(irqchip, mips_cpu_intc, "mti,cpu-interrupt-controller",
+ mips_cpu_irq_of_init);
+
static inline int mips_pcibios_iack(void)
{
int irq;
@@ -104,30 +107,6 @@ static inline int get_int(void)
return irq;
}
-static void malta_hw0_irqdispatch(void)
-{
- int irq;
-
- irq = get_int();
- if (irq < 0) {
- /* interrupt has already been cleared */
- return;
- }
-
- do_IRQ(MALTA_INT_BASE + irq);
-
-#ifdef CONFIG_MIPS_VPE_APSP_API_MT
- if (aprp_hook)
- aprp_hook();
-#endif
-}
-
-static irqreturn_t i8259_handler(int irq, void *dev_id)
-{
- malta_hw0_irqdispatch();
- return IRQ_HANDLED;
-}
-
static void corehi_irqdispatch(void)
{
unsigned int intedge, intsteer, pcicmd, pcibadaddr;
@@ -240,12 +219,6 @@ static struct irqaction irq_call = {
};
#endif /* CONFIG_MIPS_MT_SMP */
-static struct irqaction i8259irq = {
- .handler = i8259_handler,
- .name = "XT-PIC cascade",
- .flags = IRQF_NO_THREAD,
-};
-
static struct irqaction corehi_irqaction = {
.handler = corehi_handler,
.name = "CoreHi",
@@ -281,28 +254,9 @@ void __init arch_init_ipiirq(int irq, struct irqaction *action)
void __init arch_init_irq(void)
{
- int corehi_irq, i8259_irq;
-
- init_i8259_irqs();
+ int corehi_irq;
- if (!cpu_has_veic)
- mips_cpu_irq_init();
-
- if (mips_cm_present()) {
- write_gcr_gic_base(GIC_BASE_ADDR | CM_GCR_GIC_BASE_GICEN_MSK);
- gic_present = 1;
- } else {
- if (mips_revision_sconid == MIPS_REVISION_SCON_ROCIT) {
- _msc01_biu_base = ioremap_nocache(MSC01_BIU_REG_BASE,
- MSC01_BIU_ADDRSPACE_SZ);
- gic_present =
- (__raw_readl(_msc01_biu_base + MSC01_SC_CFG_OFS) &
- MSC01_SC_CFG_GICPRES_MSK) >>
- MSC01_SC_CFG_GICPRES_SHF;
- }
- }
- if (gic_present)
- pr_debug("GIC present\n");
+ irqchip_init();
switch (mips_revision_sconid) {
case MIPS_REVISION_SCON_SOCIT:
@@ -330,18 +284,6 @@ void __init arch_init_irq(void)
}
if (gic_present) {
- int i;
-
- gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, MIPSCPU_INT_GIC,
- MIPS_GIC_IRQ_BASE);
- if (!mips_cm_present()) {
- /* Enable the GIC */
- i = __raw_readl(_msc01_biu_base + MSC01_SC_CFG_OFS);
- __raw_writel(i | (0x1 << MSC01_SC_CFG_GICENA_SHF),
- _msc01_biu_base + MSC01_SC_CFG_OFS);
- pr_debug("GIC Enabled\n");
- }
- i8259_irq = MIPS_GIC_IRQ_BASE + GIC_INT_I8259A;
corehi_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_COREHI;
} else {
#if defined(CONFIG_MIPS_MT_SMP)
@@ -361,19 +303,14 @@ void __init arch_init_irq(void)
arch_init_ipiirq(cpu_ipi_call_irq, &irq_call);
#endif
if (cpu_has_veic) {
- set_vi_handler(MSC01E_INT_I8259A,
- malta_hw0_irqdispatch);
set_vi_handler(MSC01E_INT_COREHI,
corehi_irqdispatch);
- i8259_irq = MSC01E_INT_BASE + MSC01E_INT_I8259A;
corehi_irq = MSC01E_INT_BASE + MSC01E_INT_COREHI;
} else {
- i8259_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_I8259A;
corehi_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_COREHI;
}
}
- setup_irq(i8259_irq, &i8259irq);
setup_irq(corehi_irq, &corehi_irqaction);
}
diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c
index 9d1e7f5..4740c82 100644
--- a/arch/mips/mti-malta/malta-setup.c
+++ b/arch/mips/mti-malta/malta-setup.c
@@ -27,6 +27,7 @@
#include <linux/time.h>
#include <asm/fw/fw.h>
+#include <asm/mach-malta/malta-dtshim.h>
#include <asm/mips-cm.h>
#include <asm/mips-boards/generic.h>
#include <asm/mips-boards/malta.h>
@@ -250,8 +251,10 @@ static void __init bonito_quirks_setup(void)
void __init plat_mem_setup(void)
{
unsigned int i;
+ void *fdt = __dtb_start;
- __dt_setup_arch(__dtb_start);
+ fdt = malta_dt_shim(fdt);
+ __dt_setup_arch(fdt);
if (config_enabled(CONFIG_EVA))
/* EVA has already been configured in mach-malta/kernel-init.h */
--
2.4.1
This code is only invoked from Malta's corehi_irqdispatch function,
which would then promptly die() even if it did service an interrupt.
It most definitely isn't needed for any vaguely recent Malta system
and since it seems to be broken for any older ones & nobody even
noticed, just remove it.
Signed-off-by: Paul Burton <[email protected]>
---
arch/mips/include/asm/msc01_ic.h | 147 ------------------------------------
arch/mips/kernel/Makefile | 1 -
arch/mips/kernel/irq-msc01.c | 159 ---------------------------------------
arch/mips/mti-malta/malta-int.c | 53 -------------
arch/mips/mti-malta/malta-time.c | 1 -
5 files changed, 361 deletions(-)
delete mode 100644 arch/mips/include/asm/msc01_ic.h
delete mode 100644 arch/mips/kernel/irq-msc01.c
diff --git a/arch/mips/include/asm/msc01_ic.h b/arch/mips/include/asm/msc01_ic.h
deleted file mode 100644
index ff7f074..0000000
--- a/arch/mips/include/asm/msc01_ic.h
+++ /dev/null
@@ -1,147 +0,0 @@
-/*
- * PCI Register definitions for the MIPS System Controller.
- *
- * Copyright (C) 2004 MIPS Technologies, Inc. All rights reserved.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-
-#ifndef __ASM_MIPS_BOARDS_MSC01_IC_H
-#define __ASM_MIPS_BOARDS_MSC01_IC_H
-
-/*****************************************************************************
- * Register offset addresses
- *****************************************************************************/
-
-#define MSC01_IC_RST_OFS 0x00008 /* Software reset */
-#define MSC01_IC_ENAL_OFS 0x00100 /* Int_in enable mask 31:0 */
-#define MSC01_IC_ENAH_OFS 0x00108 /* Int_in enable mask 63:32 */
-#define MSC01_IC_DISL_OFS 0x00120 /* Int_in disable mask 31:0 */
-#define MSC01_IC_DISH_OFS 0x00128 /* Int_in disable mask 63:32 */
-#define MSC01_IC_ISBL_OFS 0x00140 /* Raw int_in 31:0 */
-#define MSC01_IC_ISBH_OFS 0x00148 /* Raw int_in 63:32 */
-#define MSC01_IC_ISAL_OFS 0x00160 /* Masked int_in 31:0 */
-#define MSC01_IC_ISAH_OFS 0x00168 /* Masked int_in 63:32 */
-#define MSC01_IC_LVL_OFS 0x00180 /* Disable priority int_out */
-#define MSC01_IC_RAMW_OFS 0x00180 /* Shadow set RAM (EI) */
-#define MSC01_IC_OSB_OFS 0x00188 /* Raw int_out */
-#define MSC01_IC_OSA_OFS 0x00190 /* Masked int_out */
-#define MSC01_IC_GENA_OFS 0x00198 /* Global HW int enable */
-#define MSC01_IC_BASE_OFS 0x001a0 /* Base address of IC_VEC */
-#define MSC01_IC_VEC_OFS 0x001b0 /* Active int's vector address */
-#define MSC01_IC_EOI_OFS 0x001c0 /* Enable lower level ints */
-#define MSC01_IC_CFG_OFS 0x001c8 /* Configuration register */
-#define MSC01_IC_TRLD_OFS 0x001d0 /* Interval timer reload val */
-#define MSC01_IC_TVAL_OFS 0x001e0 /* Interval timer current val */
-#define MSC01_IC_TCFG_OFS 0x001f0 /* Interval timer config */
-#define MSC01_IC_SUP_OFS 0x00200 /* Set up int_in line 0 */
-#define MSC01_IC_ENA_OFS 0x00800 /* Int_in enable mask 63:0 */
-#define MSC01_IC_DIS_OFS 0x00820 /* Int_in disable mask 63:0 */
-#define MSC01_IC_ISB_OFS 0x00840 /* Raw int_in 63:0 */
-#define MSC01_IC_ISA_OFS 0x00860 /* Masked int_in 63:0 */
-
-/*****************************************************************************
- * Register field encodings
- *****************************************************************************/
-
-#define MSC01_IC_RST_RST_SHF 0
-#define MSC01_IC_RST_RST_MSK 0x00000001
-#define MSC01_IC_RST_RST_BIT MSC01_IC_RST_RST_MSK
-#define MSC01_IC_LVL_LVL_SHF 0
-#define MSC01_IC_LVL_LVL_MSK 0x000000ff
-#define MSC01_IC_LVL_SPUR_SHF 16
-#define MSC01_IC_LVL_SPUR_MSK 0x00010000
-#define MSC01_IC_LVL_SPUR_BIT MSC01_IC_LVL_SPUR_MSK
-#define MSC01_IC_RAMW_RIPL_SHF 0
-#define MSC01_IC_RAMW_RIPL_MSK 0x0000003f
-#define MSC01_IC_RAMW_DATA_SHF 6
-#define MSC01_IC_RAMW_DATA_MSK 0x00000fc0
-#define MSC01_IC_RAMW_ADDR_SHF 25
-#define MSC01_IC_RAMW_ADDR_MSK 0x7e000000
-#define MSC01_IC_RAMW_READ_SHF 31
-#define MSC01_IC_RAMW_READ_MSK 0x80000000
-#define MSC01_IC_RAMW_READ_BIT MSC01_IC_RAMW_READ_MSK
-#define MSC01_IC_OSB_OSB_SHF 0
-#define MSC01_IC_OSB_OSB_MSK 0x000000ff
-#define MSC01_IC_OSA_OSA_SHF 0
-#define MSC01_IC_OSA_OSA_MSK 0x000000ff
-#define MSC01_IC_GENA_GENA_SHF 0
-#define MSC01_IC_GENA_GENA_MSK 0x00000001
-#define MSC01_IC_GENA_GENA_BIT MSC01_IC_GENA_GENA_MSK
-#define MSC01_IC_CFG_DIS_SHF 0
-#define MSC01_IC_CFG_DIS_MSK 0x00000001
-#define MSC01_IC_CFG_DIS_BIT MSC01_IC_CFG_DIS_MSK
-#define MSC01_IC_CFG_SHFT_SHF 8
-#define MSC01_IC_CFG_SHFT_MSK 0x00000f00
-#define MSC01_IC_TCFG_ENA_SHF 0
-#define MSC01_IC_TCFG_ENA_MSK 0x00000001
-#define MSC01_IC_TCFG_ENA_BIT MSC01_IC_TCFG_ENA_MSK
-#define MSC01_IC_TCFG_INT_SHF 8
-#define MSC01_IC_TCFG_INT_MSK 0x00000100
-#define MSC01_IC_TCFG_INT_BIT MSC01_IC_TCFG_INT_MSK
-#define MSC01_IC_TCFG_EDGE_SHF 16
-#define MSC01_IC_TCFG_EDGE_MSK 0x00010000
-#define MSC01_IC_TCFG_EDGE_BIT MSC01_IC_TCFG_EDGE_MSK
-#define MSC01_IC_SUP_PRI_SHF 0
-#define MSC01_IC_SUP_PRI_MSK 0x00000007
-#define MSC01_IC_SUP_EDGE_SHF 8
-#define MSC01_IC_SUP_EDGE_MSK 0x00000100
-#define MSC01_IC_SUP_EDGE_BIT MSC01_IC_SUP_EDGE_MSK
-#define MSC01_IC_SUP_STEP 8
-
-/*
- * MIPS System controller interrupt register base.
- *
- */
-
-/*****************************************************************************
- * Absolute register addresses
- *****************************************************************************/
-
-#define MSC01_IC_RST (MSC01_IC_REG_BASE + MSC01_IC_RST_OFS)
-#define MSC01_IC_ENAL (MSC01_IC_REG_BASE + MSC01_IC_ENAL_OFS)
-#define MSC01_IC_ENAH (MSC01_IC_REG_BASE + MSC01_IC_ENAH_OFS)
-#define MSC01_IC_DISL (MSC01_IC_REG_BASE + MSC01_IC_DISL_OFS)
-#define MSC01_IC_DISH (MSC01_IC_REG_BASE + MSC01_IC_DISH_OFS)
-#define MSC01_IC_ISBL (MSC01_IC_REG_BASE + MSC01_IC_ISBL_OFS)
-#define MSC01_IC_ISBH (MSC01_IC_REG_BASE + MSC01_IC_ISBH_OFS)
-#define MSC01_IC_ISAL (MSC01_IC_REG_BASE + MSC01_IC_ISAL_OFS)
-#define MSC01_IC_ISAH (MSC01_IC_REG_BASE + MSC01_IC_ISAH_OFS)
-#define MSC01_IC_LVL (MSC01_IC_REG_BASE + MSC01_IC_LVL_OFS)
-#define MSC01_IC_RAMW (MSC01_IC_REG_BASE + MSC01_IC_RAMW_OFS)
-#define MSC01_IC_OSB (MSC01_IC_REG_BASE + MSC01_IC_OSB_OFS)
-#define MSC01_IC_OSA (MSC01_IC_REG_BASE + MSC01_IC_OSA_OFS)
-#define MSC01_IC_GENA (MSC01_IC_REG_BASE + MSC01_IC_GENA_OFS)
-#define MSC01_IC_BASE (MSC01_IC_REG_BASE + MSC01_IC_BASE_OFS)
-#define MSC01_IC_VEC (MSC01_IC_REG_BASE + MSC01_IC_VEC_OFS)
-#define MSC01_IC_EOI (MSC01_IC_REG_BASE + MSC01_IC_EOI_OFS)
-#define MSC01_IC_CFG (MSC01_IC_REG_BASE + MSC01_IC_CFG_OFS)
-#define MSC01_IC_TRLD (MSC01_IC_REG_BASE + MSC01_IC_TRLD_OFS)
-#define MSC01_IC_TVAL (MSC01_IC_REG_BASE + MSC01_IC_TVAL_OFS)
-#define MSC01_IC_TCFG (MSC01_IC_REG_BASE + MSC01_IC_TCFG_OFS)
-#define MSC01_IC_SUP (MSC01_IC_REG_BASE + MSC01_IC_SUP_OFS)
-#define MSC01_IC_ENA (MSC01_IC_REG_BASE + MSC01_IC_ENA_OFS)
-#define MSC01_IC_DIS (MSC01_IC_REG_BASE + MSC01_IC_DIS_OFS)
-#define MSC01_IC_ISB (MSC01_IC_REG_BASE + MSC01_IC_ISB_OFS)
-#define MSC01_IC_ISA (MSC01_IC_REG_BASE + MSC01_IC_ISA_OFS)
-
-/*
- * Soc-it interrupts are configurable.
- * Every board describes its IRQ mapping with this table.
- */
-typedef struct msc_irqmap {
- int im_irq;
- int im_type;
- int im_lvl;
-} msc_irqmap_t;
-
-/* im_type */
-#define MSC01_IRQ_LEVEL 0
-#define MSC01_IRQ_EDGE 1
-
-extern void __init init_msc_irqs(unsigned long icubase, unsigned int base, msc_irqmap_t *imp, int nirq);
-extern void ll_msc_irq(void);
-
-#endif /* __ASM_MIPS_BOARDS_MSC01_IC_H */
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index d3d2ff2..738d943 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -64,7 +64,6 @@ obj-$(CONFIG_MIPS_VPE_APSP_API_MT) += rtlx-mt.o
obj-$(CONFIG_I8259) += i8259.o
obj-$(CONFIG_IRQ_CPU) += irq_cpu.o
obj-$(CONFIG_IRQ_CPU_RM7K) += irq-rm7000.o
-obj-$(CONFIG_MIPS_MSC) += irq-msc01.o
obj-$(CONFIG_IRQ_TXX9) += irq_txx9.o
obj-$(CONFIG_IRQ_GT641XX) += irq-gt641xx.o
diff --git a/arch/mips/kernel/irq-msc01.c b/arch/mips/kernel/irq-msc01.c
deleted file mode 100644
index a734b2c..0000000
--- a/arch/mips/kernel/irq-msc01.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * Copyright (c) 2004 MIPS Inc
- * Author: [email protected]
- *
- * Copyright (C) 2004, 06 Ralf Baechle <[email protected]>
- */
-#include <linux/interrupt.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/kernel_stat.h>
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/msc01_ic.h>
-#include <asm/traps.h>
-
-static unsigned long _icctrl_msc;
-#define MSC01_IC_REG_BASE _icctrl_msc
-
-#define MSCIC_WRITE(reg, data) do { *(volatile u32 *)(reg) = data; } while (0)
-#define MSCIC_READ(reg, data) do { data = *(volatile u32 *)(reg); } while (0)
-
-static unsigned int irq_base;
-
-/* mask off an interrupt */
-static inline void mask_msc_irq(struct irq_data *d)
-{
- unsigned int irq = d->irq;
-
- if (irq < (irq_base + 32))
- MSCIC_WRITE(MSC01_IC_DISL, 1<<(irq - irq_base));
- else
- MSCIC_WRITE(MSC01_IC_DISH, 1<<(irq - irq_base - 32));
-}
-
-/* unmask an interrupt */
-static inline void unmask_msc_irq(struct irq_data *d)
-{
- unsigned int irq = d->irq;
-
- if (irq < (irq_base + 32))
- MSCIC_WRITE(MSC01_IC_ENAL, 1<<(irq - irq_base));
- else
- MSCIC_WRITE(MSC01_IC_ENAH, 1<<(irq - irq_base - 32));
-}
-
-/*
- * Masks and ACKs an IRQ
- */
-static void level_mask_and_ack_msc_irq(struct irq_data *d)
-{
- mask_msc_irq(d);
- if (!cpu_has_veic)
- MSCIC_WRITE(MSC01_IC_EOI, 0);
-}
-
-/*
- * Masks and ACKs an IRQ
- */
-static void edge_mask_and_ack_msc_irq(struct irq_data *d)
-{
- unsigned int irq = d->irq;
-
- mask_msc_irq(d);
- if (!cpu_has_veic)
- MSCIC_WRITE(MSC01_IC_EOI, 0);
- else {
- u32 r;
- MSCIC_READ(MSC01_IC_SUP+irq*8, r);
- MSCIC_WRITE(MSC01_IC_SUP+irq*8, r | ~MSC01_IC_SUP_EDGE_BIT);
- MSCIC_WRITE(MSC01_IC_SUP+irq*8, r);
- }
-}
-
-/*
- * Interrupt handler for interrupts coming from SOC-it.
- */
-void ll_msc_irq(void)
-{
- unsigned int irq;
-
- /* read the interrupt vector register */
- MSCIC_READ(MSC01_IC_VEC, irq);
- if (irq < 64)
- do_IRQ(irq + irq_base);
- else {
- /* Ignore spurious interrupt */
- }
-}
-
-static void msc_bind_eic_interrupt(int irq, int set)
-{
- MSCIC_WRITE(MSC01_IC_RAMW,
- (irq<<MSC01_IC_RAMW_ADDR_SHF) | (set<<MSC01_IC_RAMW_DATA_SHF));
-}
-
-static struct irq_chip msc_levelirq_type = {
- .name = "SOC-it-Level",
- .irq_ack = level_mask_and_ack_msc_irq,
- .irq_mask = mask_msc_irq,
- .irq_mask_ack = level_mask_and_ack_msc_irq,
- .irq_unmask = unmask_msc_irq,
- .irq_eoi = unmask_msc_irq,
-};
-
-static struct irq_chip msc_edgeirq_type = {
- .name = "SOC-it-Edge",
- .irq_ack = edge_mask_and_ack_msc_irq,
- .irq_mask = mask_msc_irq,
- .irq_mask_ack = edge_mask_and_ack_msc_irq,
- .irq_unmask = unmask_msc_irq,
- .irq_eoi = unmask_msc_irq,
-};
-
-
-void __init init_msc_irqs(unsigned long icubase, unsigned int irqbase, msc_irqmap_t *imp, int nirq)
-{
- _icctrl_msc = (unsigned long) ioremap(icubase, 0x40000);
-
- /* Reset interrupt controller - initialises all registers to 0 */
- MSCIC_WRITE(MSC01_IC_RST, MSC01_IC_RST_RST_BIT);
-
- board_bind_eic_interrupt = &msc_bind_eic_interrupt;
-
- for (; nirq > 0; nirq--, imp++) {
- int n = imp->im_irq;
-
- switch (imp->im_type) {
- case MSC01_IRQ_EDGE:
- irq_set_chip_and_handler_name(irqbase + n,
- &msc_edgeirq_type,
- handle_edge_irq,
- "edge");
- if (cpu_has_veic)
- MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT);
- else
- MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl);
- break;
- case MSC01_IRQ_LEVEL:
- irq_set_chip_and_handler_name(irqbase + n,
- &msc_levelirq_type,
- handle_level_irq,
- "level");
- if (cpu_has_veic)
- MSCIC_WRITE(MSC01_IC_SUP+n*8, 0);
- else
- MSCIC_WRITE(MSC01_IC_SUP+n*8, imp->im_lvl);
- }
- }
-
- irq_base = irqbase;
-
- MSCIC_WRITE(MSC01_IC_GENA, MSC01_IC_GENA_GENA_BIT); /* Enable interrupt generation */
-
-}
diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c
index 3fe5c17..ea809cf 100644
--- a/arch/mips/mti-malta/malta-int.c
+++ b/arch/mips/mti-malta/malta-int.c
@@ -35,7 +35,6 @@
#include <asm/gt64120.h>
#include <asm/mips-boards/generic.h>
#include <asm/mips-boards/msc01_pci.h>
-#include <asm/msc01_ic.h>
#include <asm/setup.h>
#include <asm/rtlx.h>
@@ -126,12 +125,6 @@ static void corehi_irqdispatch(void)
*/
switch (mips_revision_sconid) {
- case MIPS_REVISION_SCON_SOCIT:
- case MIPS_REVISION_SCON_ROCIT:
- case MIPS_REVISION_SCON_SOCITSC:
- case MIPS_REVISION_SCON_SOCITSCP:
- ll_msc_irq();
- break;
case MIPS_REVISION_SCON_GT64120:
intrcause = GT_READ(GT_INTRCAUSE_OFS);
datalo = GT_READ(GT_CPUERR_ADDRLO_OFS);
@@ -225,27 +218,6 @@ static struct irqaction corehi_irqaction = {
.flags = IRQF_NO_THREAD,
};
-static msc_irqmap_t msc_irqmap[] __initdata = {
- {MSC01C_INT_TMR, MSC01_IRQ_EDGE, 0},
- {MSC01C_INT_PCI, MSC01_IRQ_LEVEL, 0},
-};
-static int msc_nr_irqs __initdata = ARRAY_SIZE(msc_irqmap);
-
-static msc_irqmap_t msc_eicirqmap[] __initdata = {
- {MSC01E_INT_SW0, MSC01_IRQ_LEVEL, 0},
- {MSC01E_INT_SW1, MSC01_IRQ_LEVEL, 0},
- {MSC01E_INT_I8259A, MSC01_IRQ_LEVEL, 0},
- {MSC01E_INT_SMI, MSC01_IRQ_LEVEL, 0},
- {MSC01E_INT_COREHI, MSC01_IRQ_LEVEL, 0},
- {MSC01E_INT_CORELO, MSC01_IRQ_LEVEL, 0},
- {MSC01E_INT_TMR, MSC01_IRQ_EDGE, 0},
- {MSC01E_INT_PCI, MSC01_IRQ_LEVEL, 0},
- {MSC01E_INT_PERFCTR, MSC01_IRQ_LEVEL, 0},
- {MSC01E_INT_CPUCTR, MSC01_IRQ_LEVEL, 0}
-};
-
-static int msc_nr_eicirqs __initdata = ARRAY_SIZE(msc_eicirqmap);
-
void __init arch_init_ipiirq(int irq, struct irqaction *action)
{
setup_irq(irq, action);
@@ -258,31 +230,6 @@ void __init arch_init_irq(void)
irqchip_init();
- switch (mips_revision_sconid) {
- case MIPS_REVISION_SCON_SOCIT:
- case MIPS_REVISION_SCON_ROCIT:
- if (cpu_has_veic)
- init_msc_irqs(MIPS_MSC01_IC_REG_BASE,
- MSC01E_INT_BASE, msc_eicirqmap,
- msc_nr_eicirqs);
- else
- init_msc_irqs(MIPS_MSC01_IC_REG_BASE,
- MSC01C_INT_BASE, msc_irqmap,
- msc_nr_irqs);
- break;
-
- case MIPS_REVISION_SCON_SOCITSC:
- case MIPS_REVISION_SCON_SOCITSCP:
- if (cpu_has_veic)
- init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE,
- MSC01E_INT_BASE, msc_eicirqmap,
- msc_nr_eicirqs);
- else
- init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE,
- MSC01C_INT_BASE, msc_irqmap,
- msc_nr_irqs);
- }
-
if (gic_present) {
corehi_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_COREHI;
} else {
diff --git a/arch/mips/mti-malta/malta-time.c b/arch/mips/mti-malta/malta-time.c
index 185e682..fcdc156 100644
--- a/arch/mips/mti-malta/malta-time.c
+++ b/arch/mips/mti-malta/malta-time.c
@@ -37,7 +37,6 @@
#include <asm/setup.h>
#include <asm/time.h>
#include <asm/mc146818-time.h>
-#include <asm/msc01_ic.h>
#include <asm/mips-boards/generic.h>
#include <asm/mips-boards/maltaint.h>
--
2.4.1
If the address provided for the UART is of an I/O port rather than
a regular memory address, then set the port iotype appropriately and
write the address to iobase rather than mapbase.
Signed-off-by: Paul Burton <[email protected]>
---
drivers/tty/serial/of_serial.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/tty/serial/of_serial.c b/drivers/tty/serial/of_serial.c
index 137381e..ccff9ba 100644
--- a/drivers/tty/serial/of_serial.c
+++ b/drivers/tty/serial/of_serial.c
@@ -110,7 +110,12 @@ static int of_platform_serial_setup(struct platform_device *ofdev,
port->irq = irq_of_parse_and_map(np, 0);
port->iotype = UPIO_MEM;
- if (of_property_read_u32(np, "reg-io-width", &prop) == 0) {
+
+ if (resource.flags & IORESOURCE_IO) {
+ port->iotype = UPIO_PORT;
+ port->iobase = port->mapbase;
+ port->mapbase = 0;
+ } else if (of_property_read_u32(np, "reg-io-width", &prop) == 0) {
switch (prop) {
case 1:
port->iotype = UPIO_MEM;
--
2.4.1
Add the DT nodes required to probe the UARTs present in the Malta
development board, and remove the platform data that was previously
accomplishing the same thing. Enable CONFIG_SERIAL_OF_PLATFORM in the
various Malta defconfigs in order to continue supporting serial output
when using them.
Signed-off-by: Paul Burton <[email protected]>
---
arch/mips/boot/dts/mti/malta.dts | 51 +++++++++++++++++++++++++++++
arch/mips/configs/malta_defconfig | 1 +
arch/mips/configs/malta_kvm_defconfig | 1 +
arch/mips/configs/malta_kvm_guest_defconfig | 1 +
arch/mips/configs/malta_qemu_32r6_defconfig | 1 +
arch/mips/configs/maltaaprp_defconfig | 1 +
arch/mips/configs/maltasmvp_defconfig | 1 +
arch/mips/configs/maltasmvp_eva_defconfig | 1 +
arch/mips/configs/maltaup_defconfig | 1 +
arch/mips/configs/maltaup_xpa_defconfig | 1 +
arch/mips/mti-malta/malta-platform.c | 37 ---------------------
11 files changed, 60 insertions(+), 37 deletions(-)
diff --git a/arch/mips/boot/dts/mti/malta.dts b/arch/mips/boot/dts/mti/malta.dts
index 4bcdeb4..905a347 100644
--- a/arch/mips/boot/dts/mti/malta.dts
+++ b/arch/mips/boot/dts/mti/malta.dts
@@ -43,6 +43,57 @@
};
};
+ isa {
+ compatible = "isa";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <1 0 0 0x1000>;
+
+ uart0: uart@3f8 {
+ compatible = "ns16550";
+ reg = <1 0x3f8 0x8>;
+
+ clock-frequency = <1843200>;
+
+ interrupt-parent = <&i8259>;
+ interrupts = <4>;
+
+ no-loopback-test;
+ };
+
+ uart1: uart@2f8 {
+ compatible = "ns16550";
+ reg = <1 0x2f8 0x8>;
+
+ clock-frequency = <1843200>;
+
+ interrupt-parent = <&i8259>;
+ interrupts = <3>;
+
+ no-loopback-test;
+ };
+ };
+
+ fpga {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1f000000 0x100000>;
+
+ uart2: uart@900 {
+ compatible = "ns16550";
+
+ reg = <0x900 0x40>;
+ reg-io-width = <4>;
+ reg-shift = <3>;
+
+ clock-frequency = <3686400>;
+
+ interrupt-parent = <&cpu_intc>;
+ interrupts = <4>;
+ };
+ };
+
board {
compatible = "simple-bus";
#address-cells = <1>;
diff --git a/arch/mips/configs/malta_defconfig b/arch/mips/configs/malta_defconfig
index 61a4460..4f0528c 100644
--- a/arch/mips/configs/malta_defconfig
+++ b/arch/mips/configs/malta_defconfig
@@ -320,6 +320,7 @@ CONFIG_LIBERTAS=m
# CONFIG_SERIO_I8042 is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_OF_PLATFORM=y
# CONFIG_HWMON is not set
CONFIG_FB=y
CONFIG_FB_CIRRUS=y
diff --git a/arch/mips/configs/malta_kvm_defconfig b/arch/mips/configs/malta_kvm_defconfig
index d41742d..815595d 100644
--- a/arch/mips/configs/malta_kvm_defconfig
+++ b/arch/mips/configs/malta_kvm_defconfig
@@ -329,6 +329,7 @@ CONFIG_LIBERTAS=m
# CONFIG_SERIO_I8042 is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_OF_PLATFORM=y
# CONFIG_HWMON is not set
CONFIG_FB=y
CONFIG_FB_CIRRUS=y
diff --git a/arch/mips/configs/malta_kvm_guest_defconfig b/arch/mips/configs/malta_kvm_guest_defconfig
index a7806e8..2a0d7b0 100644
--- a/arch/mips/configs/malta_kvm_guest_defconfig
+++ b/arch/mips/configs/malta_kvm_guest_defconfig
@@ -329,6 +329,7 @@ CONFIG_LIBERTAS=m
# CONFIG_SERIO_I8042 is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_OF_PLATFORM=y
# CONFIG_HWMON is not set
CONFIG_FB=y
CONFIG_FB_CIRRUS=y
diff --git a/arch/mips/configs/malta_qemu_32r6_defconfig b/arch/mips/configs/malta_qemu_32r6_defconfig
index 4bce1f8..9415088 100644
--- a/arch/mips/configs/malta_qemu_32r6_defconfig
+++ b/arch/mips/configs/malta_qemu_32r6_defconfig
@@ -132,6 +132,7 @@ CONFIG_PCNET32=y
CONFIG_LEGACY_PTY_COUNT=4
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_HW_RANDOM=y
# CONFIG_HWMON is not set
CONFIG_FB=y
diff --git a/arch/mips/configs/maltaaprp_defconfig b/arch/mips/configs/maltaaprp_defconfig
index fb042ce..955897a 100644
--- a/arch/mips/configs/maltaaprp_defconfig
+++ b/arch/mips/configs/maltaaprp_defconfig
@@ -132,6 +132,7 @@ CONFIG_PCNET32=y
CONFIG_LEGACY_PTY_COUNT=16
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_HW_RANDOM=y
# CONFIG_HWMON is not set
CONFIG_VIDEO_OUTPUT_CONTROL=m
diff --git a/arch/mips/configs/maltasmvp_defconfig b/arch/mips/configs/maltasmvp_defconfig
index f8a3231..b3ae18e 100644
--- a/arch/mips/configs/maltasmvp_defconfig
+++ b/arch/mips/configs/maltasmvp_defconfig
@@ -136,6 +136,7 @@ CONFIG_PCNET32=y
CONFIG_LEGACY_PTY_COUNT=4
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_HW_RANDOM=y
# CONFIG_HWMON is not set
CONFIG_VIDEO_OUTPUT_CONTROL=m
diff --git a/arch/mips/configs/maltasmvp_eva_defconfig b/arch/mips/configs/maltasmvp_eva_defconfig
index c83338a..9ae3235 100644
--- a/arch/mips/configs/maltasmvp_eva_defconfig
+++ b/arch/mips/configs/maltasmvp_eva_defconfig
@@ -137,6 +137,7 @@ CONFIG_PCNET32=y
CONFIG_LEGACY_PTY_COUNT=4
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_HW_RANDOM=y
# CONFIG_HWMON is not set
CONFIG_VIDEO_OUTPUT_CONTROL=m
diff --git a/arch/mips/configs/maltaup_defconfig b/arch/mips/configs/maltaup_defconfig
index 6234464..73a54ca 100644
--- a/arch/mips/configs/maltaup_defconfig
+++ b/arch/mips/configs/maltaup_defconfig
@@ -131,6 +131,7 @@ CONFIG_PCNET32=y
CONFIG_LEGACY_PTY_COUNT=16
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_HW_RANDOM=y
# CONFIG_HWMON is not set
CONFIG_VIDEO_OUTPUT_CONTROL=m
diff --git a/arch/mips/configs/maltaup_xpa_defconfig b/arch/mips/configs/maltaup_xpa_defconfig
index c388bff..7d7714c 100644
--- a/arch/mips/configs/maltaup_xpa_defconfig
+++ b/arch/mips/configs/maltaup_xpa_defconfig
@@ -324,6 +324,7 @@ CONFIG_LIBERTAS=m
# CONFIG_SERIO_I8042 is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_OF_PLATFORM=y
# CONFIG_HWMON is not set
CONFIG_FB=y
CONFIG_FB_CIRRUS=y
diff --git a/arch/mips/mti-malta/malta-platform.c b/arch/mips/mti-malta/malta-platform.c
index e1dd1c1..184c00d5 100644
--- a/arch/mips/mti-malta/malta-platform.c
+++ b/arch/mips/mti-malta/malta-platform.c
@@ -32,42 +32,6 @@
#include <asm/mips-boards/maltaint.h>
#include <mtd/mtd-abi.h>
-#define SMC_PORT(base, int) \
-{ \
- .iobase = base, \
- .irq = int, \
- .uartclk = 1843200, \
- .iotype = UPIO_PORT, \
- .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, \
- .regshift = 0, \
-}
-
-#define CBUS_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP)
-
-static struct plat_serial8250_port uart8250_data[] = {
- SMC_PORT(0x3F8, 4),
- SMC_PORT(0x2F8, 3),
-#ifndef CONFIG_MIPS_CMP
- {
- .mapbase = 0x1f000900, /* The CBUS UART */
- .irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_MB2,
- .uartclk = 3686400, /* Twice the usual clk! */
- .iotype = UPIO_MEM32,
- .flags = CBUS_UART_FLAGS,
- .regshift = 3,
- },
-#endif
- { },
-};
-
-static struct platform_device malta_uart8250_device = {
- .name = "serial8250",
- .id = PLAT8250_DEV_PLATFORM,
- .dev = {
- .platform_data = uart8250_data,
- },
-};
-
struct resource malta_rtc_resources[] = {
{
.start = RTC_PORT(0),
@@ -128,7 +92,6 @@ static struct platform_device malta_flash_device = {
};
static struct platform_device *malta_devices[] __initdata = {
- &malta_uart8250_device,
&malta_rtc_device,
&malta_flash_device,
};
--
2.4.1
Add the DT node required to probe the RTC, and remove the platform code
that was previously doing it.
Signed-off-by: Paul Burton <[email protected]>
---
arch/mips/boot/dts/mti/malta.dts | 8 ++++++++
arch/mips/mti-malta/malta-platform.c | 20 --------------------
2 files changed, 8 insertions(+), 20 deletions(-)
diff --git a/arch/mips/boot/dts/mti/malta.dts b/arch/mips/boot/dts/mti/malta.dts
index 905a347..66df923 100644
--- a/arch/mips/boot/dts/mti/malta.dts
+++ b/arch/mips/boot/dts/mti/malta.dts
@@ -49,6 +49,14 @@
#size-cells = <1>;
ranges = <1 0 0 0x1000>;
+ rtc: mc146818@70 {
+ compatible = "motorola,mc146818";
+ reg = <1 0x70 0x8>;
+
+ interrupt-parent = <&i8259>;
+ interrupts = <8>;
+ };
+
uart0: uart@3f8 {
compatible = "ns16550";
reg = <1 0x3f8 0x8>;
diff --git a/arch/mips/mti-malta/malta-platform.c b/arch/mips/mti-malta/malta-platform.c
index 184c00d5..c41b0e0 100644
--- a/arch/mips/mti-malta/malta-platform.c
+++ b/arch/mips/mti-malta/malta-platform.c
@@ -32,25 +32,6 @@
#include <asm/mips-boards/maltaint.h>
#include <mtd/mtd-abi.h>
-struct resource malta_rtc_resources[] = {
- {
- .start = RTC_PORT(0),
- .end = RTC_PORT(7),
- .flags = IORESOURCE_IO,
- }, {
- .start = RTC_IRQ,
- .end = RTC_IRQ,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-static struct platform_device malta_rtc_device = {
- .name = "rtc_cmos",
- .id = -1,
- .resource = malta_rtc_resources,
- .num_resources = ARRAY_SIZE(malta_rtc_resources),
-};
-
static struct mtd_partition malta_mtd_partitions[] = {
{
.name = "YAMON",
@@ -92,7 +73,6 @@ static struct platform_device malta_flash_device = {
};
static struct platform_device *malta_devices[] __initdata = {
- &malta_rtc_device,
&malta_flash_device,
};
--
2.4.1
Add the DT nodes required to probe the CFI compatible parallel monitor
flash found on the Malta development board, and remove the platform
code that was previously doing it. Delete the now-empty malta-platform.c
file. Adjust the Malta defconfigs that enable MTD & the pflash/CFI
driver to enable CONFIG_MTD_PHYSMAP_OF rather than CONFIG_MTD_PHYSMAP in
order to preserve their behaviour.
Signed-off-by: Paul Burton <[email protected]>
---
arch/mips/boot/dts/mti/malta.dts | 25 ++++++++
arch/mips/configs/malta_defconfig | 2 +-
arch/mips/configs/malta_kvm_defconfig | 2 +-
arch/mips/configs/malta_kvm_guest_defconfig | 2 +-
arch/mips/configs/maltaup_xpa_defconfig | 2 +-
arch/mips/mti-malta/Makefile | 2 +-
arch/mips/mti-malta/malta-platform.c | 90 -----------------------------
7 files changed, 30 insertions(+), 95 deletions(-)
delete mode 100644 arch/mips/mti-malta/malta-platform.c
diff --git a/arch/mips/boot/dts/mti/malta.dts b/arch/mips/boot/dts/mti/malta.dts
index 66df923..9720c66 100644
--- a/arch/mips/boot/dts/mti/malta.dts
+++ b/arch/mips/boot/dts/mti/malta.dts
@@ -117,5 +117,30 @@
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
};
+
+ pflash@1e000000 {
+ compatible = "intel,dt28f160", "cfi-flash";
+ reg = <0x1e000000 0x400000>;
+ bank-width = <4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ yamon@0 {
+ label = "YAMON";
+ reg = <0x0 0x100000>;
+ read-only;
+ };
+
+ user-fs@100000 {
+ label = "User FS";
+ reg = <0x100000 0x2e0000>;
+ };
+
+ board-config@3e0000 {
+ label = "Board Config";
+ reg = <0x3e0000 0x20000>;
+ read-only;
+ };
+ };
};
};
diff --git a/arch/mips/configs/malta_defconfig b/arch/mips/configs/malta_defconfig
index 4f0528c..52b00ab 100644
--- a/arch/mips/configs/malta_defconfig
+++ b/arch/mips/configs/malta_defconfig
@@ -230,7 +230,7 @@ CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_CFI_STAA=y
-CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_UBI=m
CONFIG_MTD_UBI_GLUEBI=m
CONFIG_BLK_DEV_FD=m
diff --git a/arch/mips/configs/malta_kvm_defconfig b/arch/mips/configs/malta_kvm_defconfig
index 815595d..7199654 100644
--- a/arch/mips/configs/malta_kvm_defconfig
+++ b/arch/mips/configs/malta_kvm_defconfig
@@ -235,7 +235,7 @@ CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_CFI_STAA=y
-CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_UBI=m
CONFIG_MTD_UBI_GLUEBI=m
CONFIG_BLK_DEV_FD=m
diff --git a/arch/mips/configs/malta_kvm_guest_defconfig b/arch/mips/configs/malta_kvm_guest_defconfig
index 2a0d7b0..9ba7149 100644
--- a/arch/mips/configs/malta_kvm_guest_defconfig
+++ b/arch/mips/configs/malta_kvm_guest_defconfig
@@ -234,7 +234,7 @@ CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_CFI_STAA=y
-CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_UBI=m
CONFIG_MTD_UBI_GLUEBI=m
CONFIG_BLK_DEV_FD=m
diff --git a/arch/mips/configs/maltaup_xpa_defconfig b/arch/mips/configs/maltaup_xpa_defconfig
index 7d7714c..245bf14 100644
--- a/arch/mips/configs/maltaup_xpa_defconfig
+++ b/arch/mips/configs/maltaup_xpa_defconfig
@@ -231,7 +231,7 @@ CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_CFI_STAA=y
-CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_UBI=m
CONFIG_MTD_UBI_GLUEBI=m
CONFIG_BLK_DEV_FD=m
diff --git a/arch/mips/mti-malta/Makefile b/arch/mips/mti-malta/Makefile
index 1d633fe..357fde1 100644
--- a/arch/mips/mti-malta/Makefile
+++ b/arch/mips/mti-malta/Makefile
@@ -6,7 +6,7 @@
# written by Ralf Baechle <[email protected]>
#
obj-y := malta-display.o malta-dt.o malta-dtshim.o malta-init.o \
- malta-int.o malta-memory.o malta-platform.o \
+ malta-int.o malta-memory.o \
malta-reset.o malta-setup.o malta-time.o
obj-$(CONFIG_MIPS_CMP) += malta-amon.o
diff --git a/arch/mips/mti-malta/malta-platform.c b/arch/mips/mti-malta/malta-platform.c
deleted file mode 100644
index c41b0e0..0000000
--- a/arch/mips/mti-malta/malta-platform.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2006, 07 MIPS Technologies, Inc.
- * written by Ralf Baechle ([email protected])
- * written by Ralf Baechle <[email protected]>
- *
- * Copyright (C) 2008 Wind River Systems, Inc.
- * updated by Tiejun Chen <[email protected]>
- *
- * 1. Probe driver for the Malta's UART ports:
- *
- * o 2 ports in the SMC SuperIO
- * o 1 port in the CBUS UART, a discrete 16550 which normally is only used
- * for bringups.
- *
- * We don't use 8250_platform.c on Malta as it would result in the CBUS
- * UART becoming ttyS0.
- *
- * 2. Register RTC-CMOS platform device on Malta.
- */
-#include <linux/init.h>
-#include <linux/serial_8250.h>
-#include <linux/mc146818rtc.h>
-#include <linux/module.h>
-#include <linux/irq.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/platform_device.h>
-#include <asm/mips-boards/maltaint.h>
-#include <mtd/mtd-abi.h>
-
-static struct mtd_partition malta_mtd_partitions[] = {
- {
- .name = "YAMON",
- .offset = 0x0,
- .size = 0x100000,
- .mask_flags = MTD_WRITEABLE
- }, {
- .name = "User FS",
- .offset = 0x100000,
- .size = 0x2e0000
- }, {
- .name = "Board Config",
- .offset = 0x3e0000,
- .size = 0x020000,
- .mask_flags = MTD_WRITEABLE
- }
-};
-
-static struct physmap_flash_data malta_flash_data = {
- .width = 4,
- .nr_parts = ARRAY_SIZE(malta_mtd_partitions),
- .parts = malta_mtd_partitions
-};
-
-static struct resource malta_flash_resource = {
- .start = 0x1e000000,
- .end = 0x1e3fffff,
- .flags = IORESOURCE_MEM
-};
-
-static struct platform_device malta_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &malta_flash_data,
- },
- .num_resources = 1,
- .resource = &malta_flash_resource,
-};
-
-static struct platform_device *malta_devices[] __initdata = {
- &malta_flash_device,
-};
-
-static int __init malta_add_devices(void)
-{
- int err;
-
- err = platform_add_devices(malta_devices, ARRAY_SIZE(malta_devices));
- if (err)
- return err;
-
- return 0;
-}
-
-device_initcall(malta_add_devices);
--
2.4.1
The fw_getmdesc function & fw_memblock_t abstraction is only used by
Malta, and so far as I can tell serves no purpose beyond making the code
less clear than it could be. Remove the useless level of abstraction.
Signed-off-by: Paul Burton <[email protected]>
---
arch/mips/include/asm/fw/fw.h | 16 -------
arch/mips/mti-malta/malta-memory.c | 93 ++++++++++++--------------------------
2 files changed, 29 insertions(+), 80 deletions(-)
diff --git a/arch/mips/include/asm/fw/fw.h b/arch/mips/include/asm/fw/fw.h
index f3e6978..d0ef8b4 100644
--- a/arch/mips/include/asm/fw/fw.h
+++ b/arch/mips/include/asm/fw/fw.h
@@ -10,21 +10,6 @@
#include <asm/bootinfo.h> /* For cleaner code... */
-enum fw_memtypes {
- fw_dontuse,
- fw_code,
- fw_free,
-};
-
-typedef struct {
- unsigned long base; /* Within KSEG0 */
- unsigned int size; /* bytes */
- enum fw_memtypes type; /* fw_memtypes */
-} fw_memblock_t;
-
-/* Maximum number of memory block descriptors. */
-#define FW_MAX_MEMBLOCKS 32
-
extern int fw_argc;
extern int *_fw_argv;
extern int *_fw_envp;
@@ -38,7 +23,6 @@ extern int *_fw_envp;
extern void fw_init_cmdline(void);
extern char *fw_getcmdline(void);
-extern fw_memblock_t *fw_getmdesc(int);
extern void fw_meminit(void);
extern char *fw_getenv(char *name);
extern unsigned long fw_getenvl(char *name);
diff --git a/arch/mips/mti-malta/malta-memory.c b/arch/mips/mti-malta/malta-memory.c
index b769657..5660cd6 100644
--- a/arch/mips/mti-malta/malta-memory.c
+++ b/arch/mips/mti-malta/malta-memory.c
@@ -21,19 +21,25 @@
#include <asm/sections.h>
#include <asm/fw/fw.h>
-static fw_memblock_t mdesc[FW_MAX_MEMBLOCKS];
-
/* determined physical memory size, not overridden by command line args */
unsigned long physical_memsize = 0L;
-fw_memblock_t * __init fw_getmdesc(int eva)
+static void free_init_pages_eva_malta(void *begin, void *end)
+{
+ free_init_pages("unused kernel", __pa_symbol((unsigned long *)begin),
+ __pa_symbol((unsigned long *)end));
+}
+
+void __init fw_meminit(void)
{
char *memsize_str, *ememsize_str = NULL, *ptr;
unsigned long memsize = 0, ememsize = 0;
+ unsigned long kernel_start_phys, kernel_end_phys;
static char cmdline[COMMAND_LINE_SIZE] __initdata;
+ bool eva = config_enabled(CONFIG_EVA);
int tmp;
- /* otherwise look in the environment */
+ free_init_pages_eva = eva ? free_init_pages_eva_malta : NULL;
memsize_str = fw_getenv("memsize");
if (memsize_str) {
@@ -92,15 +98,14 @@ fw_memblock_t * __init fw_getmdesc(int eva)
if (memsize > 0x7fff0000)
memsize = 0x7fff0000;
- memset(mdesc, 0, sizeof(mdesc));
-
- mdesc[0].type = fw_dontuse;
- mdesc[0].base = PHYS_OFFSET;
- mdesc[0].size = 0x00001000;
+ add_memory_region(PHYS_OFFSET, 0x00001000, BOOT_MEM_RESERVED);
- mdesc[1].type = fw_code;
- mdesc[1].base = mdesc[0].base + 0x00001000UL;
- mdesc[1].size = 0x000ef000;
+ /*
+ * YAMON may still be using the region of memory from 0x1000 to 0xfffff
+ * if it has started secondary CPUs.
+ */
+ add_memory_region(PHYS_OFFSET + 0x00001000, 0x000ef000,
+ BOOT_MEM_ROM_DATA);
/*
* The area 0x000f0000-0x000fffff is allocated for BIOS memory by the
@@ -109,59 +114,19 @@ fw_memblock_t * __init fw_getmdesc(int eva)
* This mean that this area can't be used as DMA memory for PCI
* devices.
*/
- mdesc[2].type = fw_dontuse;
- mdesc[2].base = mdesc[0].base + 0x000f0000UL;
- mdesc[2].size = 0x00010000;
-
- mdesc[3].type = fw_dontuse;
- mdesc[3].base = mdesc[0].base + 0x00100000UL;
- mdesc[3].size = CPHYSADDR(PFN_ALIGN((unsigned long)&_end)) -
- 0x00100000UL;
-
- mdesc[4].type = fw_free;
- mdesc[4].base = mdesc[0].base + CPHYSADDR(PFN_ALIGN(&_end));
- mdesc[4].size = memsize - CPHYSADDR(mdesc[4].base);
-
- return &mdesc[0];
-}
-
-static void free_init_pages_eva_malta(void *begin, void *end)
-{
- free_init_pages("unused kernel", __pa_symbol((unsigned long *)begin),
- __pa_symbol((unsigned long *)end));
-}
+ add_memory_region(PHYS_OFFSET + 0x000f0000, 0x00010000,
+ BOOT_MEM_RESERVED);
-static int __init fw_memtype_classify(unsigned int type)
-{
- switch (type) {
- case fw_free:
- return BOOT_MEM_RAM;
- case fw_code:
- return BOOT_MEM_ROM_DATA;
- default:
- return BOOT_MEM_RESERVED;
- }
-}
-
-void __init fw_meminit(void)
-{
- fw_memblock_t *p;
-
- p = fw_getmdesc(config_enabled(CONFIG_EVA));
- free_init_pages_eva = (config_enabled(CONFIG_EVA) ?
- free_init_pages_eva_malta : NULL);
-
- while (p->size) {
- long type;
- unsigned long base, size;
-
- type = fw_memtype_classify(p->type);
- base = p->base;
- size = p->size;
-
- add_memory_region(base, size, type);
- p++;
- }
+ /*
+ * Reserve the memory used by kernel code, and allow the rest of RAM to
+ * be used.
+ */
+ kernel_start_phys = PHYS_OFFSET + 0x00100000;
+ kernel_end_phys = PHYS_OFFSET + CPHYSADDR(PFN_ALIGN(&_end));
+ add_memory_region(kernel_start_phys, kernel_end_phys,
+ BOOT_MEM_RESERVED);
+ add_memory_region(kernel_end_phys, memsize - kernel_end_phys,
+ BOOT_MEM_RAM);
}
void __init prom_free_prom_memory(void)
--
2.4.1
This cap of Malta memory size to 0x7fff0000 was added by commit
e6ca4e5bf114 "MIPS: malta: malta-memory: Add support for the 'ememsize'
variable" as part of support for EVA, with only the cryptic comment
"Last 64K for HIGHMEM arithmetics". However
- EVA is used to avoid highmem, both are not enabled at once which
makes the comment about highmem macros nonsensical.
- I can think of no good reason for it, and nor could anyone else I
asked.
So remove this memsize limit.
Signed-off-by: Paul Burton <[email protected]>
---
arch/mips/mti-malta/malta-memory.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/arch/mips/mti-malta/malta-memory.c b/arch/mips/mti-malta/malta-memory.c
index 5660cd6..831f583 100644
--- a/arch/mips/mti-malta/malta-memory.c
+++ b/arch/mips/mti-malta/malta-memory.c
@@ -94,10 +94,6 @@ void __init fw_meminit(void)
else
memsize = physical_memsize;
- /* Last 64K for HIGHMEM arithmetics */
- if (memsize > 0x7fff0000)
- memsize = 0x7fff0000;
-
add_memory_region(PHYS_OFFSET, 0x00001000, BOOT_MEM_RESERVED);
/*
--
2.4.1
Move memory configuration to be performed via device tree for the Malta
board. This moves more Malta specific code to malta-dtshim.c, leaving
the rest of the mti-malta code a little more board-agnostic. This will
be useful to share more code between boards, with the device tree
providing the board specifics as intended.
Since we can't rely upon Malta boards running a bootloader capable of
handling devictrees & filling in the required information, the
malta_dt_shim code is extended to consume the (e)memsize variables
provided as part of the bootloader environment (or on the kernel command
line) then generate the DT memory node using the provided values.
Signed-off-by: Paul Burton <[email protected]>
---
arch/mips/boot/dts/mti/malta.dts | 4 ++
arch/mips/mti-malta/malta-dtshim.c | 104 +++++++++++++++++++++++++++++++++++++
arch/mips/mti-malta/malta-memory.c | 88 -------------------------------
3 files changed, 108 insertions(+), 88 deletions(-)
diff --git a/arch/mips/boot/dts/mti/malta.dts b/arch/mips/boot/dts/mti/malta.dts
index 9720c66..2fe2364 100644
--- a/arch/mips/boot/dts/mti/malta.dts
+++ b/arch/mips/boot/dts/mti/malta.dts
@@ -1,5 +1,9 @@
/dts-v1/;
+/memreserve/ 0x00000000 0x00001000; /* reserved */
+/memreserve/ 0x00001000 0x000ef000; /* YAMON */
+/memreserve/ 0x000f0000 0x00010000; /* PIIX4 ISA memory */
+
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/mips-gic.h>
diff --git a/arch/mips/mti-malta/malta-dtshim.c b/arch/mips/mti-malta/malta-dtshim.c
index ca33201..9074951 100644
--- a/arch/mips/mti-malta/malta-dtshim.c
+++ b/arch/mips/mti-malta/malta-dtshim.c
@@ -20,6 +20,109 @@
static unsigned char fdt_buf[16 << 10] __initdata;
+/* determined physical memory size, not overridden by command line args */
+extern unsigned long physical_memsize;
+
+#define MAX_MEM_ARRAY_ENTRIES 1
+
+static unsigned __init gen_fdt_mem_array(__be32 *mem_array, unsigned long size)
+{
+ unsigned long size_preio;
+ unsigned entries;
+
+ entries = 1;
+ mem_array[0] = cpu_to_be32(PHYS_OFFSET);
+ if (config_enabled(CONFIG_EVA)) {
+ mem_array[1] = cpu_to_be32(PHYS_OFFSET + size);
+ } else {
+ size_preio = min_t(unsigned long, size, 256 << 20);
+ mem_array[1] = cpu_to_be32(PHYS_OFFSET + size_preio);
+ }
+
+ BUG_ON(entries > MAX_MEM_ARRAY_ENTRIES);
+ return entries;
+}
+
+static void __init append_memory(void *fdt, int root_off)
+{
+ __be32 mem_array[2 * MAX_MEM_ARRAY_ENTRIES];
+ unsigned long memsize;
+ unsigned mem_entries;
+ int i, err, mem_off;
+ char *var, param_name[10], *var_names[] = {
+ "ememsize", "memsize",
+ };
+
+ /* if a memory node already exists, leave it alone */
+ mem_off = fdt_path_offset(fdt, "/memory");
+ if (mem_off >= 0)
+ return;
+
+ /* find memory size from the bootloader environment */
+ for (i = 0; i < ARRAY_SIZE(var_names); i++) {
+ var = fw_getenv(var_names[i]);
+ if (!var)
+ continue;
+
+ err = kstrtoul(var, 0, &physical_memsize);
+ if (!err)
+ break;
+
+ pr_warn("Failed to read the '%s' env variable '%s'\n",
+ var_names[i], var);
+ }
+
+ if (!physical_memsize) {
+ pr_warn("The bootloader didn't provide memsize: defaulting to 32MB\n");
+ physical_memsize = 32 << 20;
+ }
+
+ if (config_enabled(CONFIG_CPU_BIG_ENDIAN)) {
+ /*
+ * SOC-it swaps, or perhaps doesn't swap, when DMA'ing
+ * the last word of physical memory.
+ */
+ physical_memsize -= PAGE_SIZE;
+ }
+
+ /* default to using all available RAM */
+ memsize = physical_memsize;
+
+ /* allow the user to override the usable memory */
+ for (i = 0; i < ARRAY_SIZE(var_names); i++) {
+ snprintf(param_name, sizeof(param_name), "%s=", var_names[i]);
+ var = strstr(arcs_cmdline, param_name);
+ if (!var)
+ continue;
+
+ memsize = memparse(var + strlen(param_name), NULL);
+ }
+
+ /* if the user says there's more RAM than we thought, believe them */
+ physical_memsize = max_t(unsigned long, physical_memsize, memsize);
+
+ /* append memory to the DT */
+ mem_off = fdt_add_subnode(fdt, root_off, "memory");
+ if (mem_off < 0)
+ panic("Unable to add memory node to DT: %d", mem_off);
+
+ err = fdt_setprop_string(fdt, mem_off, "device_type", "memory");
+ if (err)
+ panic("Unable to set memory node device_type: %d", err);
+
+ mem_entries = gen_fdt_mem_array(mem_array, physical_memsize);
+ err = fdt_setprop(fdt, mem_off, "reg", mem_array,
+ mem_entries * 2 * sizeof(mem_array[0]));
+ if (err)
+ panic("Unable to set memory regs property: %d", err);
+
+ mem_entries = gen_fdt_mem_array(mem_array, memsize);
+ err = fdt_setprop(fdt, mem_off, "linux,usable-memory", mem_array,
+ mem_entries * 2 * sizeof(mem_array[0]));
+ if (err)
+ panic("Unable to set linux,usable-memory property: %d", err);
+}
+
static void __init remove_gic(void *fdt)
{
int err, gic_off, i8259_off, cpu_off;
@@ -118,6 +221,7 @@ void __init *malta_dt_shim(void *fdt)
if (strncmp(compat, "mti,malta", len))
return fdt;
+ append_memory(fdt_buf, root_off);
remove_gic(fdt_buf);
err = fdt_pack(fdt_buf);
diff --git a/arch/mips/mti-malta/malta-memory.c b/arch/mips/mti-malta/malta-memory.c
index 831f583..5203241 100644
--- a/arch/mips/mti-malta/malta-memory.c
+++ b/arch/mips/mti-malta/malta-memory.c
@@ -32,97 +32,9 @@ static void free_init_pages_eva_malta(void *begin, void *end)
void __init fw_meminit(void)
{
- char *memsize_str, *ememsize_str = NULL, *ptr;
- unsigned long memsize = 0, ememsize = 0;
- unsigned long kernel_start_phys, kernel_end_phys;
- static char cmdline[COMMAND_LINE_SIZE] __initdata;
bool eva = config_enabled(CONFIG_EVA);
- int tmp;
free_init_pages_eva = eva ? free_init_pages_eva_malta : NULL;
-
- memsize_str = fw_getenv("memsize");
- if (memsize_str) {
- tmp = kstrtoul(memsize_str, 0, &memsize);
- if (tmp)
- pr_warn("Failed to read the 'memsize' env variable.\n");
- }
- if (eva) {
- /* Look for ememsize for EVA */
- ememsize_str = fw_getenv("ememsize");
- if (ememsize_str) {
- tmp = kstrtoul(ememsize_str, 0, &ememsize);
- if (tmp)
- pr_warn("Failed to read the 'ememsize' env variable.\n");
- }
- }
- if (!memsize && !ememsize) {
- pr_warn("memsize not set in YAMON, set to default (32Mb)\n");
- physical_memsize = 0x02000000;
- } else {
- if (memsize > (256 << 20)) { /* memsize should be capped to 256M */
- pr_warn("Unsupported memsize value (0x%lx) detected! "
- "Using 0x10000000 (256M) instead\n",
- memsize);
- memsize = 256 << 20;
- }
- /* If ememsize is set, then set physical_memsize to that */
- physical_memsize = ememsize ? : memsize;
- }
-
-#ifdef CONFIG_CPU_BIG_ENDIAN
- /* SOC-it swaps, or perhaps doesn't swap, when DMA'ing the last
- word of physical memory */
- physical_memsize -= PAGE_SIZE;
-#endif
-
- /* Check the command line for a memsize directive that overrides
- the physical/default amount */
- strcpy(cmdline, arcs_cmdline);
- ptr = strstr(cmdline, "memsize=");
- if (ptr && (ptr != cmdline) && (*(ptr - 1) != ' '))
- ptr = strstr(ptr, " memsize=");
- /* And now look for ememsize */
- if (eva) {
- ptr = strstr(cmdline, "ememsize=");
- if (ptr && (ptr != cmdline) && (*(ptr - 1) != ' '))
- ptr = strstr(ptr, " ememsize=");
- }
-
- if (ptr)
- memsize = memparse(ptr + 8 + (eva ? 1 : 0), &ptr);
- else
- memsize = physical_memsize;
-
- add_memory_region(PHYS_OFFSET, 0x00001000, BOOT_MEM_RESERVED);
-
- /*
- * YAMON may still be using the region of memory from 0x1000 to 0xfffff
- * if it has started secondary CPUs.
- */
- add_memory_region(PHYS_OFFSET + 0x00001000, 0x000ef000,
- BOOT_MEM_ROM_DATA);
-
- /*
- * The area 0x000f0000-0x000fffff is allocated for BIOS memory by the
- * south bridge and PCI access always forwarded to the ISA Bus and
- * BIOSCS# is always generated.
- * This mean that this area can't be used as DMA memory for PCI
- * devices.
- */
- add_memory_region(PHYS_OFFSET + 0x000f0000, 0x00010000,
- BOOT_MEM_RESERVED);
-
- /*
- * Reserve the memory used by kernel code, and allow the rest of RAM to
- * be used.
- */
- kernel_start_phys = PHYS_OFFSET + 0x00100000;
- kernel_end_phys = PHYS_OFFSET + CPHYSADDR(PFN_ALIGN(&_end));
- add_memory_region(kernel_start_phys, kernel_end_phys,
- BOOT_MEM_RESERVED);
- add_memory_region(kernel_end_phys, memsize - kernel_end_phys,
- BOOT_MEM_RAM);
}
void __init prom_free_prom_memory(void)
--
2.4.1
If the system has more than 256MB RAM (ie. more than will fit in the
unmapped kseg[01] regions before the I/O hole) then set up a region to
use that memory via its alias in the upper half of the physical address
space, where the I/O hole is not present. This allows highmem to be used
on Malta without needing to manually specify mem= parameters on the
kernel command line.
Signed-off-by: Paul Burton <[email protected]>
---
arch/mips/mti-malta/malta-dtshim.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/mips/mti-malta/malta-dtshim.c b/arch/mips/mti-malta/malta-dtshim.c
index 9074951..6320b44 100644
--- a/arch/mips/mti-malta/malta-dtshim.c
+++ b/arch/mips/mti-malta/malta-dtshim.c
@@ -23,7 +23,7 @@ static unsigned char fdt_buf[16 << 10] __initdata;
/* determined physical memory size, not overridden by command line args */
extern unsigned long physical_memsize;
-#define MAX_MEM_ARRAY_ENTRIES 1
+#define MAX_MEM_ARRAY_ENTRIES 2
static unsigned __init gen_fdt_mem_array(__be32 *mem_array, unsigned long size)
{
@@ -37,6 +37,12 @@ static unsigned __init gen_fdt_mem_array(__be32 *mem_array, unsigned long size)
} else {
size_preio = min_t(unsigned long, size, 256 << 20);
mem_array[1] = cpu_to_be32(PHYS_OFFSET + size_preio);
+
+ if (size > size_preio) {
+ entries++;
+ mem_array[2] = cpu_to_be32(0x80000000 + size_preio);
+ mem_array[3] = cpu_to_be32(size - size_preio);
+ }
}
BUG_ON(entries > MAX_MEM_ARRAY_ENTRIES);
--
2.4.1
On Fri, May 22, 2015 at 04:51:04PM +0100, Paul Burton wrote:
> On Malta, some IRQs are still referenced by hardcoded numbers relative
> to MIPS_GIC_IRQ_BASE. When gic_init is called to register the GIC
> without using device tree the irqbase argument allows this base to be
> used. When the GIC is probed using device tree however the base is not
> specified. This leads to conflicts between the GIC interrupts and other
> interrupt controllers.
>
> TODO: convert Malta (& SEAD3) to drop the hardcoded numbers instead
This will never be seen again. :-P Why not just go ahead and do it as separate
patch(es) in this series?
thx,
Jason.
> Signed-off-by: Paul Burton <[email protected]>
> ---
>
> drivers/irqchip/irq-mips-gic.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
> index 57f09cb..697f340 100644
> --- a/drivers/irqchip/irq-mips-gic.c
> +++ b/drivers/irqchip/irq-mips-gic.c
> @@ -858,7 +858,7 @@ static int __init gic_of_init(struct device_node *node,
> write_gcr_gic_base(gic_base | CM_GCR_GIC_BASE_GICEN_MSK);
> gic_present = true;
>
> - __gic_init(gic_base, gic_len, cpu_vec, 0, node);
> + __gic_init(gic_base, gic_len, cpu_vec, MIPS_GIC_IRQ_BASE, node);
>
> return 0;
> }
> --
> 2.4.1
>
On Fri, May 22, 2015 at 10:50 AM, Paul Burton <[email protected]> wrote:
> This series begins converting the MIPS Malta board to use device tree,
> which is done with a few goals in mind:
>
> - To modernise the Malta board support, providing a cleaner example to
> people referencing it when bringing up new boards and reducing the
> amount of code they need to write.
>
> - To make the code at the board level more generic with the eventual
> aim of sharing it between multiple boards & allowing for
> multi-platform kernel binaries. Although this series doesn't result
> in the kernel reaching those goals, it is a step in that direction.
>
> - To result in a more maintainable kernel through a combination of the
> above.
How would I go about testing this under qemu?
(Especially the "more than 256 megs ram" part. :)
Rob
On Mon, May 25, 2015 at 02:59:31AM -0500, Rob Landley wrote:
> On Fri, May 22, 2015 at 10:50 AM, Paul Burton <[email protected]> wrote:
> > This series begins converting the MIPS Malta board to use device tree,
> > which is done with a few goals in mind:
> >
> > - To modernise the Malta board support, providing a cleaner example to
> > people referencing it when bringing up new boards and reducing the
> > amount of code they need to write.
> >
> > - To make the code at the board level more generic with the eventual
> > aim of sharing it between multiple boards & allowing for
> > multi-platform kernel binaries. Although this series doesn't result
> > in the kernel reaching those goals, it is a step in that direction.
> >
> > - To result in a more maintainable kernel through a combination of the
> > above.
>
> How would I go about testing this under qemu?
>
> (Especially the "more than 256 megs ram" part. :)
Hi Rob,
With the series applied you can start from malta_defconfig, enable
CONFIG_HIGHMEM, build your kernel then run QEMU like so:
$ qemu-system-mipsel -kernel vmlinux -m 1G -append memsize=1G -serial stdio
If you apply this patch to QEMU:
https://www.mail-archive.com/[email protected]/msg297902.html
(or if you use a real board) then you can omit the memsize argument from
the kernel command line (ie. the -append) and just do:
$ qemu-system-mipsel -kernel vmlinux -m 1G -serial stdio
The kernel will then retrieve the correct memory size from the
bootloader-provided environment and make use of all the available RAM.
Thanks,
Paul
[ + Arnd who has been reviewing/acking of_serial.c changes ]
On 05/22/2015 11:51 AM, Paul Burton wrote:
> If the address provided for the UART is of an I/O port rather than
> a regular memory address, then set the port iotype appropriately and
> write the address to iobase rather than mapbase.
>
> Signed-off-by: Paul Burton <[email protected]>
> ---
>
> drivers/tty/serial/of_serial.c | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/tty/serial/of_serial.c b/drivers/tty/serial/of_serial.c
> index 137381e..ccff9ba 100644
> --- a/drivers/tty/serial/of_serial.c
> +++ b/drivers/tty/serial/of_serial.c
> @@ -110,7 +110,12 @@ static int of_platform_serial_setup(struct platform_device *ofdev,
>
> port->irq = irq_of_parse_and_map(np, 0);
> port->iotype = UPIO_MEM;
> - if (of_property_read_u32(np, "reg-io-width", &prop) == 0) {
> +
> + if (resource.flags & IORESOURCE_IO) {
> + port->iotype = UPIO_PORT;
> + port->iobase = port->mapbase;
> + port->mapbase = 0;
> + } else if (of_property_read_u32(np, "reg-io-width", &prop) == 0) {
> switch (prop) {
> case 1:
> port->iotype = UPIO_MEM;
>