This patchset fixexs this and do some cosmetic cleanup in the clocksource
driver for mach-gemini.
timer1 is used for clockevent
timer3 for free running timer, scheduler clock source.
The work is based on a patch found on openwrt.org in
target/linux/gemini/patches-3.18/160-gemini-timers.patch
Hans Ulli
We need the offset for the timer registers in driver only.
So move this out of hardware.h
Signed-off-by: Hans Ulli Kroll <[email protected]>
---
arch/arm/mach-gemini/include/mach/hardware.h | 3 ---
arch/arm/mach-gemini/time.c | 4 ++++
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-gemini/include/mach/hardware.h b/arch/arm/mach-gemini/include/mach/hardware.h
index 98e7b0f..f0390f1 100644
--- a/arch/arm/mach-gemini/include/mach/hardware.h
+++ b/arch/arm/mach-gemini/include/mach/hardware.h
@@ -57,9 +57,6 @@
#define GEMINI_USB1_BASE 0x69000000
#define GEMINI_BIG_ENDIAN_BASE 0x80000000
-#define GEMINI_TIMER1_BASE GEMINI_TIMER_BASE
-#define GEMINI_TIMER2_BASE (GEMINI_TIMER_BASE + 0x10)
-#define GEMINI_TIMER3_BASE (GEMINI_TIMER_BASE + 0x20)
/*
* UART Clock when System clk is 150MHz
diff --git a/arch/arm/mach-gemini/time.c b/arch/arm/mach-gemini/time.c
index 0a63c4d2..d0bbd2f 100644
--- a/arch/arm/mach-gemini/time.c
+++ b/arch/arm/mach-gemini/time.c
@@ -19,6 +19,10 @@
/*
* Register definitions for the timers
*/
+#define GEMINI_TIMER1_BASE GEMINI_TIMER_BASE
+#define GEMINI_TIMER2_BASE (GEMINI_TIMER_BASE + 0x10)
+#define GEMINI_TIMER3_BASE (GEMINI_TIMER_BASE + 0x20)
+
#define TIMER_COUNT(BASE_ADDR) (BASE_ADDR + 0x00)
#define TIMER_LOAD(BASE_ADDR) (BASE_ADDR + 0x04)
#define TIMER_MATCH1(BASE_ADDR) (BASE_ADDR + 0x08)
--
2.4.2
For better code readability move IO_ADDRESS() into register definitions
Signed-off-by: Hans Ulli Kroll <[email protected]>
---
arch/arm/mach-gemini/time.c | 40 ++++++++++++++++++++--------------------
1 file changed, 20 insertions(+), 20 deletions(-)
diff --git a/arch/arm/mach-gemini/time.c b/arch/arm/mach-gemini/time.c
index d0bbd2f..76e3ca7 100644
--- a/arch/arm/mach-gemini/time.c
+++ b/arch/arm/mach-gemini/time.c
@@ -23,11 +23,11 @@
#define GEMINI_TIMER2_BASE (GEMINI_TIMER_BASE + 0x10)
#define GEMINI_TIMER3_BASE (GEMINI_TIMER_BASE + 0x20)
-#define TIMER_COUNT(BASE_ADDR) (BASE_ADDR + 0x00)
-#define TIMER_LOAD(BASE_ADDR) (BASE_ADDR + 0x04)
-#define TIMER_MATCH1(BASE_ADDR) (BASE_ADDR + 0x08)
-#define TIMER_MATCH2(BASE_ADDR) (BASE_ADDR + 0x0C)
-#define TIMER_CR(BASE_ADDR) (BASE_ADDR + 0x30)
+#define TIMER_COUNT(BASE_ADDR) (IO_ADDRESS(BASE_ADDR) + 0x00)
+#define TIMER_LOAD(BASE_ADDR) (IO_ADDRESS(BASE_ADDR) + 0x04)
+#define TIMER_MATCH1(BASE_ADDR) (IO_ADDRESS(BASE_ADDR) + 0x08)
+#define TIMER_MATCH2(BASE_ADDR) (IO_ADDRESS(BASE_ADDR) + 0x0C)
+#define TIMER_CR(BASE_ADDR) (IO_ADDRESS(BASE_ADDR) + 0x30)
#define TIMER_1_CR_ENABLE (1 << 0)
#define TIMER_1_CR_CLOCK (1 << 1)
@@ -46,19 +46,19 @@ static int gemini_timer_set_next_event(unsigned long cycles,
{
u32 cr;
- cr = readl(TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE)));
+ cr = readl(TIMER_CR(GEMINI_TIMER_BASE));
/* This may be overdoing it, feel free to test without this */
cr &= ~TIMER_2_CR_ENABLE;
cr &= ~TIMER_2_CR_INT;
- writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE)));
+ writel(cr, TIMER_CR(GEMINI_TIMER_BASE));
/* Set next event */
- writel(cycles, TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER2_BASE)));
- writel(cycles, TIMER_LOAD(IO_ADDRESS(GEMINI_TIMER2_BASE)));
+ writel(cycles, TIMER_COUNT(GEMINI_TIMER2_BASE));
+ writel(cycles, TIMER_LOAD(GEMINI_TIMER2_BASE));
cr |= TIMER_2_CR_ENABLE;
cr |= TIMER_2_CR_INT;
- writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE)));
+ writel(cr, TIMER_CR(GEMINI_TIMER_BASE));
return 0;
}
@@ -73,13 +73,13 @@ static void gemini_timer_set_mode(enum clock_event_mode mode,
case CLOCK_EVT_MODE_PERIODIC:
/* Start the timer */
writel(period,
- TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER2_BASE)));
+ TIMER_COUNT(GEMINI_TIMER2_BASE));
writel(period,
- TIMER_LOAD(IO_ADDRESS(GEMINI_TIMER2_BASE)));
- cr = readl(TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE)));
+ TIMER_LOAD(GEMINI_TIMER2_BASE));
+ cr = readl(TIMER_CR(GEMINI_TIMER_BASE));
cr |= TIMER_2_CR_ENABLE;
cr |= TIMER_2_CR_INT;
- writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE)));
+ writel(cr, TIMER_CR(GEMINI_TIMER_BASE));
break;
case CLOCK_EVT_MODE_ONESHOT:
case CLOCK_EVT_MODE_UNUSED:
@@ -89,10 +89,10 @@ static void gemini_timer_set_mode(enum clock_event_mode mode,
* Disable also for oneshot: the set_next() call will
* arm the timer instead.
*/
- cr = readl(TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE)));
+ cr = readl(TIMER_CR(GEMINI_TIMER_BASE));
cr &= ~TIMER_2_CR_ENABLE;
cr &= ~TIMER_2_CR_INT;
- writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE)));
+ writel(cr, TIMER_CR(GEMINI_TIMER_BASE));
break;
default:
break;
@@ -160,10 +160,10 @@ void __init gemini_timer_init(void)
setup_irq(IRQ_TIMER2, &gemini_timer_irq);
/* Enable and use TIMER1 as clock source */
- writel(0xffffffff, TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER1_BASE)));
- writel(0xffffffff, TIMER_LOAD(IO_ADDRESS(GEMINI_TIMER1_BASE)));
- writel(TIMER_1_CR_ENABLE, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE)));
- if (clocksource_mmio_init(TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER1_BASE)),
+ writel(0xffffffff, TIMER_COUNT(GEMINI_TIMER1_BASE));
+ writel(0xffffffff, TIMER_LOAD(GEMINI_TIMER1_BASE));
+ writel(TIMER_1_CR_ENABLE, TIMER_CR(GEMINI_TIMER_BASE));
+ if (clocksource_mmio_init(TIMER_COUNT(GEMINI_TIMER1_BASE),
"TIMER1", tick_rate, 300, 32,
clocksource_mmio_readl_up))
pr_err("timer: failed to initialize gemini clock source\n");
--
2.4.2
For earch timer function we have intr state and mask register.
Add control bits up/down counting for each timer
Signed-off-by: Hans Ulli Kroll <[email protected]>
---
arch/arm/mach-gemini/time.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm/mach-gemini/time.c b/arch/arm/mach-gemini/time.c
index 76e3ca7..a8604a3 100644
--- a/arch/arm/mach-gemini/time.c
+++ b/arch/arm/mach-gemini/time.c
@@ -28,6 +28,8 @@
#define TIMER_MATCH1(BASE_ADDR) (IO_ADDRESS(BASE_ADDR) + 0x08)
#define TIMER_MATCH2(BASE_ADDR) (IO_ADDRESS(BASE_ADDR) + 0x0C)
#define TIMER_CR(BASE_ADDR) (IO_ADDRESS(BASE_ADDR) + 0x30)
+#define TIMER_INTR_STATE (IO_ADDRESS(GEMINI_TIMER_BASE) + 0x34)
+#define TIMER_INTR_MASK (IO_ADDRESS(GEMINI_TIMER_BASE) + 0x38)
#define TIMER_1_CR_ENABLE (1 << 0)
#define TIMER_1_CR_CLOCK (1 << 1)
@@ -38,6 +40,21 @@
#define TIMER_3_CR_ENABLE (1 << 6)
#define TIMER_3_CR_CLOCK (1 << 7)
#define TIMER_3_CR_INT (1 << 8)
+#define TIMER_1_CR_UPDOWN (1 << 9)
+#define TIMER_2_CR_UPDOWN (1 << 10)
+#define TIMER_3_CR_UPDOWN (1 << 11)
+
+#define TIMER_1_INT_MATCH1 (1 << 0)
+#define TIMER_1_INT_MATCH2 (1 << 1)
+#define TIMER_1_INT_OVERFLOW (1 << 2)
+#define TIMER_2_INT_MATCH1 (1 << 3)
+#define TIMER_2_INT_MATCH2 (1 << 4)
+#define TIMER_2_INT_OVERFLOW (1 << 5)
+#define TIMER_3_INT_MATCH1 (1 << 6)
+#define TIMER_3_INT_MATCH2 (1 << 7)
+#define TIMER_3_INT_OVERFLOW (1 << 8)
+#define TIMER_INT_ALL_MASK 0x1ff
+
static unsigned int tick_rate;
--
2.4.2
The TIMER_CR register control all three timer. No need for a index.
Signed-off-by: Hans Ulli Kroll <[email protected]>
---
arch/arm/mach-gemini/time.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-gemini/time.c b/arch/arm/mach-gemini/time.c
index a8604a3..e919b96 100644
--- a/arch/arm/mach-gemini/time.c
+++ b/arch/arm/mach-gemini/time.c
@@ -27,7 +27,7 @@
#define TIMER_LOAD(BASE_ADDR) (IO_ADDRESS(BASE_ADDR) + 0x04)
#define TIMER_MATCH1(BASE_ADDR) (IO_ADDRESS(BASE_ADDR) + 0x08)
#define TIMER_MATCH2(BASE_ADDR) (IO_ADDRESS(BASE_ADDR) + 0x0C)
-#define TIMER_CR(BASE_ADDR) (IO_ADDRESS(BASE_ADDR) + 0x30)
+#define TIMER_CR (IO_ADDRESS(GEMINI_TIMER_BASE) + 0x30)
#define TIMER_INTR_STATE (IO_ADDRESS(GEMINI_TIMER_BASE) + 0x34)
#define TIMER_INTR_MASK (IO_ADDRESS(GEMINI_TIMER_BASE) + 0x38)
@@ -63,19 +63,19 @@ static int gemini_timer_set_next_event(unsigned long cycles,
{
u32 cr;
- cr = readl(TIMER_CR(GEMINI_TIMER_BASE));
+ cr = readl(TIMER_CR);
/* This may be overdoing it, feel free to test without this */
cr &= ~TIMER_2_CR_ENABLE;
cr &= ~TIMER_2_CR_INT;
- writel(cr, TIMER_CR(GEMINI_TIMER_BASE));
+ writel(cr, TIMER_CR);
/* Set next event */
writel(cycles, TIMER_COUNT(GEMINI_TIMER2_BASE));
writel(cycles, TIMER_LOAD(GEMINI_TIMER2_BASE));
cr |= TIMER_2_CR_ENABLE;
cr |= TIMER_2_CR_INT;
- writel(cr, TIMER_CR(GEMINI_TIMER_BASE));
+ writel(cr, TIMER_CR);
return 0;
}
@@ -93,10 +93,10 @@ static void gemini_timer_set_mode(enum clock_event_mode mode,
TIMER_COUNT(GEMINI_TIMER2_BASE));
writel(period,
TIMER_LOAD(GEMINI_TIMER2_BASE));
- cr = readl(TIMER_CR(GEMINI_TIMER_BASE));
+ cr = readl(TIMER_CR);
cr |= TIMER_2_CR_ENABLE;
cr |= TIMER_2_CR_INT;
- writel(cr, TIMER_CR(GEMINI_TIMER_BASE));
+ writel(cr, TIMER_CR);
break;
case CLOCK_EVT_MODE_ONESHOT:
case CLOCK_EVT_MODE_UNUSED:
@@ -106,10 +106,10 @@ static void gemini_timer_set_mode(enum clock_event_mode mode,
* Disable also for oneshot: the set_next() call will
* arm the timer instead.
*/
- cr = readl(TIMER_CR(GEMINI_TIMER_BASE));
+ cr = readl(TIMER_CR);
cr &= ~TIMER_2_CR_ENABLE;
cr &= ~TIMER_2_CR_INT;
- writel(cr, TIMER_CR(GEMINI_TIMER_BASE));
+ writel(cr, TIMER_CR);
break;
default:
break;
@@ -179,7 +179,7 @@ void __init gemini_timer_init(void)
/* Enable and use TIMER1 as clock source */
writel(0xffffffff, TIMER_COUNT(GEMINI_TIMER1_BASE));
writel(0xffffffff, TIMER_LOAD(GEMINI_TIMER1_BASE));
- writel(TIMER_1_CR_ENABLE, TIMER_CR(GEMINI_TIMER_BASE));
+ writel(TIMER_1_CR_ENABLE, TIMER_CR);
if (clocksource_mmio_init(TIMER_COUNT(GEMINI_TIMER1_BASE),
"TIMER1", tick_rate, 300, 32,
clocksource_mmio_readl_up))
--
2.4.2
This patch is based on openwrt patch found in
target/linux/gemini/patches-3.18/160-gemini-timers.patch
It removes usage of timer 2 as clockevent timer and uses
timer 1.
Also setup the needed register for interrupt handling missed in
the initial patch
Signed-off-by: Hans Ulli Kroll <[email protected]>
---
arch/arm/mach-gemini/time.c | 106 ++++++++++++++++++++++++++------------------
1 file changed, 62 insertions(+), 44 deletions(-)
diff --git a/arch/arm/mach-gemini/time.c b/arch/arm/mach-gemini/time.c
index e919b96..29ec2c3 100644
--- a/arch/arm/mach-gemini/time.c
+++ b/arch/arm/mach-gemini/time.c
@@ -63,19 +63,11 @@ static int gemini_timer_set_next_event(unsigned long cycles,
{
u32 cr;
- cr = readl(TIMER_CR);
-
- /* This may be overdoing it, feel free to test without this */
- cr &= ~TIMER_2_CR_ENABLE;
- cr &= ~TIMER_2_CR_INT;
- writel(cr, TIMER_CR);
-
- /* Set next event */
- writel(cycles, TIMER_COUNT(GEMINI_TIMER2_BASE));
- writel(cycles, TIMER_LOAD(GEMINI_TIMER2_BASE));
- cr |= TIMER_2_CR_ENABLE;
- cr |= TIMER_2_CR_INT;
- writel(cr, TIMER_CR);
+ /* Setup the match register */
+ cr = readl(TIMER_COUNT(GEMINI_TIMER1_BASE));
+ writel(cr + cycles, TIMER_MATCH1(GEMINI_TIMER1_BASE));
+ if (readl(TIMER_COUNT(GEMINI_TIMER1_BASE)) - cr > cycles)
+ return -ETIME;
return 0;
}
@@ -87,32 +79,55 @@ static void gemini_timer_set_mode(enum clock_event_mode mode,
u32 cr;
switch (mode) {
- case CLOCK_EVT_MODE_PERIODIC:
- /* Start the timer */
- writel(period,
- TIMER_COUNT(GEMINI_TIMER2_BASE));
- writel(period,
- TIMER_LOAD(GEMINI_TIMER2_BASE));
+ case CLOCK_EVT_MODE_PERIODIC:
+ /* Stop timer and interrupt. */
+ cr = readl(TIMER_CR);
+ cr &= ~(TIMER_1_CR_ENABLE | TIMER_1_CR_INT);
+ writel(cr, TIMER_CR);
+
+ /* Setup timer to fire at 1/HZ intervals. */
+ cr = 0xffffffff - (period - 1);
+ writel(cr, TIMER_COUNT(GEMINI_TIMER1_BASE));
+ writel(cr, TIMER_LOAD(GEMINI_TIMER1_BASE));
+
+ /* enable interrupt on overflaw */
+ cr = readl(TIMER_INTR_MASK);
+ cr &= ~(TIMER_1_INT_MATCH1 | TIMER_1_INT_MATCH2);
+ cr |= TIMER_1_INT_OVERFLOW;
+ writel(cr, TIMER_INTR_MASK);
+
+ /* start the timer */
cr = readl(TIMER_CR);
- cr |= TIMER_2_CR_ENABLE;
- cr |= TIMER_2_CR_INT;
+ cr |= TIMER_1_CR_ENABLE | TIMER_1_CR_INT;
writel(cr, TIMER_CR);
break;
+
case CLOCK_EVT_MODE_ONESHOT:
case CLOCK_EVT_MODE_UNUSED:
- case CLOCK_EVT_MODE_SHUTDOWN:
- case CLOCK_EVT_MODE_RESUME:
- /*
- * Disable also for oneshot: the set_next() call will
- * arm the timer instead.
- */
+ case CLOCK_EVT_MODE_SHUTDOWN:
+ /* Stop timer and interrupt. */
+ cr = readl(TIMER_CR);
+ cr &= ~(TIMER_1_CR_ENABLE | TIMER_1_CR_INT);
+ writel(cr, TIMER_CR);
+
+ /* Setup counter start from 0 */
+ writel(0, TIMER_COUNT(GEMINI_TIMER1_BASE));
+ writel(0, TIMER_LOAD(GEMINI_TIMER1_BASE));
+
+ /* enable interrupt */
+ cr = readl(TIMER_INTR_MASK);
+ cr &= ~(TIMER_1_INT_OVERFLOW | TIMER_1_INT_MATCH2);
+ cr |= TIMER_1_INT_MATCH1;
+ writel(cr, TIMER_INTR_MASK);
+
+ /* start the timer */
cr = readl(TIMER_CR);
- cr &= ~TIMER_2_CR_ENABLE;
- cr &= ~TIMER_2_CR_INT;
+ cr |= TIMER_1_CR_ENABLE;
writel(cr, TIMER_CR);
break;
- default:
- break;
+
+ case CLOCK_EVT_MODE_RESUME:
+ break;
}
}
@@ -120,6 +135,7 @@ static void gemini_timer_set_mode(enum clock_event_mode mode,
static struct clock_event_device gemini_clockevent = {
.name = "TIMER2",
.rating = 300, /* Reasonably fast and accurate clock event */
+ .shift = 32,
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
.set_next_event = gemini_timer_set_next_event,
.set_mode = gemini_timer_set_mode,
@@ -172,20 +188,22 @@ void __init gemini_timer_init(void)
}
/*
- * Make irqs happen for the system timer
+ * Reset the interrupt mask and status
+ */
+ writel(TIMER_INT_ALL_MASK, TIMER_INTR_MASK);
+ writel(0, TIMER_INTR_STATE);
+ writel(TIMER_1_CR_UPDOWN | TIMER_3_CR_ENABLE | TIMER_3_CR_UPDOWN,
+ TIMER_CR);
+
+ /*
+ * Setup clockevent timer (interrupt-driven.)
*/
- setup_irq(IRQ_TIMER2, &gemini_timer_irq);
-
- /* Enable and use TIMER1 as clock source */
- writel(0xffffffff, TIMER_COUNT(GEMINI_TIMER1_BASE));
- writel(0xffffffff, TIMER_LOAD(GEMINI_TIMER1_BASE));
- writel(TIMER_1_CR_ENABLE, TIMER_CR);
- if (clocksource_mmio_init(TIMER_COUNT(GEMINI_TIMER1_BASE),
- "TIMER1", tick_rate, 300, 32,
- clocksource_mmio_readl_up))
- pr_err("timer: failed to initialize gemini clock source\n");
-
- /* Configure and register the clockevent */
+ writel(0, TIMER_COUNT(GEMINI_TIMER1_BASE));
+ writel(0, TIMER_LOAD(GEMINI_TIMER1_BASE));
+ writel(0, TIMER_MATCH1(GEMINI_TIMER1_BASE));
+ writel(0, TIMER_MATCH2(GEMINI_TIMER1_BASE));
+ setup_irq(IRQ_TIMER1, &gemini_timer_irq);
+ gemini_clockevent.cpumask = cpumask_of(0);
clockevents_config_and_register(&gemini_clockevent, tick_rate,
1, 0xffffffff);
}
--
2.4.2
This patch is based on openwrt patch found in
target/linux/gemini/patches-3.18/160-gemini-timers.patch
It setups a free running timer (timer3) for scheduler clock
Signed-off-by: Hans Ulli Kroll <[email protected]>
---
arch/arm/mach-gemini/time.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm/mach-gemini/time.c b/arch/arm/mach-gemini/time.c
index 29ec2c3..e419dd4 100644
--- a/arch/arm/mach-gemini/time.c
+++ b/arch/arm/mach-gemini/time.c
@@ -15,6 +15,8 @@
#include <asm/mach/time.h>
#include <linux/clockchips.h>
#include <linux/clocksource.h>
+#include <linux/sched_clock.h>
+
/*
* Register definitions for the timers
@@ -58,6 +60,11 @@
static unsigned int tick_rate;
+static u64 notrace gemini_read_sched_clock(void)
+{
+ return readl(TIMER_COUNT(GEMINI_TIMER3_BASE));
+}
+
static int gemini_timer_set_next_event(unsigned long cycles,
struct clock_event_device *evt)
{
@@ -196,6 +203,19 @@ void __init gemini_timer_init(void)
TIMER_CR);
/*
+ * Setup free-running clocksource timer (interrupts
+ * disabled.)
+ */
+ writel(0, TIMER_COUNT(GEMINI_TIMER3_BASE));
+ writel(0, TIMER_LOAD(GEMINI_TIMER3_BASE));
+ writel(0, TIMER_MATCH1(GEMINI_TIMER3_BASE));
+ writel(0, TIMER_MATCH2(GEMINI_TIMER3_BASE));
+ clocksource_mmio_init(TIMER_COUNT(GEMINI_TIMER3_BASE),
+ "gemini_clocksource", tick_rate,
+ 300, 32, clocksource_mmio_readl_up);
+ sched_clock_register(gemini_read_sched_clock, 32, tick_rate);
+
+ /*
* Setup clockevent timer (interrupt-driven.)
*/
writel(0, TIMER_COUNT(GEMINI_TIMER1_BASE));
--
2.4.2