Power8 Perforence Monitoring Unit (PMU) supports different
sampling modes (SM) Random Instruction Sampling (RIS),
Random Load/Store Facility Sampling (RLS) and Random Branch
Sampling (RBS). This patchset enabled RLS mode to mark
Load/Store instructions to save the memory hierarchy level
(eg: L2, L3) for cache reload. Event used here to sample
is "marked instruction complete".
This patchset exports the hierarchy information to the user via the
perf_mem_data_src object. Patchset is based on and derived from
Sukadev Bhattiprolu work[1]. It exports the memory hierarchy
information only to Power8 processor based system, since
similiar event or modes are not supported in Power7
[1]:https://lkml.org/lkml/2013/10/15/858
perf interface sample. Workload used here is "ebizzy"
# perf report -n --mem-mode --sort=mem,sym,dso,symbol_daddr --stdio
# To display the perf.data header info, please use --header/--header-only options.
#
# Samples: 33 of event 'cpu/mem_access/'
# Total weight : 33
# Sort order : mem,sym,dso,symbol_daddr
#
# Overhead Samples Memory access Symbol Shared Object Data Symbol
# ........ ............ ........................ .................................. ................. .........................................
#
12.12% 4 L2 hit [k] __do_softirq [kernel.kallsyms] [k] softirq_vec+0x8
6.06% 2 L2 hit [k] __schedule [kernel.kallsyms] [k] 0xc0000003bb975df0
6.06% 2 Remote Cache (1 hop) hit [k] scheduler_tick [kernel.kallsyms] [k] 0xc0000003feb1e4b0
3.03% 1 L2 hit [k] __acct_update_integrals [kernel.kallsyms] [k] 0xc0000003b79d8a30
3.03% 1 L2 hit [.] __memcpy_power7 libc-2.17.so [.] 0x0000010021349b00
3.03% 1 L2 hit [.] __memcpy_power7 libc-2.17.so [.] 0x000001002134a030
3.03% 1 L2 hit [k] __mmdrop [kernel.kallsyms] [k] pgtable_cache+0x58
3.03% 1 L2 hit [k] __update_cpu_load [kernel.kallsyms] [k] 0xc0000003feb1dc60
3.03% 1 L2 hit [.] _int_malloc libc-2.17.so [.] 0x00003fff90000090
3.03% 1 L2 hit [k] account_system_time [kernel.kallsyms] [k] 0xc0000003feb08088
.....
Madhavan Srinivasan (8):
powerpc/perf: Remove PME_ prefix for power7 events
powerpc/perf: Export Power8 generic events in sysfs
powerpc/perf: EVENT macro for exporting generic events
powerpc/perf: Add Power8 mem_access event to sysfs
powerpc/perf: Define big-endian version of perf_mem_data_src
powerpc/perf: Export Power8 memory hierarchy info to user space
powerpc/perf: Set data source value
powerpc/perf: cleanup in perf_event_print_debug()
arch/powerpc/include/asm/perf_event_server.h | 4 +-
arch/powerpc/perf/core-book3s.c | 17 ++++-
arch/powerpc/perf/power7-pmu.c | 18 ++---
arch/powerpc/perf/power8-events-list.h | 21 ++++++
arch/powerpc/perf/power8-pmu.c | 98 ++++++++++++++++++++++++++--
include/uapi/linux/perf_event.h | 16 +++++
6 files changed, 155 insertions(+), 19 deletions(-)
create mode 100644 arch/powerpc/perf/power8-events-list.h
--
1.9.1
From: Sukadev Bhattiprolu <[email protected]>
We used the PME_ prefix earlier to avoid some macro/variable name
collisions. We have since changed the way we define/use the event
macros so we no longer need the prefix.
By dropping the prefix, we keep the the event macros consistent with
their official names.
Reported-by: Michael Ellerman <[email protected]>
Signed-off-by: Sukadev Bhattiprolu <[email protected]>
Signed-off-by: Madhavan Srinivasan <[email protected]>
---
arch/powerpc/include/asm/perf_event_server.h | 2 +-
arch/powerpc/perf/power7-pmu.c | 18 +++++++++---------
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/powerpc/include/asm/perf_event_server.h b/arch/powerpc/include/asm/perf_event_server.h
index 8146221..0691087 100644
--- a/arch/powerpc/include/asm/perf_event_server.h
+++ b/arch/powerpc/include/asm/perf_event_server.h
@@ -141,7 +141,7 @@ extern ssize_t power_events_sysfs_show(struct device *dev,
#define EVENT_PTR(_id, _suffix) &EVENT_VAR(_id, _suffix).attr.attr
#define EVENT_ATTR(_name, _id, _suffix) \
- PMU_EVENT_ATTR(_name, EVENT_VAR(_id, _suffix), PME_##_id, \
+ PMU_EVENT_ATTR(_name, EVENT_VAR(_id, _suffix), _id, \
power_events_sysfs_show)
#define GENERIC_EVENT_ATTR(_name, _id) EVENT_ATTR(_name, _id, _g)
diff --git a/arch/powerpc/perf/power7-pmu.c b/arch/powerpc/perf/power7-pmu.c
index 5b62f238..a383c23 100644
--- a/arch/powerpc/perf/power7-pmu.c
+++ b/arch/powerpc/perf/power7-pmu.c
@@ -54,7 +54,7 @@
* Power7 event codes.
*/
#define EVENT(_name, _code) \
- PME_##_name = _code,
+ _name = _code,
enum {
#include "power7-events-list.h"
@@ -318,14 +318,14 @@ static void power7_disable_pmc(unsigned int pmc, unsigned long mmcr[])
}
static int power7_generic_events[] = {
- [PERF_COUNT_HW_CPU_CYCLES] = PME_PM_CYC,
- [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = PME_PM_GCT_NOSLOT_CYC,
- [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = PME_PM_CMPLU_STALL,
- [PERF_COUNT_HW_INSTRUCTIONS] = PME_PM_INST_CMPL,
- [PERF_COUNT_HW_CACHE_REFERENCES] = PME_PM_LD_REF_L1,
- [PERF_COUNT_HW_CACHE_MISSES] = PME_PM_LD_MISS_L1,
- [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = PME_PM_BRU_FIN,
- [PERF_COUNT_HW_BRANCH_MISSES] = PME_PM_BR_MPRED,
+ [PERF_COUNT_HW_CPU_CYCLES] = PM_CYC,
+ [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = PM_GCT_NOSLOT_CYC,
+ [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = PM_CMPLU_STALL,
+ [PERF_COUNT_HW_INSTRUCTIONS] = PM_INST_CMPL,
+ [PERF_COUNT_HW_CACHE_REFERENCES] = PM_LD_REF_L1,
+ [PERF_COUNT_HW_CACHE_MISSES] = PM_LD_MISS_L1,
+ [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = PM_BRU_FIN,
+ [PERF_COUNT_HW_BRANCH_MISSES] = PM_BR_MPRED,
};
#define C(x) PERF_COUNT_HW_CACHE_##x
--
1.9.1
From: Sukadev Bhattiprolu <[email protected]>
Export generic perf events for Power8 in sysfs.
Signed-off-by: Sukadev Bhattiprolu <[email protected]>
Signed-off-by: Madhavan Srinivasan <[email protected]>
---
arch/powerpc/perf/power8-events-list.h | 20 ++++++++++++++++
arch/powerpc/perf/power8-pmu.c | 43 +++++++++++++++++++++++++++++-----
2 files changed, 57 insertions(+), 6 deletions(-)
create mode 100644 arch/powerpc/perf/power8-events-list.h
diff --git a/arch/powerpc/perf/power8-events-list.h b/arch/powerpc/perf/power8-events-list.h
new file mode 100644
index 0000000..1368547
--- /dev/null
+++ b/arch/powerpc/perf/power8-events-list.h
@@ -0,0 +1,20 @@
+/*
+ * Performance counter support for POWER8 processors.
+ *
+ * Copyright 2013 Sukadev Bhattiprolu, IBM Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+/*
+ * Some power8 event codes.
+ */
+EVENT(PM_CYC, 0x0001e)
+EVENT(PM_GCT_NOSLOT_CYC, 0x100f8)
+EVENT(PM_CMPLU_STALL, 0x4000a)
+EVENT(PM_INST_CMPL, 0x00002)
+EVENT(PM_BRU_FIN, 0x10068)
+EVENT(PM_BR_MPRED_CMPL, 0x400f6)
diff --git a/arch/powerpc/perf/power8-pmu.c b/arch/powerpc/perf/power8-pmu.c
index 396351d..a542310 100644
--- a/arch/powerpc/perf/power8-pmu.c
+++ b/arch/powerpc/perf/power8-pmu.c
@@ -21,12 +21,11 @@
/*
* Some power8 event codes.
*/
-#define PM_CYC 0x0001e
-#define PM_GCT_NOSLOT_CYC 0x100f8
-#define PM_CMPLU_STALL 0x4000a
-#define PM_INST_CMPL 0x00002
-#define PM_BRU_FIN 0x10068
-#define PM_BR_MPRED_CMPL 0x400f6
+enum {
+#include "power8-events-list.h"
+};
+
+#undef EVENT
/* All L1 D cache load references counted at finish, gated by reject */
#define PM_LD_REF_L1 0x100ee
@@ -604,6 +603,37 @@ static void power8_disable_pmc(unsigned int pmc, unsigned long mmcr[])
mmcr[1] &= ~(0xffUL << MMCR1_PMCSEL_SHIFT(pmc + 1));
}
+GENERIC_EVENT_ATTR(cpu-cyles, PM_CYC);
+GENERIC_EVENT_ATTR(stalled-cycles-frontend, PM_GCT_NOSLOT_CYC);
+GENERIC_EVENT_ATTR(stalled-cycles-backend, PM_CMPLU_STALL);
+GENERIC_EVENT_ATTR(instructions, PM_INST_CMPL);
+GENERIC_EVENT_ATTR(branch-instructions, PM_BRU_FIN);
+GENERIC_EVENT_ATTR(branch-misses, PM_BR_MPRED_CMPL);
+
+#define EVENT(_name, _code) POWER_EVENT_ATTR(_name, _name);
+#include "power8-events-list.h"
+#undef EVENT
+
+#define EVENT(_name, _code) POWER_EVENT_PTR(_name),
+
+static struct attribute *power8_events_attr[] = {
+ GENERIC_EVENT_PTR(PM_CYC),
+ GENERIC_EVENT_PTR(PM_GCT_NOSLOT_CYC),
+ GENERIC_EVENT_PTR(PM_CMPLU_STALL),
+ GENERIC_EVENT_PTR(PM_INST_CMPL),
+ GENERIC_EVENT_PTR(PM_BRU_FIN),
+ GENERIC_EVENT_PTR(PM_BR_MPRED_CMPL),
+
+ #include "power8-events-list.h"
+ #undef EVENT
+ NULL
+};
+
+static struct attribute_group power8_pmu_events_group = {
+ .name = "events",
+ .attrs = power8_events_attr,
+};
+
PMU_FORMAT_ATTR(event, "config:0-49");
PMU_FORMAT_ATTR(pmcxsel, "config:0-7");
PMU_FORMAT_ATTR(mark, "config:8");
@@ -640,6 +670,7 @@ struct attribute_group power8_pmu_format_group = {
static const struct attribute_group *power8_pmu_attr_groups[] = {
&power8_pmu_format_group,
+ &power8_pmu_events_group,
NULL,
};
--
1.9.1
Adding EVENT macro for exporting Power8 generic events
Reviewed-by: Sukadev Bhattiprolu <[email protected]>
Signed-off-by: Madhavan Srinivasan <[email protected]>
---
arch/powerpc/perf/power8-pmu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/powerpc/perf/power8-pmu.c b/arch/powerpc/perf/power8-pmu.c
index a542310..282ab40 100644
--- a/arch/powerpc/perf/power8-pmu.c
+++ b/arch/powerpc/perf/power8-pmu.c
@@ -21,6 +21,8 @@
/*
* Some power8 event codes.
*/
+#define EVENT(_name, _code) \
+ _name = _code,
enum {
#include "power8-events-list.h"
};
--
1.9.1
Patch add "mem_access" event to sysfs. This as-is not a raw event
supported by Power8 pmu. Instead, it is formed based on
raw event encoding specificed in Power8-pmu.c.
Primary PMU event used here is PM_MRK_INST_CMPL.
This event tracks only the completed marked instructions.
Random sampling mode (MMCRA[SM]) with Random Load/Store
Facility Sampling (RLS) is enabled to mark type of instructions.
With Random sampling in RLS mode with PM_MRK_INST_CMPL event
on Power8, the LDST field in SIER identifies the memory
hierarchy level (eg: L1, L2 etc), from which a data-cache
miss for a marked instruction are satisfied.
Reviewed-by: Sukadev Bhattiprolu <[email protected]>
Signed-off-by: Madhavan Srinivasan <[email protected]>
---
arch/powerpc/perf/power8-events-list.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/perf/power8-events-list.h b/arch/powerpc/perf/power8-events-list.h
index 1368547..fdb8ce2 100644
--- a/arch/powerpc/perf/power8-events-list.h
+++ b/arch/powerpc/perf/power8-events-list.h
@@ -18,3 +18,4 @@ EVENT(PM_CMPLU_STALL, 0x4000a)
EVENT(PM_INST_CMPL, 0x00002)
EVENT(PM_BRU_FIN, 0x10068)
EVENT(PM_BR_MPRED_CMPL, 0x400f6)
+EVENT(mem_access, 0x100010401e0)
--
1.9.1
From: Sukadev Bhattiprolu <[email protected]>
perf_mem_data_src is an union that is initialized via the ->val field
and accessed via the bitmap fields. For this to work on big endian
platforms, we also need a big-endian represenation of perf_mem_data_src.
Signed-off-by: Sukadev Bhattiprolu <[email protected]>
Signed-off-by: Madhavan Srinivasan <[email protected]>
---
include/uapi/linux/perf_event.h | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h
index 9b79abb..b3f4099 100644
--- a/include/uapi/linux/perf_event.h
+++ b/include/uapi/linux/perf_event.h
@@ -747,6 +747,7 @@ enum perf_callchain_context {
#define PERF_FLAG_PID_CGROUP (1UL << 2) /* pid=cgroup id, per-cpu mode only */
#define PERF_FLAG_FD_CLOEXEC (1UL << 3) /* O_CLOEXEC */
+#if defined(__LITTLE_ENDIAN_BITFIELD)
union perf_mem_data_src {
__u64 val;
struct {
@@ -758,6 +759,21 @@ union perf_mem_data_src {
mem_rsvd:31;
};
};
+#elif defined(__BIG_ENDIAN_BITFIELD)
+union perf_mem_data_src {
+ __u64 val;
+ struct {
+ __u64 mem_rsvd:31,
+ mem_dtlb:7, /* tlb access */
+ mem_lock:2, /* lock instr */
+ mem_snoop:5, /* snoop mode */
+ mem_lvl:14, /* memory hierarchy level */
+ mem_op:5; /* type of opcode */
+ };
+};
+#else
+#error "Unknown endianness"
+#endif
/* type of opcode (load/store/prefetch,code) */
#define PERF_MEM_OP_NA 0x01 /* not available */
--
1.9.1
From: Sukadev Bhattiprolu <[email protected]>
On Power8, the LDST field in SIER identifies the memory hierarchy level
(eg: L1, L2 etc), from which a data-cache miss for a marked instruction
was satisfied.
Use the 'perf_mem_data_src' object to export this hierarchy level to user
space. Fortunately, the memory hierarchy levels in Power8 map fairly easily
into the arch-neutral levels as described by the ldst_src_map[] table.
Usage:
perf record -d -e 'cpu/mem_access/' <application>
perf report -n --mem-mode --sort=mem,sym,dso,symbol_daddr,dso_daddr"
For samples involving load/store instructions, the memory
hierarchy level is shown as "L1 hit", "Remote RAM hit" etc.
# or
perf record --data <application>
perf report -D
Sample records contain a 'data_src' field which encodes the
memory hierarchy level: Eg: data_src 0x442 indicates
MEM_OP_LOAD, MEM_LVL_HIT, MEM_LVL_L2 (i.e load hit L2).
As the precise semantics of 'perf mem -t load' or 'perf mem -t store' (which
require sampling only loads or only stores) cannot be implemented on Power,
we don't implement 'perf mem' on Power for now.
Thanks to input from Stephane Eranian, Michael Ellerman and Michael Neuling.
Signed-off-by: Sukadev Bhattiprolu <[email protected]>
Signed-off-by: Madhavan Srinivasan <[email protected]>
---
Edited the commit message to fit in the new event name
arch/powerpc/include/asm/perf_event_server.h | 2 ++
arch/powerpc/perf/core-book3s.c | 11 ++++++
arch/powerpc/perf/power8-pmu.c | 53 ++++++++++++++++++++++++++++
3 files changed, 66 insertions(+)
diff --git a/arch/powerpc/include/asm/perf_event_server.h b/arch/powerpc/include/asm/perf_event_server.h
index 0691087..b147cb6 100644
--- a/arch/powerpc/include/asm/perf_event_server.h
+++ b/arch/powerpc/include/asm/perf_event_server.h
@@ -42,6 +42,8 @@ struct power_pmu {
void (*config_bhrb)(u64 pmu_bhrb_filter);
void (*disable_pmc)(unsigned int pmc, unsigned long mmcr[]);
int (*limited_pmc_event)(u64 event_id);
+ void (*get_mem_data_src)(union perf_mem_data_src *dsrc,
+ struct pt_regs *regs);
u32 flags;
const struct attribute_group **attr_groups;
int n_generic;
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
index 7c4f669..4b27caf 100644
--- a/arch/powerpc/perf/core-book3s.c
+++ b/arch/powerpc/perf/core-book3s.c
@@ -1888,6 +1888,13 @@ ssize_t power_events_sysfs_show(struct device *dev,
return sprintf(page, "event=0x%02llx\n", pmu_attr->id);
}
+static inline void power_get_mem_data_src(union perf_mem_data_src *dsrc,
+ struct pt_regs *regs)
+{
+ if (ppmu->get_mem_data_src)
+ ppmu->get_mem_data_src(dsrc, regs);
+}
+
static struct pmu power_pmu = {
.pmu_enable = power_pmu_enable,
.pmu_disable = power_pmu_disable,
@@ -1969,6 +1976,10 @@ static void record_and_restart(struct perf_event *event, unsigned long val,
data.br_stack = &cpuhw->bhrb_stack;
}
+ if (event->attr.sample_type & PERF_SAMPLE_DATA_SRC &&
+ ppmu->get_mem_data_src)
+ ppmu->get_mem_data_src(&data.data_src, regs);
+
if (perf_event_overflow(event, &data, regs))
power_pmu_stop(event, 0);
}
diff --git a/arch/powerpc/perf/power8-pmu.c b/arch/powerpc/perf/power8-pmu.c
index 282ab40..40e74a0 100644
--- a/arch/powerpc/perf/power8-pmu.c
+++ b/arch/powerpc/perf/power8-pmu.c
@@ -636,6 +636,58 @@ static struct attribute_group power8_pmu_events_group = {
.attrs = power8_events_attr,
};
+#define POWER8_SIER_TYPE_SHIFT 15
+#define POWER8_SIER_TYPE_MASK (0x7LL << POWER8_SIER_TYPE_SHIFT)
+
+#define POWER8_SIER_LDST_SHIFT 1
+#define POWER8_SIER_LDST_MASK (0x7LL << POWER8_SIER_LDST_SHIFT)
+
+#define P(a, b) PERF_MEM_S(a, b)
+#define PLH(a, b) (P(OP, LOAD) | P(LVL, HIT) | P(a, b))
+#define PSM(a, b) (P(OP, STORE) | P(LVL, MISS) | P(a, b))
+
+/*
+ * Power8 interpretations:
+ * REM_CCE1: 1-hop indicates L2/L3 cache of a different core on same chip
+ * REM_CCE2: 2-hop indicates different chip or different node.
+ */
+static u64 ldst_src_map[] = {
+ /* 000 */ P(LVL, NA),
+
+ /* 001 */ PLH(LVL, L1),
+ /* 010 */ PLH(LVL, L2),
+ /* 011 */ PLH(LVL, L3),
+ /* 100 */ PLH(LVL, LOC_RAM),
+ /* 101 */ PLH(LVL, REM_CCE1),
+ /* 110 */ PLH(LVL, REM_CCE2),
+
+ /* 111 */ PSM(LVL, L1),
+};
+
+static inline bool is_load_store_inst(u64 sier)
+{
+ u64 val;
+ val = (sier & POWER8_SIER_TYPE_MASK) >> POWER8_SIER_TYPE_SHIFT;
+
+ /* 1 = load, 2 = store */
+ return val == 1 || val == 2;
+}
+
+static void power8_get_mem_data_src(union perf_mem_data_src *dsrc,
+ struct pt_regs *regs)
+{
+ u64 idx;
+ u64 sier;
+
+ sier = mfspr(SPRN_SIER);
+
+ if (is_load_store_inst(sier)) {
+ idx = (sier & POWER8_SIER_LDST_MASK) >> POWER8_SIER_LDST_SHIFT;
+
+ dsrc->val |= ldst_src_map[idx];
+ }
+}
+
PMU_FORMAT_ATTR(event, "config:0-49");
PMU_FORMAT_ATTR(pmcxsel, "config:0-7");
PMU_FORMAT_ATTR(mark, "config:8");
@@ -845,6 +897,7 @@ static struct power_pmu power8_pmu = {
.bhrb_filter_map = power8_bhrb_filter_map,
.get_constraint = power8_get_constraint,
.get_alternatives = power8_get_alternatives,
+ .get_mem_data_src = power8_get_mem_data_src,
.disable_pmc = power8_disable_pmc,
.flags = PPMU_HAS_SSLOT | PPMU_HAS_SIER | PPMU_ARCH_207S,
.n_generic = ARRAY_SIZE(power8_generic_events),
--
1.9.1
perf_sample_data_init initialize the data source variable "->val"
with PERF_MEM_NA. New value should not be ORed since the userspace
perf tool will look at bitmap field when displaying the hierarchy levels.
Reviewed-by: Sukadev Bhattiprolu <[email protected]>
Signed-off-by: Madhavan Srinivasan <[email protected]>
---
arch/powerpc/perf/power8-pmu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/perf/power8-pmu.c b/arch/powerpc/perf/power8-pmu.c
index 40e74a0..667736f 100644
--- a/arch/powerpc/perf/power8-pmu.c
+++ b/arch/powerpc/perf/power8-pmu.c
@@ -684,7 +684,7 @@ static void power8_get_mem_data_src(union perf_mem_data_src *dsrc,
if (is_load_store_inst(sier)) {
idx = (sier & POWER8_SIER_LDST_MASK) >> POWER8_SIER_LDST_SHIFT;
- dsrc->val |= ldst_src_map[idx];
+ dsrc->val = ldst_src_map[idx];
}
}
--
1.9.1
From: Janani <[email protected]>
Code cleanup/fix in perf_event_print_debug(). Performance
Monitoring Unit (PMU) registers in the server side
are 64bit long.
Signed-off-by: Janani <[email protected]>
Signed-off-by: Madhavan Srinivasan <[email protected]>
---
arch/powerpc/perf/core-book3s.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
index 4b27caf..36dc23b 100644
--- a/arch/powerpc/perf/core-book3s.c
+++ b/arch/powerpc/perf/core-book3s.c
@@ -758,7 +758,7 @@ static void write_pmc(int idx, unsigned long val)
void perf_event_print_debug(void)
{
unsigned long sdar, sier, flags;
- u32 pmcs[MAX_HWEVENTS];
+ unsigned long pmcs[MAX_HWEVENTS];
int i;
if (!ppmu->n_counter)
@@ -775,11 +775,11 @@ void perf_event_print_debug(void)
for (; i < MAX_HWEVENTS; i++)
pmcs[i] = 0xdeadbeef;
- pr_info("PMC1: %08x PMC2: %08x PMC3: %08x PMC4: %08x\n",
+ pr_info("PMC1: %016lx PMC2: %016lx PMC3: %016lx PMC4: %016lx\n",
pmcs[0], pmcs[1], pmcs[2], pmcs[3]);
if (ppmu->n_counter > 4)
- pr_info("PMC5: %08x PMC6: %08x PMC7: %08x PMC8: %08x\n",
+ pr_info("PMC5: %016lx PMC6: %016lx PMC7: %016lx PMC8: %016lx\n",
pmcs[4], pmcs[5], pmcs[6], pmcs[7]);
pr_info("MMCR0: %016lx MMCR1: %016lx MMCRA: %016lx\n",
--
1.9.1
On Thu, 2015-11-06 at 08:43:37 UTC, Madhavan Srinivasan wrote:
> From: Janani <[email protected]>
>
> Code cleanup/fix in perf_event_print_debug(). Performance
> Monitoring Unit (PMU) registers in the server side
> are 64bit long.
No they're not, see the ISA, figure 17.
cheers