This patch series adds Broadcom North Star 2 (NS2) SoC support. NS2 is an ARMv8
based SoC and under the Broadcom iProc family.
Sorry for tying this with the Broadcom iProc PCIe driver fixes for ARM64. I
have to tie them together because iProc PCIe support is enabled by default
when ARCH_BCM_IPROC is enabled. Without the fixes in the iProc PCIe driver,
enabling CONFIG_ARCH_BCM_IPROC would break the build for arm64 defconfig. Let
me know if there's a better way to handle this.
This patch series is generated based on v4.2-rc2 and tested on Broadcom NS2 SVK
Ray Jui (4):
PCI: iproc: enable arm64 support for iProc PCIe
PCI: iproc: Fix ARM64 dependency in Kconfig
arm64: Add Broadcom's North Star 2 support
arm64: dts: Add Broadcom North Star 2 support
Documentation/devicetree/bindings/arm/bcm/ns2.txt | 9 ++
arch/arm64/Kconfig | 12 +++
arch/arm64/boot/dts/Makefile | 1 +
arch/arm64/boot/dts/broadcom/Makefile | 5 ++
arch/arm64/boot/dts/broadcom/ns2-svk.dts | 55 ++++++++++++
arch/arm64/boot/dts/broadcom/ns2.dtsi | 95 +++++++++++++++++++++
arch/arm64/configs/defconfig | 2 +
drivers/pci/host/Kconfig | 2 +-
drivers/pci/host/pcie-iproc.c | 12 +++
drivers/pci/host/pcie-iproc.h | 2 +
10 files changed, 194 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/arm/bcm/ns2.txt
create mode 100644 arch/arm64/boot/dts/broadcom/Makefile
create mode 100644 arch/arm64/boot/dts/broadcom/ns2-svk.dts
create mode 100644 arch/arm64/boot/dts/broadcom/ns2.dtsi
--
1.7.9.5
This patch enables arm64 support to iProc PCIe driver by wrapping
ARM 32-bit specific PCI APIs with CONFIG_ARM
Signed-off-by: Ray Jui <[email protected]>
Reviewed-by: Scott Branden <[email protected]>
---
drivers/pci/host/pcie-iproc.c | 12 ++++++++++++
drivers/pci/host/pcie-iproc.h | 2 ++
2 files changed, 14 insertions(+)
diff --git a/drivers/pci/host/pcie-iproc.c b/drivers/pci/host/pcie-iproc.c
index d77481e..a76b4df 100644
--- a/drivers/pci/host/pcie-iproc.c
+++ b/drivers/pci/host/pcie-iproc.c
@@ -58,10 +58,12 @@
#define SYS_RC_INTX_EN 0x330
#define SYS_RC_INTX_MASK 0xf
+#ifdef CONFIG_ARM
static inline struct iproc_pcie *sys_to_pcie(struct pci_sys_data *sys)
{
return sys->private_data;
}
+#endif
/**
* Note access to the configuration registers are protected at the higher layer
@@ -71,8 +73,12 @@ static void __iomem *iproc_pcie_map_cfg_bus(struct pci_bus *bus,
unsigned int devfn,
int where)
{
+#ifdef CONFIG_ARM
struct pci_sys_data *sys = bus->sysdata;
struct iproc_pcie *pcie = sys_to_pcie(sys);
+#else
+ struct iproc_pcie *pcie = bus->sysdata;
+#endif
unsigned slot = PCI_SLOT(devfn);
unsigned fn = PCI_FUNC(devfn);
unsigned busno = bus->number;
@@ -208,10 +214,14 @@ int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res)
iproc_pcie_reset(pcie);
+#ifdef CONFIG_ARM
pcie->sysdata.private_data = pcie;
bus = pci_create_root_bus(pcie->dev, 0, &iproc_pcie_ops,
&pcie->sysdata, res);
+#else
+ bus = pci_create_root_bus(pcie->dev, 0, &iproc_pcie_ops, pcie, res);
+#endif
if (!bus) {
dev_err(pcie->dev, "unable to create PCI root bus\n");
ret = -ENOMEM;
@@ -229,7 +239,9 @@ int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res)
pci_scan_child_bus(bus);
pci_assign_unassigned_bus_resources(bus);
+#ifdef CONFIG_ARM
pci_fixup_irqs(pci_common_swizzle, pcie->map_irq);
+#endif
pci_bus_add_devices(bus);
return 0;
diff --git a/drivers/pci/host/pcie-iproc.h b/drivers/pci/host/pcie-iproc.h
index ba0a108..12aaac4 100644
--- a/drivers/pci/host/pcie-iproc.h
+++ b/drivers/pci/host/pcie-iproc.h
@@ -29,7 +29,9 @@
struct iproc_pcie {
struct device *dev;
void __iomem *base;
+#ifdef CONFIG_ARM
struct pci_sys_data sysdata;
+#endif
struct pci_bus *root_bus;
struct phy *phy;
int irqs[IPROC_PCIE_MAX_NUM_IRQS];
--
1.7.9.5
Allow Broadcom iProc PCIe core driver to be compiled for ARM64
Signed-off-by: Ray Jui <[email protected]>
Reviewed-by: Vikram Prakash <[email protected]>
Reviewed-by: Scott Branden <[email protected]>
---
drivers/pci/host/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index c132bdd..d2c6144 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -117,7 +117,7 @@ config PCI_VERSATILE
config PCIE_IPROC
tristate "Broadcom iProc PCIe controller"
- depends on OF && ARM
+ depends on OF && (ARM || ARM64)
default n
help
This enables the iProc PCIe core controller support for Broadcom's
--
1.7.9.5
This patch adds support to Broadcom's North Star 2 SoC in the arm64
Kconfig and defconfig files
Signed-off-by: Ray Jui <[email protected]>
Reviewed-by: Scott Branden <[email protected]>
---
arch/arm64/Kconfig | 12 ++++++++++++
arch/arm64/configs/defconfig | 2 ++
2 files changed, 14 insertions(+)
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 318175f..6c5c279 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -162,6 +162,18 @@ source "kernel/Kconfig.freezer"
menu "Platform selection"
+config ARCH_BCM_IPROC
+ bool
+ help
+ This enables support for Broadcom iProc based SoCs
+
+config ARCH_BCM_NS2
+ bool "Broadcom North Start 2 (BCM5871X)"
+ select ARCH_BCM_IPROC
+ help
+ This enables support for Broadcom NS2 (BCM5871X). NS2 is in
+ the iProc family of SoCs based on the ARMv8 architecture
+
config ARCH_EXYNOS
bool
help
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 4e17e7e..3138700 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -31,6 +31,7 @@ CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_ARCH_BCM_NS2=y
CONFIG_ARCH_EXYNOS7=y
CONFIG_ARCH_FSL_LS2085A=y
CONFIG_ARCH_HISI=y
@@ -102,6 +103,7 @@ CONFIG_SERIO_AMBAKMI=y
CONFIG_LEGACY_PTY_COUNT=16
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_DW=y
CONFIG_SERIAL_8250_MT6577=y
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
--
1.7.9.5
Add Broadcom NS2 device tree binding document. Also add initial device
tree dtsi for Broadcom North Star 2 (NS2) SoC and board support for NS2
SVK board
Signed-off-by: Jon Mason <[email protected]>
Signed-off-by: Ray Jui <[email protected]>
Reviewed-by: Scott Branden <[email protected]>
---
Documentation/devicetree/bindings/arm/bcm/ns2.txt | 9 ++
arch/arm64/boot/dts/Makefile | 1 +
arch/arm64/boot/dts/broadcom/Makefile | 5 ++
arch/arm64/boot/dts/broadcom/ns2-svk.dts | 55 ++++++++++++
arch/arm64/boot/dts/broadcom/ns2.dtsi | 95 +++++++++++++++++++++
5 files changed, 165 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/bcm/ns2.txt
create mode 100644 arch/arm64/boot/dts/broadcom/Makefile
create mode 100644 arch/arm64/boot/dts/broadcom/ns2-svk.dts
create mode 100644 arch/arm64/boot/dts/broadcom/ns2.dtsi
diff --git a/Documentation/devicetree/bindings/arm/bcm/ns2.txt b/Documentation/devicetree/bindings/arm/bcm/ns2.txt
new file mode 100644
index 0000000..35f056f
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/bcm/ns2.txt
@@ -0,0 +1,9 @@
+Broadcom North Star 2 (NS2) device tree bindings
+------------------------------------------------
+
+Boards with NS2 shall have the following properties:
+
+Required root node property:
+
+NS2 SVK board
+compatible = "brcm,ns2-svk", "brcm,ns2";
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 38913be..9f95941 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -1,6 +1,7 @@
dts-dirs += amd
dts-dirs += apm
dts-dirs += arm
+dts-dirs += broadcom
dts-dirs += cavium
dts-dirs += exynos
dts-dirs += freescale
diff --git a/arch/arm64/boot/dts/broadcom/Makefile b/arch/arm64/boot/dts/broadcom/Makefile
new file mode 100644
index 0000000..9fda762
--- /dev/null
+++ b/arch/arm64/boot/dts/broadcom/Makefile
@@ -0,0 +1,5 @@
+dtb-$(CONFIG_ARCH_BCM_NS2) += ns2-svk.dtb
+
+always := $(dtb-y)
+subdir-y := $(dts-dirs)
+clean-files := *.dtb
diff --git a/arch/arm64/boot/dts/broadcom/ns2-svk.dts b/arch/arm64/boot/dts/broadcom/ns2-svk.dts
new file mode 100644
index 0000000..08a7816
--- /dev/null
+++ b/arch/arm64/boot/dts/broadcom/ns2-svk.dts
@@ -0,0 +1,55 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright(c) 2015 Broadcom Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Broadcom Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/dts-v1/;
+
+#include "ns2.dtsi"
+
+/ {
+ model = "Broadcom NS2 SVK";
+ compatible = "brcm,ns2-svk", "brcm,ns2";
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8 earlycon=uart8250,mmio32,0x66130000";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x000000000 0x80000000 0x00000000 0x40000000>;
+ };
+
+ soc: soc {
+ uart3: serial@66130000 {
+ status = "ok";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi
new file mode 100644
index 0000000..9d34fe4
--- /dev/null
+++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi
@@ -0,0 +1,95 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright(c) 2015 Broadcom Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Broadcom Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/memreserve/ 0x84b00000 0x00000008;
+
+/ {
+ compatible = "brcm,ns2";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57", "arm,armv8";
+ reg = <0 0>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x84b00000>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) |
+ IRQ_TYPE_EDGE_RISING)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) |
+ IRQ_TYPE_EDGE_RISING)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xff) |
+ IRQ_TYPE_EDGE_RISING)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xff) |
+ IRQ_TYPE_EDGE_RISING)>;
+ clock-frequency = <25000000>;
+ };
+
+ soc: soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0 0xffffffff>;
+
+ gic: interrupt-controller@65210000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x65210000 0x1000>,
+ <0x65220000 0x1000>,
+ <0x65240000 0x2000>,
+ <0x65260000 0x1000>;
+ };
+
+ uart3: serial@66130000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x66130000 0x100>;
+ interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <23961600>;
+ status = "disabled";
+ };
+ };
+};
--
1.7.9.5
On Mon, Jul 13, 2015 at 06:39:14PM -0700, Ray Jui wrote:
> This patch adds support to Broadcom's North Star 2 SoC in the arm64
> Kconfig and defconfig files
>
> Signed-off-by: Ray Jui <[email protected]>
> Reviewed-by: Scott Branden <[email protected]>
> ---
> arch/arm64/Kconfig | 12 ++++++++++++
> arch/arm64/configs/defconfig | 2 ++
> 2 files changed, 14 insertions(+)
>
> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
> index 318175f..6c5c279 100644
> --- a/arch/arm64/Kconfig
> +++ b/arch/arm64/Kconfig
> @@ -162,6 +162,18 @@ source "kernel/Kconfig.freezer"
>
> menu "Platform selection"
>
> +config ARCH_BCM_IPROC
> + bool
> + help
> + This enables support for Broadcom iProc based SoCs
> +
> +config ARCH_BCM_NS2
> + bool "Broadcom North Start 2 (BCM5871X)"
> + select ARCH_BCM_IPROC
> + help
> + This enables support for Broadcom NS2 (BCM5871X). NS2 is in
> + the iProc family of SoCs based on the ARMv8 architecture
Do you really need the second config option? Just leave the one covering
the family as we do for most of the other family SoCs on arm64 (apart
from ARCH_TEGRA_123_SOC which I plan to remove and use ARCH_TEGRA
instead).
--
Catalin
Hi,
> +/dts-v1/;
> +
> +#include "ns2.dtsi"
> +
> +/ {
> + model = "Broadcom NS2 SVK";
> + compatible = "brcm,ns2-svk", "brcm,ns2";
> +
> + chosen {
> + bootargs = "console=ttyS0,115200n8 earlycon=uart8250,mmio32,0x66130000";
> + };
Please use stdout-path instead (you can use /aliases to make it
simpler). It'll save a redundant description of the UART and will remove
the dependency on Linux-specific naming of the UART.
[...]
> +/ {
> + compatible = "brcm,ns2";
> + interrupt-parent = <&gic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpus {
> + #address-cells = <2>;
> + #size-cells = <0>;
> +
> + cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57", "arm,armv8";
> + reg = <0 0>;
> + enable-method = "spin-table";
> + cpu-release-addr = <0 0x84b00000>;
> + };
> + };
Shouldn't the other CPUs be described?
Using spin-table for SMP is somewhat unfortunate, as it comes with a
number of problems (e.g. unwoken secondaries spinning in the kernel). I
would strongly advise using PSCI instead.
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) |
> + IRQ_TYPE_EDGE_RISING)>,
> + <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) |
> + IRQ_TYPE_EDGE_RISING)>,
> + <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xff) |
> + IRQ_TYPE_EDGE_RISING)>,
> + <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xff) |
> + IRQ_TYPE_EDGE_RISING)>;
> + clock-frequency = <25000000>;
> + };
Please fix your firmware to configure CNTFRQ_EL0, it is simply a bug not
to, and using clock-frequency does not fix all the problems that not
configuring it causes.
Thanks,
Mark.
On Monday 13 July 2015 18:39:15 Ray Jui wrote:
> + chosen {
> + bootargs = "console=ttyS0,115200n8 earlycon=uart8250,mmio32,0x66130000";
> + };
> +
Please remove those bootargs and just set the stdout-path to the alias
of the uart. If necessary, you can have just "earlycon" in the bootargs.
Arnd
On 7/14/2015 2:14 AM, Catalin Marinas wrote:
> On Mon, Jul 13, 2015 at 06:39:14PM -0700, Ray Jui wrote:
>> This patch adds support to Broadcom's North Star 2 SoC in the arm64
>> Kconfig and defconfig files
>>
>> Signed-off-by: Ray Jui <[email protected]>
>> Reviewed-by: Scott Branden <[email protected]>
>> ---
>> arch/arm64/Kconfig | 12 ++++++++++++
>> arch/arm64/configs/defconfig | 2 ++
>> 2 files changed, 14 insertions(+)
>>
>> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
>> index 318175f..6c5c279 100644
>> --- a/arch/arm64/Kconfig
>> +++ b/arch/arm64/Kconfig
>> @@ -162,6 +162,18 @@ source "kernel/Kconfig.freezer"
>>
>> menu "Platform selection"
>>
>> +config ARCH_BCM_IPROC
>> + bool
>> + help
>> + This enables support for Broadcom iProc based SoCs
>> +
>> +config ARCH_BCM_NS2
>> + bool "Broadcom North Start 2 (BCM5871X)"
>> + select ARCH_BCM_IPROC
>> + help
>> + This enables support for Broadcom NS2 (BCM5871X). NS2 is in
>> + the iProc family of SoCs based on the ARMv8 architecture
>
> Do you really need the second config option? Just leave the one covering
> the family as we do for most of the other family SoCs on arm64 (apart
> from ARCH_TEGRA_123_SOC which I plan to remove and use ARCH_TEGRA
> instead).
>
ARCH_BCM_NS2 helps in cases where a NS2 specific driver may just default
to ARCH_BCM_NS2 in its Kconfig, so those NS2 drivers got turned on
whenever ARCH_BCM_NS2 is turned on.
If the plan is to allow only one ARCH flag per family of SoCs for ARMv8,
I can go ahead and remove ARCH_BCM_NS2.
Thanks,
Ray
On 7/14/2015 2:23 AM, Mark Rutland wrote:
> Hi,
>
>> +/dts-v1/;
>> +
>> +#include "ns2.dtsi"
>> +
>> +/ {
>> + model = "Broadcom NS2 SVK";
>> + compatible = "brcm,ns2-svk", "brcm,ns2";
>> +
>> + chosen {
>> + bootargs = "console=ttyS0,115200n8 earlycon=uart8250,mmio32,0x66130000";
>> + };
>
> Please use stdout-path instead (you can use /aliases to make it
> simpler). It'll save a redundant description of the UART and will remove
> the dependency on Linux-specific naming of the UART.
>
> [...]
Saw that Arnd also has the same comment. I will fix this.
>
>> +/ {
>> + compatible = "brcm,ns2";
>> + interrupt-parent = <&gic>;
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> +
>> + cpus {
>> + #address-cells = <2>;
>> + #size-cells = <0>;
>> +
>> + cpu@0 {
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a57", "arm,armv8";
>> + reg = <0 0>;
>> + enable-method = "spin-table";
>> + cpu-release-addr = <0 0x84b00000>;
>> + };
>> + };
>
> Shouldn't the other CPUs be described?
Let me give that a try but there's a chance that I cannot enable other 3
cores until we have a more stable bootloader configuration.
>
> Using spin-table for SMP is somewhat unfortunate, as it comes with a
> number of problems (e.g. unwoken secondaries spinning in the kernel). I
> would strongly advise using PSCI instead.
>
Yes I agree and I'm fully aware PSCI is the preferred way of bringing up
ARMv8 cores. Unfortunately this is currently out of my control as this
is done in ARM Trusted Firmware that was handled by a different team
within Broadcom and they have very tight schedule and will not have time
to add PSCI support in the near term.
The plan is to use spin-table for now and convert to PSCI when we have
the support for it in our ATF. That should happen within the next couple
months.
>> +
>> + timer {
>> + compatible = "arm,armv8-timer";
>> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) |
>> + IRQ_TYPE_EDGE_RISING)>,
>> + <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) |
>> + IRQ_TYPE_EDGE_RISING)>,
>> + <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xff) |
>> + IRQ_TYPE_EDGE_RISING)>,
>> + <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xff) |
>> + IRQ_TYPE_EDGE_RISING)>;
>> + clock-frequency = <25000000>;
>> + };
>
> Please fix your firmware to configure CNTFRQ_EL0, it is simply a bug not
> to, and using clock-frequency does not fix all the problems that not
> configuring it causes.
Yes will do this.
>
> Thanks,
> Mark.
>
Thanks,
Ray