Add support for Tegra210 Audio DMA (ADMA) controller. This driver is based
upon the existing Tegra20-APB DMA driver and a lot of the core code has
been re-used.
This is currently being distributed as an RFC to get feedback on the
approach and although this has been compile and boot tested, it still
needs further functional testing to ensure it is working well.
This series is based upon the Tegra-APB clean-up series [0].
[0] https://lkml.org/lkml/2015/8/6/315
Jon Hunter (7):
DMA: tegra-apb: Correct runtime-pm usage
DMA: tegra-apb: Move code dealing with h/w registers into separate
functions
DMA: tegra-apb: Clean-up and simplify setting up of transfer
parameters
DMA: tegra-apb: Add a function table for functions dealing with
registers
DMA: tegra-apb: Move common code into separate source files
Documentation: DT: Add binding documentation for NVIDIA ADMA
DMA: tegra-adma: Add support for Tegra210 ADMA
.../devicetree/bindings/dma/tegra210-adma.txt | 49 +
drivers/dma/Kconfig | 16 +
drivers/dma/Makefile | 2 +
drivers/dma/tegra-common.c | 734 +++++++++++++
drivers/dma/tegra-common.h | 260 +++++
drivers/dma/tegra20-apb-dma.c | 1121 +++-----------------
drivers/dma/tegra210-adma.c | 710 +++++++++++++
7 files changed, 1928 insertions(+), 964 deletions(-)
create mode 100644 Documentation/devicetree/bindings/dma/tegra210-adma.txt
create mode 100644 drivers/dma/tegra-common.c
create mode 100644 drivers/dma/tegra-common.h
create mode 100644 drivers/dma/tegra210-adma.c
--
2.1.4
The tegra-apb DMA driver enables runtime-pm but never calls
pm_runtime_get/put and hence the runtime-pm callbacks are never invoked.
The driver manages the clocks by directly calling clk_prepare_enable()
and clk_unprepare_disable().
Fix this by replacing the clk_prepare_enable() and clk_disable_unprepare()
with pm_runtime_get_sync() and pm_runtime_put(), respectively. Note that
the consequence of this is that if runtime-pm is disabled, then the clocks
will remain on the entire time the driver is loaded. However, if
runtime-pm is disabled, then power is not most likely not a concern.
Signed-off-by: Jon Hunter <[email protected]>
---
drivers/dma/tegra20-apb-dma.c | 36 ++++++++++++------------------------
1 file changed, 12 insertions(+), 24 deletions(-)
diff --git a/drivers/dma/tegra20-apb-dma.c b/drivers/dma/tegra20-apb-dma.c
index c8f79dcaaee8..097432ea89fa 100644
--- a/drivers/dma/tegra20-apb-dma.c
+++ b/drivers/dma/tegra20-apb-dma.c
@@ -1182,14 +1182,11 @@ static int tegra_dma_alloc_chan_resources(struct dma_chan *dc)
{
struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
struct tegra_dma *tdma = tdc->tdma;
- int ret;
dma_cookie_init(&tdc->dma_chan);
tdc->config_init = false;
- ret = clk_prepare_enable(tdma->dma_clk);
- if (ret < 0)
- dev_err(tdc2dev(tdc), "clk_prepare_enable failed: %d\n", ret);
- return ret;
+
+ return pm_runtime_get_sync(tdma->dev);
}
static void tegra_dma_free_chan_resources(struct dma_chan *dc)
@@ -1232,7 +1229,7 @@ static void tegra_dma_free_chan_resources(struct dma_chan *dc)
list_del(&sg_req->node);
kfree(sg_req);
}
- clk_disable_unprepare(tdma->dma_clk);
+ pm_runtime_put(tdma->dev);
tdc->slave_id = 0;
}
@@ -1356,21 +1353,13 @@ static int tegra_dma_probe(struct platform_device *pdev)
spin_lock_init(&tdma->global_lock);
pm_runtime_enable(&pdev->dev);
- if (!pm_runtime_enabled(&pdev->dev)) {
+ if (!pm_runtime_enabled(&pdev->dev))
ret = tegra_dma_runtime_resume(&pdev->dev);
- if (ret) {
- dev_err(&pdev->dev, "dma_runtime_resume failed %d\n",
- ret);
- goto err_pm_disable;
- }
- }
+ else
+ ret = pm_runtime_get_sync(&pdev->dev);
- /* Enable clock before accessing registers */
- ret = clk_prepare_enable(tdma->dma_clk);
- if (ret < 0) {
- dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
+ if (ret)
goto err_pm_disable;
- }
/* Reset DMA controller */
reset_control_assert(tdma->rst);
@@ -1382,7 +1371,7 @@ static int tegra_dma_probe(struct platform_device *pdev)
tdma_write(tdma, TEGRA_APBDMA_CONTROL, 0);
tdma_write(tdma, TEGRA_APBDMA_IRQ_MASK_SET, 0xFFFFFFFFul);
- clk_disable_unprepare(tdma->dma_clk);
+ pm_runtime_put(&pdev->dev);
INIT_LIST_HEAD(&tdma->dma_dev.channels);
for (i = 0; i < cdata->nr_channels; i++) {
@@ -1484,7 +1473,6 @@ err_irq:
struct tegra_dma_channel *tdc = &tdma->channels[i];
tasklet_kill(&tdc->tasklet);
}
-
err_pm_disable:
pm_runtime_disable(&pdev->dev);
if (!pm_runtime_status_suspended(&pdev->dev))
@@ -1543,7 +1531,7 @@ static int tegra_dma_pm_suspend(struct device *dev)
int ret;
/* Enable clock before accessing register */
- ret = tegra_dma_runtime_resume(dev);
+ ret = pm_runtime_get_sync(dev);
if (ret < 0)
return ret;
@@ -1560,7 +1548,7 @@ static int tegra_dma_pm_suspend(struct device *dev)
}
/* Disable clock */
- tegra_dma_runtime_suspend(dev);
+ pm_runtime_put(dev);
return 0;
}
@@ -1571,7 +1559,7 @@ static int tegra_dma_pm_resume(struct device *dev)
int ret;
/* Enable clock before accessing register */
- ret = tegra_dma_runtime_resume(dev);
+ ret = pm_runtime_get_sync(dev);
if (ret < 0)
return ret;
@@ -1592,7 +1580,7 @@ static int tegra_dma_pm_resume(struct device *dev)
}
/* Disable clock */
- tegra_dma_runtime_suspend(dev);
+ pm_runtime_put(dev);
return 0;
}
#endif
--
2.1.4
In preparation for adding the Tegra210 ADMA driver, that is based upon the
Tegra20-APB DMA driver, move code that accesses hardware registers into
specific functions. The Tegra210 ADMA and Tegra20-APB DMA drivers are not
compatible from a hardware register perspective, but the drivers are very
much the same. Hence, by isolating code that deals with the hardware
registers it will then be possible to add a function table to call code
that accesses the hardware registers and re-use the common driver code
for both DMAs.
Signed-off-by: Jon Hunter <[email protected]>
---
drivers/dma/tegra20-apb-dma.c | 277 ++++++++++++++++++++++++++----------------
1 file changed, 170 insertions(+), 107 deletions(-)
diff --git a/drivers/dma/tegra20-apb-dma.c b/drivers/dma/tegra20-apb-dma.c
index 097432ea89fa..e552a4efef71 100644
--- a/drivers/dma/tegra20-apb-dma.c
+++ b/drivers/dma/tegra20-apb-dma.c
@@ -359,6 +359,18 @@ static int tegra_dma_slave_config(struct dma_chan *dc,
return 0;
}
+static u32 tegra_dma_get_xfer_count(struct tegra_dma_channel *tdc)
+{
+ u32 wcount;
+
+ if (tdc->tdma->chip_data->support_separate_wcount_reg)
+ wcount = tdc_read(tdc, TEGRA_APBDMA_CHAN_WORD_TRANSFER);
+ else
+ wcount = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
+
+ return (wcount & TEGRA_APBDMA_STATUS_COUNT_MASK) - 4;
+}
+
static void tegra_dma_global_pause(struct tegra_dma_channel *tdc,
bool wait_for_burst_complete)
{
@@ -394,6 +406,38 @@ out:
spin_unlock(&tdma->global_lock);
}
+static u32 tegra_dma_irq_status(struct tegra_dma_channel *tdc)
+{
+ u32 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
+
+ return status & TEGRA_APBDMA_STATUS_ISE_EOC;
+}
+
+static u32 tegra_dma_irq_clear(struct tegra_dma_channel *tdc)
+{
+ u32 status = tegra_dma_irq_status(tdc);
+
+ if (status) {
+ dev_dbg(tdc2dev(tdc), "%s():clearing interrupt\n", __func__);
+ tdc_write(tdc, TEGRA_APBDMA_CHAN_STATUS, status);
+ }
+
+ return status;
+}
+
+static void tegra_dma_program(struct tegra_dma_channel *tdc,
+ struct tegra_dma_sg_req *nsg_req)
+{
+ tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, nsg_req->ch_regs.apb_ptr);
+ tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, nsg_req->ch_regs.ahb_ptr);
+ if (tdc->tdma->chip_data->support_separate_wcount_reg)
+ tdc_write(tdc, TEGRA_APBDMA_CHAN_WCOUNT,
+ nsg_req->ch_regs.wcount);
+ tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,
+ nsg_req->ch_regs.csr | TEGRA_APBDMA_CSR_ENB);
+ nsg_req->configured = true;
+}
+
static void tegra_dma_pause(struct tegra_dma_channel *tdc,
bool wait_for_burst_complete)
{
@@ -423,7 +467,6 @@ static void tegra_dma_resume(struct tegra_dma_channel *tdc)
static void tegra_dma_stop(struct tegra_dma_channel *tdc)
{
u32 csr;
- u32 status;
/* Disable interrupts */
csr = tdc_read(tdc, TEGRA_APBDMA_CHAN_CSR);
@@ -435,11 +478,8 @@ static void tegra_dma_stop(struct tegra_dma_channel *tdc)
tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, csr);
/* Clear interrupt status if it is there */
- status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
- if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
- dev_dbg(tdc2dev(tdc), "%s():clearing interrupt\n", __func__);
- tdc_write(tdc, TEGRA_APBDMA_CHAN_STATUS, status);
- }
+ tegra_dma_irq_clear(tdc);
+
tdc->busy = false;
}
@@ -478,13 +518,13 @@ static void tegra_dma_configure_for_next(struct tegra_dma_channel *tdc,
* load new configuration.
*/
tegra_dma_pause(tdc, false);
- status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
+ status = tegra_dma_irq_status(tdc);
/*
* If interrupt is pending then do nothing as the ISR will handle
* the programing for new request.
*/
- if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
+ if (status) {
dev_err(tdc2dev(tdc),
"Skipping new configuration as interrupt is pending\n");
tegra_dma_resume(tdc);
@@ -492,15 +532,7 @@ static void tegra_dma_configure_for_next(struct tegra_dma_channel *tdc,
}
/* Safe to program new configuration */
- tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, nsg_req->ch_regs.apb_ptr);
- tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, nsg_req->ch_regs.ahb_ptr);
- if (tdc->tdma->chip_data->support_separate_wcount_reg)
- tdc_write(tdc, TEGRA_APBDMA_CHAN_WCOUNT,
- nsg_req->ch_regs.wcount);
- tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,
- nsg_req->ch_regs.csr | TEGRA_APBDMA_CSR_ENB);
- nsg_req->configured = true;
-
+ tegra_dma_program(tdc, nsg_req);
tegra_dma_resume(tdc);
}
@@ -534,10 +566,10 @@ static void tdc_configure_next_head_desc(struct tegra_dma_channel *tdc)
}
}
-static inline int get_current_xferred_count(struct tegra_dma_channel *tdc,
- struct tegra_dma_sg_req *sg_req, unsigned long status)
+static inline int get_current_xferred_count(struct tegra_dma_sg_req *sg_req,
+ unsigned long wcount)
{
- return sg_req->req_len - (status & TEGRA_APBDMA_STATUS_COUNT_MASK) - 4;
+ return sg_req->req_len - wcount;
}
static void tegra_dma_abort_all(struct tegra_dma_channel *tdc)
@@ -683,9 +715,8 @@ static irqreturn_t tegra_dma_isr(int irq, void *dev_id)
spin_lock_irqsave(&tdc->lock, flags);
- status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
- if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
- tdc_write(tdc, TEGRA_APBDMA_CHAN_STATUS, status);
+ status = tegra_dma_irq_clear(tdc);
+ if (status) {
tdc->isr_handler(tdc, false);
tasklet_schedule(&tdc->tasklet);
spin_unlock_irqrestore(&tdc->lock, flags);
@@ -762,16 +793,13 @@ static int tegra_dma_terminate_all(struct dma_chan *dc)
/* Pause DMA before checking the queue status */
tegra_dma_pause(tdc, true);
- status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
- if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
+ status = tegra_dma_irq_status(tdc);
+ if (status) {
dev_dbg(tdc2dev(tdc), "%s():handling isr\n", __func__);
tdc->isr_handler(tdc, true);
- status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
}
- if (tdc->tdma->chip_data->support_separate_wcount_reg)
- wcount = tdc_read(tdc, TEGRA_APBDMA_CHAN_WORD_TRANSFER);
- else
- wcount = status;
+
+ wcount = tegra_dma_get_xfer_count(tdc);
was_busy = tdc->busy;
tegra_dma_stop(tdc);
@@ -780,7 +808,7 @@ static int tegra_dma_terminate_all(struct dma_chan *dc)
sgreq = list_first_entry(&tdc->pending_sg_req,
typeof(*sgreq), node);
sgreq->dma_desc->bytes_transferred +=
- get_current_xferred_count(tdc, sgreq, wcount);
+ get_current_xferred_count(sgreq, wcount);
}
tegra_dma_resume(tdc);
@@ -865,11 +893,27 @@ static inline int get_bus_width(struct tegra_dma_channel *tdc,
}
static inline int get_burst_size(struct tegra_dma_channel *tdc,
- u32 burst_size, enum dma_slave_buswidth slave_bw, int len)
+ enum dma_transfer_direction direction,
+ int len)
{
+ enum dma_slave_buswidth slave_bw;
+ u32 burst_size;
int burst_byte;
int burst_ahb_width;
+ switch (direction) {
+ case DMA_MEM_TO_DEV:
+ burst_size = tdc->dma_sconfig.dst_maxburst;
+ slave_bw = tdc->dma_sconfig.dst_addr_width;
+ break;
+ case DMA_DEV_TO_MEM:
+ burst_size = tdc->dma_sconfig.src_maxburst;
+ slave_bw = tdc->dma_sconfig.src_addr_width;
+ break;
+ default:
+ return TEGRA_APBDMA_AHBSEQ_BURST_1;
+ }
+
/*
* burst_size from client is in terms of the bus_width.
* convert them into AHB memory width which is 4 byte.
@@ -894,29 +938,23 @@ static inline int get_burst_size(struct tegra_dma_channel *tdc,
return TEGRA_APBDMA_AHBSEQ_BURST_8;
}
-static int get_transfer_param(struct tegra_dma_channel *tdc,
- enum dma_transfer_direction direction, unsigned long *apb_addr,
- unsigned long *apb_seq, unsigned long *csr, unsigned int *burst_size,
- enum dma_slave_buswidth *slave_bw)
+static int tegra_dma_get_xfer_params(struct tegra_dma_channel *tdc,
+ struct tegra_dma_channel_regs *ch_regs,
+ enum dma_transfer_direction direction)
{
-
switch (direction) {
case DMA_MEM_TO_DEV:
- *apb_addr = tdc->dma_sconfig.dst_addr;
- *apb_seq = get_bus_width(tdc, tdc->dma_sconfig.dst_addr_width);
- *burst_size = tdc->dma_sconfig.dst_maxburst;
- *slave_bw = tdc->dma_sconfig.dst_addr_width;
- *csr = TEGRA_APBDMA_CSR_DIR;
+ ch_regs->apb_ptr = tdc->dma_sconfig.dst_addr;
+ ch_regs->apb_seq = get_bus_width(tdc,
+ tdc->dma_sconfig.dst_addr_width);
+ ch_regs->csr = TEGRA_APBDMA_CSR_DIR;
return 0;
-
case DMA_DEV_TO_MEM:
- *apb_addr = tdc->dma_sconfig.src_addr;
- *apb_seq = get_bus_width(tdc, tdc->dma_sconfig.src_addr_width);
- *burst_size = tdc->dma_sconfig.src_maxburst;
- *slave_bw = tdc->dma_sconfig.src_addr_width;
- *csr = 0;
+ ch_regs->apb_ptr = tdc->dma_sconfig.src_addr;
+ ch_regs->apb_seq = get_bus_width(tdc,
+ tdc->dma_sconfig.src_addr_width);
+ ch_regs->csr = 0;
return 0;
-
default:
dev_err(tdc2dev(tdc), "Dma direction is not supported\n");
return -EINVAL;
@@ -924,6 +962,60 @@ static int get_transfer_param(struct tegra_dma_channel *tdc,
return -EINVAL;
}
+static int tegra_dma_get_xfer_params_sg(struct tegra_dma_channel *tdc,
+ struct tegra_dma_sg_req *sg_req,
+ enum dma_transfer_direction direction,
+ unsigned int flags)
+{
+ struct tegra_dma_channel_regs *ch_regs = &sg_req->ch_regs;
+ int ret;
+
+ ret = tegra_dma_get_xfer_params(tdc, ch_regs, direction);
+ if (ret < 0)
+ return ret;
+
+ ch_regs->ahb_seq = TEGRA_APBDMA_AHBSEQ_INTR_ENB;
+ ch_regs->ahb_seq |= TEGRA_APBDMA_AHBSEQ_WRAP_NONE <<
+ TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT;
+ ch_regs->ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32;
+
+ ch_regs->csr |= TEGRA_APBDMA_CSR_ONCE | TEGRA_APBDMA_CSR_FLOW;
+ ch_regs->csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
+ if (flags & DMA_PREP_INTERRUPT)
+ ch_regs->csr |= TEGRA_APBDMA_CSR_IE_EOC;
+
+ ch_regs->apb_seq |= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1;
+
+ return 0;
+}
+
+static int tegra_dma_get_xfer_params_cyclic(struct tegra_dma_channel *tdc,
+ struct tegra_dma_sg_req *sg_req,
+ enum dma_transfer_direction direction,
+ unsigned int flags)
+{
+ struct tegra_dma_channel_regs *ch_regs = &sg_req->ch_regs;
+ int ret;
+
+ ret = tegra_dma_get_xfer_params(tdc, ch_regs, direction);
+ if (ret < 0)
+ return ret;
+
+ ch_regs->ahb_seq = TEGRA_APBDMA_AHBSEQ_INTR_ENB;
+ ch_regs->ahb_seq |= TEGRA_APBDMA_AHBSEQ_WRAP_NONE <<
+ TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT;
+ ch_regs->ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32;
+
+ ch_regs->csr |= TEGRA_APBDMA_CSR_FLOW;
+ if (flags & DMA_PREP_INTERRUPT)
+ ch_regs->csr |= TEGRA_APBDMA_CSR_IE_EOC;
+ ch_regs->csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
+
+ ch_regs->apb_seq |= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1;
+
+ return 0;
+}
+
static void tegra_dma_prep_wcount(struct tegra_dma_channel *tdc,
struct tegra_dma_channel_regs *ch_regs, u32 len)
{
@@ -935,6 +1027,24 @@ static void tegra_dma_prep_wcount(struct tegra_dma_channel *tdc,
ch_regs->csr |= len_field;
}
+static void tegra_dma_set_xfer_params(struct tegra_dma_channel *tdc,
+ struct tegra_dma_sg_req *sg_req,
+ struct tegra_dma_sg_req *sg_base,
+ enum dma_transfer_direction direction,
+ u32 mem, u32 len)
+{
+ sg_req->ch_regs.ahb_seq |= get_burst_size(tdc, direction, len);
+ sg_req->ch_regs.apb_ptr = sg_base->ch_regs.apb_ptr;
+ sg_req->ch_regs.ahb_ptr = mem;
+ sg_req->ch_regs.csr = sg_base->ch_regs.csr;
+ tegra_dma_prep_wcount(tdc, &sg_req->ch_regs, len);
+ sg_req->ch_regs.apb_seq = sg_base->ch_regs.apb_seq;
+ sg_req->ch_regs.ahb_seq = sg_base->ch_regs.ahb_seq;
+ sg_req->configured = false;
+ sg_req->last_sg = false;
+ sg_req->req_len = len;
+}
+
static struct dma_async_tx_descriptor *tegra_dma_prep_slave_sg(
struct dma_chan *dc, struct scatterlist *sgl, unsigned int sg_len,
enum dma_transfer_direction direction, unsigned long flags,
@@ -942,13 +1052,10 @@ static struct dma_async_tx_descriptor *tegra_dma_prep_slave_sg(
{
struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
struct tegra_dma_desc *dma_desc;
- unsigned int i;
- struct scatterlist *sg;
- unsigned long csr, ahb_seq, apb_ptr, apb_seq;
+ unsigned int i;
+ struct scatterlist *sg;
struct list_head req_list;
- struct tegra_dma_sg_req *sg_req = NULL;
- u32 burst_size;
- enum dma_slave_buswidth slave_bw;
+ struct tegra_dma_sg_req sg_base, *sg_req = NULL;
if (!tdc->config_init) {
dev_err(tdc2dev(tdc), "dma channel is not configured\n");
@@ -959,24 +1066,11 @@ static struct dma_async_tx_descriptor *tegra_dma_prep_slave_sg(
return NULL;
}
- if (get_transfer_param(tdc, direction, &apb_ptr, &apb_seq, &csr,
- &burst_size, &slave_bw) < 0)
+ if (tegra_dma_get_xfer_params_sg(tdc, &sg_base, direction, flags) < 0)
return NULL;
INIT_LIST_HEAD(&req_list);
- ahb_seq = TEGRA_APBDMA_AHBSEQ_INTR_ENB;
- ahb_seq |= TEGRA_APBDMA_AHBSEQ_WRAP_NONE <<
- TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT;
- ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32;
-
- csr |= TEGRA_APBDMA_CSR_ONCE | TEGRA_APBDMA_CSR_FLOW;
- csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
- if (flags & DMA_PREP_INTERRUPT)
- csr |= TEGRA_APBDMA_CSR_IE_EOC;
-
- apb_seq |= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1;
-
dma_desc = tegra_dma_desc_get(tdc);
if (!dma_desc) {
dev_err(tdc2dev(tdc), "Dma descriptors not available\n");
@@ -1011,19 +1105,11 @@ static struct dma_async_tx_descriptor *tegra_dma_prep_slave_sg(
return NULL;
}
- ahb_seq |= get_burst_size(tdc, burst_size, slave_bw, len);
dma_desc->bytes_requested += len;
- sg_req->ch_regs.apb_ptr = apb_ptr;
- sg_req->ch_regs.ahb_ptr = mem;
- sg_req->ch_regs.csr = csr;
- tegra_dma_prep_wcount(tdc, &sg_req->ch_regs, len);
- sg_req->ch_regs.apb_seq = apb_seq;
- sg_req->ch_regs.ahb_seq = ahb_seq;
- sg_req->configured = false;
- sg_req->last_sg = false;
+ tegra_dma_set_xfer_params(tdc, sg_req, &sg_base, direction,
+ mem, len);
sg_req->dma_desc = dma_desc;
- sg_req->req_len = len;
list_add_tail(&sg_req->node, &dma_desc->tx_list);
}
@@ -1056,13 +1142,10 @@ static struct dma_async_tx_descriptor *tegra_dma_prep_dma_cyclic(
{
struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
struct tegra_dma_desc *dma_desc = NULL;
- struct tegra_dma_sg_req *sg_req = NULL;
- unsigned long csr, ahb_seq, apb_ptr, apb_seq;
+ struct tegra_dma_sg_req sg_base, *sg_req = NULL;
int len;
size_t remain_len;
dma_addr_t mem = buf_addr;
- u32 burst_size;
- enum dma_slave_buswidth slave_bw;
if (!buf_len || !period_len) {
dev_err(tdc2dev(tdc), "Invalid buffer/period len\n");
@@ -1101,22 +1184,10 @@ static struct dma_async_tx_descriptor *tegra_dma_prep_dma_cyclic(
return NULL;
}
- if (get_transfer_param(tdc, direction, &apb_ptr, &apb_seq, &csr,
- &burst_size, &slave_bw) < 0)
+ if (tegra_dma_get_xfer_params_cyclic(tdc, &sg_base, direction,
+ flags) < 0)
return NULL;
- ahb_seq = TEGRA_APBDMA_AHBSEQ_INTR_ENB;
- ahb_seq |= TEGRA_APBDMA_AHBSEQ_WRAP_NONE <<
- TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT;
- ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32;
-
- csr |= TEGRA_APBDMA_CSR_FLOW;
- if (flags & DMA_PREP_INTERRUPT)
- csr |= TEGRA_APBDMA_CSR_IE_EOC;
- csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
-
- apb_seq |= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1;
-
dma_desc = tegra_dma_desc_get(tdc);
if (!dma_desc) {
dev_err(tdc2dev(tdc), "not enough descriptors available\n");
@@ -1140,17 +1211,9 @@ static struct dma_async_tx_descriptor *tegra_dma_prep_dma_cyclic(
return NULL;
}
- ahb_seq |= get_burst_size(tdc, burst_size, slave_bw, len);
- sg_req->ch_regs.apb_ptr = apb_ptr;
- sg_req->ch_regs.ahb_ptr = mem;
- sg_req->ch_regs.csr = csr;
- tegra_dma_prep_wcount(tdc, &sg_req->ch_regs, len);
- sg_req->ch_regs.apb_seq = apb_seq;
- sg_req->ch_regs.ahb_seq = ahb_seq;
- sg_req->configured = false;
- sg_req->last_sg = false;
+ tegra_dma_set_xfer_params(tdc, sg_req, &sg_base, direction,
+ mem, len);
sg_req->dma_desc = dma_desc;
- sg_req->req_len = len;
list_add_tail(&sg_req->node, &dma_desc->tx_list);
remain_len -= len;
--
2.1.4
Most of the DMA transfer parameters that are configured for scatter-gather
or cyclic transfers are the same. Therefore, move the setup of common
parameters into the tegra_dma_get_xfer_params() function used for both
scatter-gather and cyclic transfers.
Note that TEGRA_APBDMA_AHBSEQ_WRAP_NONE is defined as 0 and so this setting
can be completely removed.
Signed-off-by: Jon Hunter <[email protected]>
---
drivers/dma/tegra20-apb-dma.c | 53 ++++++++++++++++---------------------------
1 file changed, 19 insertions(+), 34 deletions(-)
diff --git a/drivers/dma/tegra20-apb-dma.c b/drivers/dma/tegra20-apb-dma.c
index e552a4efef71..c1eb25075756 100644
--- a/drivers/dma/tegra20-apb-dma.c
+++ b/drivers/dma/tegra20-apb-dma.c
@@ -940,7 +940,8 @@ static inline int get_burst_size(struct tegra_dma_channel *tdc,
static int tegra_dma_get_xfer_params(struct tegra_dma_channel *tdc,
struct tegra_dma_channel_regs *ch_regs,
- enum dma_transfer_direction direction)
+ enum dma_transfer_direction direction,
+ unsigned int flags)
{
switch (direction) {
case DMA_MEM_TO_DEV:
@@ -948,48 +949,32 @@ static int tegra_dma_get_xfer_params(struct tegra_dma_channel *tdc,
ch_regs->apb_seq = get_bus_width(tdc,
tdc->dma_sconfig.dst_addr_width);
ch_regs->csr = TEGRA_APBDMA_CSR_DIR;
- return 0;
+ break;
case DMA_DEV_TO_MEM:
ch_regs->apb_ptr = tdc->dma_sconfig.src_addr;
ch_regs->apb_seq = get_bus_width(tdc,
tdc->dma_sconfig.src_addr_width);
ch_regs->csr = 0;
- return 0;
+ break;
default:
dev_err(tdc2dev(tdc), "Dma direction is not supported\n");
return -EINVAL;
}
- return -EINVAL;
-}
-
-static int tegra_dma_get_xfer_params_sg(struct tegra_dma_channel *tdc,
- struct tegra_dma_sg_req *sg_req,
- enum dma_transfer_direction direction,
- unsigned int flags)
-{
- struct tegra_dma_channel_regs *ch_regs = &sg_req->ch_regs;
- int ret;
-
- ret = tegra_dma_get_xfer_params(tdc, ch_regs, direction);
- if (ret < 0)
- return ret;
+ ch_regs->apb_seq |= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1;
ch_regs->ahb_seq = TEGRA_APBDMA_AHBSEQ_INTR_ENB;
- ch_regs->ahb_seq |= TEGRA_APBDMA_AHBSEQ_WRAP_NONE <<
- TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT;
ch_regs->ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32;
- ch_regs->csr |= TEGRA_APBDMA_CSR_ONCE | TEGRA_APBDMA_CSR_FLOW;
+ ch_regs->csr |= TEGRA_APBDMA_CSR_FLOW;
ch_regs->csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
+
if (flags & DMA_PREP_INTERRUPT)
ch_regs->csr |= TEGRA_APBDMA_CSR_IE_EOC;
- ch_regs->apb_seq |= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1;
-
return 0;
}
-static int tegra_dma_get_xfer_params_cyclic(struct tegra_dma_channel *tdc,
+static int tegra_dma_get_xfer_params_sg(struct tegra_dma_channel *tdc,
struct tegra_dma_sg_req *sg_req,
enum dma_transfer_direction direction,
unsigned int flags)
@@ -997,23 +982,23 @@ static int tegra_dma_get_xfer_params_cyclic(struct tegra_dma_channel *tdc,
struct tegra_dma_channel_regs *ch_regs = &sg_req->ch_regs;
int ret;
- ret = tegra_dma_get_xfer_params(tdc, ch_regs, direction);
+ ret = tegra_dma_get_xfer_params(tdc, ch_regs, direction, flags);
if (ret < 0)
return ret;
- ch_regs->ahb_seq = TEGRA_APBDMA_AHBSEQ_INTR_ENB;
- ch_regs->ahb_seq |= TEGRA_APBDMA_AHBSEQ_WRAP_NONE <<
- TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT;
- ch_regs->ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32;
+ ch_regs->csr |= TEGRA_APBDMA_CSR_ONCE;
- ch_regs->csr |= TEGRA_APBDMA_CSR_FLOW;
- if (flags & DMA_PREP_INTERRUPT)
- ch_regs->csr |= TEGRA_APBDMA_CSR_IE_EOC;
- ch_regs->csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
+ return 0;
+}
- ch_regs->apb_seq |= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1;
+static int tegra_dma_get_xfer_params_cyclic(struct tegra_dma_channel *tdc,
+ struct tegra_dma_sg_req *sg_req,
+ enum dma_transfer_direction direction,
+ unsigned int flags)
+{
+ struct tegra_dma_channel_regs *ch_regs = &sg_req->ch_regs;
- return 0;
+ return tegra_dma_get_xfer_params(tdc, ch_regs, direction, flags);
}
static void tegra_dma_prep_wcount(struct tegra_dma_channel *tdc,
--
2.1.4
In preparation for adding the Tegra210 ADMA driver, add a function table
for calling functions that access hardware registers. This way code that
is common between the Tegra20-APB DMA and Tegra210 DMA driver can be moved
into a separate source file and used by both DMA drivers.
Note that all function pointers in the table are compulsory and so no
checking that the function pointer is valid is performed.
Signed-off-by: Jon Hunter <[email protected]>
---
drivers/dma/tegra20-apb-dma.c | 92 +++++++++++++++++++++++++++++++++----------
1 file changed, 71 insertions(+), 21 deletions(-)
diff --git a/drivers/dma/tegra20-apb-dma.c b/drivers/dma/tegra20-apb-dma.c
index c1eb25075756..7947acdf23db 100644
--- a/drivers/dma/tegra20-apb-dma.c
+++ b/drivers/dma/tegra20-apb-dma.c
@@ -209,6 +209,33 @@ struct tegra_dma_channel {
struct tegra_dma_channel_regs channel_reg;
};
+struct tegra_dma_ops {
+ u32 (*get_xfer_count)(struct tegra_dma_channel *tdc);
+ int (*get_xfer_params_cyclic)(struct tegra_dma_channel *tdc,
+ struct tegra_dma_sg_req *sg_req,
+ enum dma_transfer_direction direction,
+ unsigned int flags);
+ int (*get_xfer_params_sg)(struct tegra_dma_channel *tdc,
+ struct tegra_dma_sg_req *sg_req,
+ enum dma_transfer_direction direction,
+ unsigned int flags);
+ u32 (*irq_clear)(struct tegra_dma_channel *tdc);
+ u32 (*irq_status)(struct tegra_dma_channel *tdc);
+ void (*pause)(struct tegra_dma_channel *tdc,
+ bool wait_for_burst_complete);
+ void (*program)(struct tegra_dma_channel *tdc,
+ struct tegra_dma_sg_req *sg_req);
+ void (*resume)(struct tegra_dma_channel *tdc);
+ void (*set_xfer_params)(struct tegra_dma_channel *tdc,
+ struct tegra_dma_sg_req *sg_req,
+ struct tegra_dma_sg_req *sg_base,
+ enum dma_transfer_direction direction,
+ u32 mem, u32 len);
+ void (*start)(struct tegra_dma_channel *tdc,
+ struct tegra_dma_sg_req *sg_req);
+ void (*stop)(struct tegra_dma_channel *tdc);
+};
+
/* tegra_dma: Tegra DMA specific information */
struct tegra_dma {
struct dma_device dma_dev;
@@ -218,6 +245,7 @@ struct tegra_dma {
spinlock_t global_lock;
void __iomem *base_addr;
const struct tegra_dma_chip_data *chip_data;
+ const struct tegra_dma_ops *ops;
/*
* Counter for managing global pausing of the DMA controller.
@@ -504,6 +532,7 @@ static void tegra_dma_start(struct tegra_dma_channel *tdc,
static void tegra_dma_configure_for_next(struct tegra_dma_channel *tdc,
struct tegra_dma_sg_req *nsg_req)
{
+ const struct tegra_dma_ops *ops = tdc->tdma->ops;
unsigned long status;
/*
@@ -517,8 +546,8 @@ static void tegra_dma_configure_for_next(struct tegra_dma_channel *tdc,
* If there is already IEC status then interrupt handler need to
* load new configuration.
*/
- tegra_dma_pause(tdc, false);
- status = tegra_dma_irq_status(tdc);
+ ops->pause(tdc, false);
+ status = ops->irq_status(tdc);
/*
* If interrupt is pending then do nothing as the ISR will handle
@@ -527,17 +556,18 @@ static void tegra_dma_configure_for_next(struct tegra_dma_channel *tdc,
if (status) {
dev_err(tdc2dev(tdc),
"Skipping new configuration as interrupt is pending\n");
- tegra_dma_resume(tdc);
+ ops->resume(tdc);
return;
}
/* Safe to program new configuration */
- tegra_dma_program(tdc, nsg_req);
- tegra_dma_resume(tdc);
+ ops->program(tdc, nsg_req);
+ ops->resume(tdc);
}
static void tdc_start_head_req(struct tegra_dma_channel *tdc)
{
+ const struct tegra_dma_ops *ops = tdc->tdma->ops;
struct tegra_dma_sg_req *sg_req;
if (list_empty(&tdc->pending_sg_req))
@@ -545,7 +575,7 @@ static void tdc_start_head_req(struct tegra_dma_channel *tdc)
sg_req = list_first_entry(&tdc->pending_sg_req,
typeof(*sg_req), node);
- tegra_dma_start(tdc, sg_req);
+ ops->start(tdc, sg_req);
sg_req->configured = true;
tdc->busy = true;
}
@@ -599,11 +629,12 @@ static void tegra_dma_abort_all(struct tegra_dma_channel *tdc)
static bool handle_continuous_head_request(struct tegra_dma_channel *tdc,
struct tegra_dma_sg_req *last_sg_req, bool to_terminate)
{
+ const struct tegra_dma_ops *ops = tdc->tdma->ops;
struct tegra_dma_sg_req *hsgreq = NULL;
if (list_empty(&tdc->pending_sg_req)) {
dev_err(tdc2dev(tdc), "Dma is running without req\n");
- tegra_dma_stop(tdc);
+ ops->stop(tdc);
return false;
}
@@ -614,7 +645,7 @@ static bool handle_continuous_head_request(struct tegra_dma_channel *tdc,
*/
hsgreq = list_first_entry(&tdc->pending_sg_req, typeof(*hsgreq), node);
if (!hsgreq->configured) {
- tegra_dma_stop(tdc);
+ ops->stop(tdc);
dev_err(tdc2dev(tdc), "Error in dma transfer, aborting dma\n");
tegra_dma_abort_all(tdc);
return false;
@@ -710,12 +741,13 @@ static void tegra_dma_tasklet(unsigned long data)
static irqreturn_t tegra_dma_isr(int irq, void *dev_id)
{
struct tegra_dma_channel *tdc = dev_id;
+ const struct tegra_dma_ops *ops = tdc->tdma->ops;
unsigned long status;
unsigned long flags;
spin_lock_irqsave(&tdc->lock, flags);
- status = tegra_dma_irq_clear(tdc);
+ status = ops->irq_clear(tdc);
if (status) {
tdc->isr_handler(tdc, false);
tasklet_schedule(&tdc->tasklet);
@@ -774,6 +806,7 @@ end:
static int tegra_dma_terminate_all(struct dma_chan *dc)
{
struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+ const struct tegra_dma_ops *ops = tdc->tdma->ops;
struct tegra_dma_sg_req *sgreq;
struct tegra_dma_desc *dma_desc;
unsigned long flags;
@@ -791,18 +824,18 @@ static int tegra_dma_terminate_all(struct dma_chan *dc)
goto skip_dma_stop;
/* Pause DMA before checking the queue status */
- tegra_dma_pause(tdc, true);
+ ops->pause(tdc, true);
- status = tegra_dma_irq_status(tdc);
+ status = ops->irq_status(tdc);
if (status) {
dev_dbg(tdc2dev(tdc), "%s():handling isr\n", __func__);
tdc->isr_handler(tdc, true);
}
- wcount = tegra_dma_get_xfer_count(tdc);
+ wcount = ops->get_xfer_count(tdc);
was_busy = tdc->busy;
- tegra_dma_stop(tdc);
+ ops->stop(tdc);
if (!list_empty(&tdc->pending_sg_req) && was_busy) {
sgreq = list_first_entry(&tdc->pending_sg_req,
@@ -810,7 +843,7 @@ static int tegra_dma_terminate_all(struct dma_chan *dc)
sgreq->dma_desc->bytes_transferred +=
get_current_xferred_count(sgreq, wcount);
}
- tegra_dma_resume(tdc);
+ ops->resume(tdc);
skip_dma_stop:
tegra_dma_abort_all(tdc);
@@ -1036,6 +1069,7 @@ static struct dma_async_tx_descriptor *tegra_dma_prep_slave_sg(
void *context)
{
struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+ const struct tegra_dma_ops *ops = tdc->tdma->ops;
struct tegra_dma_desc *dma_desc;
unsigned int i;
struct scatterlist *sg;
@@ -1051,7 +1085,7 @@ static struct dma_async_tx_descriptor *tegra_dma_prep_slave_sg(
return NULL;
}
- if (tegra_dma_get_xfer_params_sg(tdc, &sg_base, direction, flags) < 0)
+ if (ops->get_xfer_params_sg(tdc, &sg_base, direction, flags) < 0)
return NULL;
INIT_LIST_HEAD(&req_list);
@@ -1092,8 +1126,8 @@ static struct dma_async_tx_descriptor *tegra_dma_prep_slave_sg(
dma_desc->bytes_requested += len;
- tegra_dma_set_xfer_params(tdc, sg_req, &sg_base, direction,
- mem, len);
+ ops->set_xfer_params(tdc, sg_req, &sg_base, direction, mem,
+ len);
sg_req->dma_desc = dma_desc;
list_add_tail(&sg_req->node, &dma_desc->tx_list);
@@ -1126,6 +1160,7 @@ static struct dma_async_tx_descriptor *tegra_dma_prep_dma_cyclic(
unsigned long flags)
{
struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+ const struct tegra_dma_ops *ops = tdc->tdma->ops;
struct tegra_dma_desc *dma_desc = NULL;
struct tegra_dma_sg_req sg_base, *sg_req = NULL;
int len;
@@ -1169,8 +1204,7 @@ static struct dma_async_tx_descriptor *tegra_dma_prep_dma_cyclic(
return NULL;
}
- if (tegra_dma_get_xfer_params_cyclic(tdc, &sg_base, direction,
- flags) < 0)
+ if (ops->get_xfer_params_cyclic(tdc, &sg_base, direction, flags) < 0)
return NULL;
dma_desc = tegra_dma_desc_get(tdc);
@@ -1196,8 +1230,8 @@ static struct dma_async_tx_descriptor *tegra_dma_prep_dma_cyclic(
return NULL;
}
- tegra_dma_set_xfer_params(tdc, sg_req, &sg_base, direction,
- mem, len);
+ ops->set_xfer_params(tdc, sg_req, &sg_base, direction, mem,
+ len);
sg_req->dma_desc = dma_desc;
list_add_tail(&sg_req->node, &dma_desc->tx_list);
@@ -1354,6 +1388,20 @@ static const struct of_device_id tegra_dma_of_match[] = {
};
MODULE_DEVICE_TABLE(of, tegra_dma_of_match);
+static const struct tegra_dma_ops tegra_apb_ops = {
+ .get_xfer_count = tegra_dma_get_xfer_count,
+ .get_xfer_params_cyclic = tegra_dma_get_xfer_params_cyclic,
+ .get_xfer_params_sg = tegra_dma_get_xfer_params_sg,
+ .irq_clear = tegra_dma_irq_clear,
+ .irq_status = tegra_dma_irq_status,
+ .pause = tegra_dma_pause,
+ .program = tegra_dma_program,
+ .resume = tegra_dma_resume,
+ .set_xfer_params = tegra_dma_set_xfer_params,
+ .start = tegra_dma_start,
+ .stop = tegra_dma_stop,
+};
+
static int tegra_dma_probe(struct platform_device *pdev)
{
struct resource *res;
@@ -1495,6 +1543,8 @@ static int tegra_dma_probe(struct platform_device *pdev)
tdma->dma_dev.device_tx_status = tegra_dma_tx_status;
tdma->dma_dev.device_issue_pending = tegra_dma_issue_pending;
+ tdma->ops = &tegra_apb_ops;
+
ret = dma_async_device_register(&tdma->dma_dev);
if (ret < 0) {
dev_err(&pdev->dev,
--
2.1.4
Move code that is common between the Tegra20-APB DMA and Tegra210 ADMA
driver into separate source files.
Signed-off-by: Jon Hunter <[email protected]>
---
drivers/dma/Kconfig | 4 +
drivers/dma/Makefile | 1 +
drivers/dma/tegra-common.c | 733 ++++++++++++++++++++++++++++++++++
drivers/dma/tegra-common.h | 226 +++++++++++
drivers/dma/tegra20-apb-dma.c | 910 +-----------------------------------------
5 files changed, 972 insertions(+), 902 deletions(-)
create mode 100644 drivers/dma/tegra-common.c
create mode 100644 drivers/dma/tegra-common.h
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index ff50af3f1bb0..dd79b0bf0876 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -189,10 +189,14 @@ config TXX9_DMAC
Support the TXx9 SoC internal DMA controller. This can be
integrated in chips such as the Toshiba TX4927/38/39.
+config TEGRA_DMA_COMMON
+ bool
+
config TEGRA20_APB_DMA
bool "NVIDIA Tegra20 APB DMA support"
depends on ARCH_TEGRA
select DMA_ENGINE
+ select TEGRA_DMA_COMMON
help
Support for the NVIDIA Tegra20 APB DMA controller driver. The
DMA controller is having multiple DMA channel which can be
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 264eb3c52446..d9c2bf5ef0bd 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -32,6 +32,7 @@ obj-$(CONFIG_SIRF_DMA) += sirf-dma.o
obj-$(CONFIG_TI_EDMA) += edma.o
obj-$(CONFIG_STE_DMA40) += ste_dma40.o ste_dma40_ll.o
obj-$(CONFIG_TEGRA20_APB_DMA) += tegra20-apb-dma.o
+obj-$(CONFIG_TEGRA_DMA_COMMON) += tegra-common.o
obj-$(CONFIG_S3C24XX_DMAC) += s3c24xx-dma.o
obj-$(CONFIG_PL330_DMA) += pl330.o
obj-$(CONFIG_PCH_DMA) += pch_dma.o
diff --git a/drivers/dma/tegra-common.c b/drivers/dma/tegra-common.c
new file mode 100644
index 000000000000..fff0a143f5bb
--- /dev/null
+++ b/drivers/dma/tegra-common.c
@@ -0,0 +1,733 @@
+/*
+ * Helper functions for NVIDIA DMA drivers.
+ *
+ * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/delay.h>
+#include <linux/dmaengine.h>
+#include <linux/interrupt.h>
+#include <linux/pm_runtime.h>
+#include <linux/slab.h>
+
+#include "dmaengine.h"
+#include "tegra-common.h"
+
+static dma_cookie_t tegra_dma_tx_submit(struct dma_async_tx_descriptor *txd)
+{
+ struct tegra_dma_desc *dma_desc = txd_to_tegra_dma_desc(txd);
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(txd->chan);
+ unsigned long flags;
+ dma_cookie_t cookie;
+
+ spin_lock_irqsave(&tdc->lock, flags);
+ dma_desc->dma_status = DMA_IN_PROGRESS;
+ cookie = dma_cookie_assign(&dma_desc->txd);
+ list_splice_tail_init(&dma_desc->tx_list, &tdc->pending_sg_req);
+ spin_unlock_irqrestore(&tdc->lock, flags);
+ return cookie;
+}
+
+/* Get DMA desc from free list, if not there then allocate it. */
+static struct tegra_dma_desc *tegra_dma_desc_get(struct tegra_dma_channel *tdc)
+{
+ struct tegra_dma_desc *dma_desc;
+ unsigned long flags;
+
+ spin_lock_irqsave(&tdc->lock, flags);
+
+ /* Do not allocate if desc are waiting for ack */
+ list_for_each_entry(dma_desc, &tdc->free_dma_desc, node) {
+ if (async_tx_test_ack(&dma_desc->txd)) {
+ list_del(&dma_desc->node);
+ spin_unlock_irqrestore(&tdc->lock, flags);
+ dma_desc->txd.flags = 0;
+ return dma_desc;
+ }
+ }
+
+ spin_unlock_irqrestore(&tdc->lock, flags);
+
+ /* Allocate DMA desc */
+ dma_desc = kzalloc(sizeof(*dma_desc), GFP_ATOMIC);
+ if (!dma_desc)
+ return NULL;
+
+ dma_async_tx_descriptor_init(&dma_desc->txd, &tdc->dma_chan);
+ dma_desc->txd.tx_submit = tegra_dma_tx_submit;
+ dma_desc->txd.flags = 0;
+ return dma_desc;
+}
+
+static void tegra_dma_desc_put(struct tegra_dma_channel *tdc,
+ struct tegra_dma_desc *dma_desc)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&tdc->lock, flags);
+ if (!list_empty(&dma_desc->tx_list))
+ list_splice_init(&dma_desc->tx_list, &tdc->free_sg_req);
+ list_add_tail(&dma_desc->node, &tdc->free_dma_desc);
+ spin_unlock_irqrestore(&tdc->lock, flags);
+}
+
+static struct tegra_dma_sg_req *tegra_dma_sg_req_get(
+ struct tegra_dma_channel *tdc)
+{
+ struct tegra_dma_sg_req *sg_req = NULL;
+ unsigned long flags;
+
+ spin_lock_irqsave(&tdc->lock, flags);
+ if (!list_empty(&tdc->free_sg_req)) {
+ sg_req = list_first_entry(&tdc->free_sg_req,
+ typeof(*sg_req), node);
+ list_del(&sg_req->node);
+ spin_unlock_irqrestore(&tdc->lock, flags);
+ return sg_req;
+ }
+ spin_unlock_irqrestore(&tdc->lock, flags);
+
+ return kzalloc(sizeof(struct tegra_dma_sg_req), GFP_ATOMIC);
+}
+
+static void tegra_dma_configure_for_next(struct tegra_dma_channel *tdc,
+ struct tegra_dma_sg_req *nsg_req)
+{
+ const struct tegra_dma_ops *ops = tdc->tdma->ops;
+ unsigned long status;
+
+ /*
+ * The DMA controller reloads the new configuration for next transfer
+ * after last burst of current transfer completes.
+ * If there is no IEC status then this makes sure that last burst
+ * has not be completed. There may be case that last burst is on
+ * flight and so it can complete but because DMA is paused, it
+ * will not generates interrupt as well as not reload the new
+ * configuration.
+ * If there is already IEC status then interrupt handler need to
+ * load new configuration.
+ */
+ ops->pause(tdc, false);
+ status = ops->irq_status(tdc);
+
+ /*
+ * If interrupt is pending then do nothing as the ISR will handle
+ * the programing for new request.
+ */
+ if (status) {
+ dev_err(tdc2dev(tdc),
+ "Skipping new configuration as interrupt is pending\n");
+ ops->resume(tdc);
+ return;
+ }
+
+ /* Safe to program new configuration */
+ ops->program(tdc, nsg_req);
+ ops->resume(tdc);
+}
+
+static void tdc_start_head_req(struct tegra_dma_channel *tdc)
+{
+ const struct tegra_dma_ops *ops = tdc->tdma->ops;
+ struct tegra_dma_sg_req *sg_req;
+
+ if (list_empty(&tdc->pending_sg_req))
+ return;
+
+ sg_req = list_first_entry(&tdc->pending_sg_req,
+ typeof(*sg_req), node);
+ ops->start(tdc, sg_req);
+ sg_req->configured = true;
+ tdc->busy = true;
+}
+
+static void tdc_configure_next_head_desc(struct tegra_dma_channel *tdc)
+{
+ struct tegra_dma_sg_req *hsgreq;
+ struct tegra_dma_sg_req *hnsgreq;
+
+ if (list_empty(&tdc->pending_sg_req))
+ return;
+
+ hsgreq = list_first_entry(&tdc->pending_sg_req, typeof(*hsgreq), node);
+ if (!list_is_last(&hsgreq->node, &tdc->pending_sg_req)) {
+ hnsgreq = list_first_entry(&hsgreq->node,
+ typeof(*hnsgreq), node);
+ tegra_dma_configure_for_next(tdc, hnsgreq);
+ }
+}
+
+static inline int get_current_xferred_count(struct tegra_dma_sg_req *sg_req,
+ unsigned long wcount)
+{
+ return sg_req->req_len - wcount;
+}
+
+static void tegra_dma_abort_all(struct tegra_dma_channel *tdc)
+{
+ struct tegra_dma_sg_req *sgreq;
+ struct tegra_dma_desc *dma_desc;
+
+ while (!list_empty(&tdc->pending_sg_req)) {
+ sgreq = list_first_entry(&tdc->pending_sg_req,
+ typeof(*sgreq), node);
+ list_move_tail(&sgreq->node, &tdc->free_sg_req);
+ if (sgreq->last_sg) {
+ dma_desc = sgreq->dma_desc;
+ dma_desc->dma_status = DMA_ERROR;
+ list_add_tail(&dma_desc->node, &tdc->free_dma_desc);
+
+ /* Add in cb list if it is not there. */
+ if (!dma_desc->cb_count)
+ list_add_tail(&dma_desc->cb_node,
+ &tdc->cb_desc);
+ dma_desc->cb_count++;
+ }
+ }
+ tdc->isr_handler = NULL;
+}
+
+static bool handle_continuous_head_request(struct tegra_dma_channel *tdc,
+ struct tegra_dma_sg_req *last_sg_req,
+ bool to_terminate)
+{
+ const struct tegra_dma_ops *ops = tdc->tdma->ops;
+ struct tegra_dma_sg_req *hsgreq = NULL;
+
+ if (list_empty(&tdc->pending_sg_req)) {
+ dev_err(tdc2dev(tdc), "Dma is running without req\n");
+ ops->stop(tdc);
+ return false;
+ }
+
+ /*
+ * Check that head req on list should be in flight.
+ * If it is not in flight then abort transfer as
+ * looping of transfer can not continue.
+ */
+ hsgreq = list_first_entry(&tdc->pending_sg_req, typeof(*hsgreq), node);
+ if (!hsgreq->configured) {
+ ops->stop(tdc);
+ dev_err(tdc2dev(tdc), "Error in dma transfer, aborting dma\n");
+ tegra_dma_abort_all(tdc);
+ return false;
+ }
+
+ /* Configure next request */
+ if (!to_terminate)
+ tdc_configure_next_head_desc(tdc);
+ return true;
+}
+
+static void handle_once_dma_done(struct tegra_dma_channel *tdc,
+ bool to_terminate)
+{
+ struct tegra_dma_sg_req *sgreq;
+ struct tegra_dma_desc *dma_desc;
+
+ tdc->busy = false;
+ sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq), node);
+ dma_desc = sgreq->dma_desc;
+ dma_desc->bytes_transferred += sgreq->req_len;
+
+ list_del(&sgreq->node);
+ if (sgreq->last_sg) {
+ dma_desc->dma_status = DMA_COMPLETE;
+ dma_cookie_complete(&dma_desc->txd);
+ if (!dma_desc->cb_count)
+ list_add_tail(&dma_desc->cb_node, &tdc->cb_desc);
+ dma_desc->cb_count++;
+ list_add_tail(&dma_desc->node, &tdc->free_dma_desc);
+ }
+ list_add_tail(&sgreq->node, &tdc->free_sg_req);
+
+ /* Do not start DMA if it is going to be terminate */
+ if (to_terminate || list_empty(&tdc->pending_sg_req))
+ return;
+
+ tdc_start_head_req(tdc);
+}
+
+static void handle_cont_sngl_cycle_dma_done(struct tegra_dma_channel *tdc,
+ bool to_terminate)
+{
+ struct tegra_dma_sg_req *sgreq;
+ struct tegra_dma_desc *dma_desc;
+ bool st;
+
+ sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq), node);
+ dma_desc = sgreq->dma_desc;
+ dma_desc->bytes_transferred += sgreq->req_len;
+
+ /* Callback need to be call */
+ if (!dma_desc->cb_count)
+ list_add_tail(&dma_desc->cb_node, &tdc->cb_desc);
+ dma_desc->cb_count++;
+
+ /* If not last req then put at end of pending list */
+ if (!list_is_last(&sgreq->node, &tdc->pending_sg_req)) {
+ list_move_tail(&sgreq->node, &tdc->pending_sg_req);
+ sgreq->configured = false;
+ st = handle_continuous_head_request(tdc, sgreq, to_terminate);
+ if (!st)
+ dma_desc->dma_status = DMA_ERROR;
+ }
+}
+
+int tegra_dma_slave_config(struct dma_chan *dc,
+ struct dma_slave_config *sconfig)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+
+ if (!list_empty(&tdc->pending_sg_req)) {
+ dev_err(tdc2dev(tdc), "Configuration not allowed\n");
+ return -EBUSY;
+ }
+
+ memcpy(&tdc->dma_sconfig, sconfig, sizeof(*sconfig));
+ if (!tdc->slave_id)
+ tdc->slave_id = sconfig->slave_id;
+ tdc->config_init = true;
+ return 0;
+}
+
+void tegra_dma_tasklet(unsigned long data)
+{
+ struct tegra_dma_channel *tdc = (struct tegra_dma_channel *)data;
+ dma_async_tx_callback callback = NULL;
+ void *callback_param = NULL;
+ struct tegra_dma_desc *dma_desc;
+ unsigned long flags;
+ int cb_count;
+
+ spin_lock_irqsave(&tdc->lock, flags);
+ while (!list_empty(&tdc->cb_desc)) {
+ dma_desc = list_first_entry(&tdc->cb_desc,
+ typeof(*dma_desc), cb_node);
+ list_del(&dma_desc->cb_node);
+ callback = dma_desc->txd.callback;
+ callback_param = dma_desc->txd.callback_param;
+ cb_count = dma_desc->cb_count;
+ dma_desc->cb_count = 0;
+ spin_unlock_irqrestore(&tdc->lock, flags);
+ while (cb_count-- && callback)
+ callback(callback_param);
+ spin_lock_irqsave(&tdc->lock, flags);
+ }
+ spin_unlock_irqrestore(&tdc->lock, flags);
+}
+
+irqreturn_t tegra_dma_isr(int irq, void *dev_id)
+{
+ struct tegra_dma_channel *tdc = dev_id;
+ const struct tegra_dma_ops *ops = tdc->tdma->ops;
+ unsigned long status;
+ unsigned long flags;
+
+ spin_lock_irqsave(&tdc->lock, flags);
+
+ status = ops->irq_clear(tdc);
+ if (status) {
+ tdc->isr_handler(tdc, false);
+ tasklet_schedule(&tdc->tasklet);
+ spin_unlock_irqrestore(&tdc->lock, flags);
+ return IRQ_HANDLED;
+ }
+
+ spin_unlock_irqrestore(&tdc->lock, flags);
+ dev_info(tdc2dev(tdc),
+ "Interrupt already served status 0x%08lx\n", status);
+ return IRQ_NONE;
+}
+
+void tegra_dma_issue_pending(struct dma_chan *dc)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+ unsigned long flags;
+
+ spin_lock_irqsave(&tdc->lock, flags);
+ if (list_empty(&tdc->pending_sg_req)) {
+ dev_err(tdc2dev(tdc), "No DMA request\n");
+ goto end;
+ }
+ if (!tdc->busy) {
+ tdc_start_head_req(tdc);
+
+ /* Continuous single mode: Configure next req */
+ if (tdc->cyclic) {
+ /*
+ * Wait for 1 burst time for configure DMA for
+ * next transfer.
+ */
+ udelay(tdc->tdma->chip_data->burst_time);
+ tdc_configure_next_head_desc(tdc);
+ }
+ }
+end:
+ spin_unlock_irqrestore(&tdc->lock, flags);
+}
+
+int tegra_dma_terminate_all(struct dma_chan *dc)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+ const struct tegra_dma_ops *ops = tdc->tdma->ops;
+ struct tegra_dma_sg_req *sgreq;
+ struct tegra_dma_desc *dma_desc;
+ unsigned long flags;
+ unsigned long status;
+ unsigned long wcount;
+ bool was_busy;
+
+ spin_lock_irqsave(&tdc->lock, flags);
+ if (list_empty(&tdc->pending_sg_req)) {
+ spin_unlock_irqrestore(&tdc->lock, flags);
+ return 0;
+ }
+
+ if (!tdc->busy)
+ goto skip_dma_stop;
+
+ /* Pause DMA before checking the queue status */
+ ops->pause(tdc, true);
+
+ status = ops->irq_status(tdc);
+ if (status) {
+ dev_dbg(tdc2dev(tdc), "%s():handling isr\n", __func__);
+ tdc->isr_handler(tdc, true);
+ }
+
+ wcount = ops->get_xfer_count(tdc);
+
+ was_busy = tdc->busy;
+ ops->stop(tdc);
+
+ if (!list_empty(&tdc->pending_sg_req) && was_busy) {
+ sgreq = list_first_entry(&tdc->pending_sg_req,
+ typeof(*sgreq), node);
+ sgreq->dma_desc->bytes_transferred +=
+ get_current_xferred_count(sgreq, wcount);
+ }
+ ops->resume(tdc);
+
+skip_dma_stop:
+ tegra_dma_abort_all(tdc);
+
+ while (!list_empty(&tdc->cb_desc)) {
+ dma_desc = list_first_entry(&tdc->cb_desc,
+ typeof(*dma_desc), cb_node);
+ list_del(&dma_desc->cb_node);
+ dma_desc->cb_count = 0;
+ }
+ spin_unlock_irqrestore(&tdc->lock, flags);
+ return 0;
+}
+
+enum dma_status tegra_dma_tx_status(struct dma_chan *dc, dma_cookie_t cookie,
+ struct dma_tx_state *txstate)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+ struct tegra_dma_desc *dma_desc;
+ struct tegra_dma_sg_req *sg_req;
+ enum dma_status ret;
+ unsigned long flags;
+ unsigned int residual;
+
+ ret = dma_cookie_status(dc, cookie, txstate);
+ if (ret == DMA_COMPLETE)
+ return ret;
+
+ spin_lock_irqsave(&tdc->lock, flags);
+
+ /* Check on wait_ack desc status */
+ list_for_each_entry(dma_desc, &tdc->free_dma_desc, node) {
+ if (dma_desc->txd.cookie == cookie) {
+ residual = dma_desc->bytes_requested -
+ (dma_desc->bytes_transferred %
+ dma_desc->bytes_requested);
+ dma_set_residue(txstate, residual);
+ ret = dma_desc->dma_status;
+ spin_unlock_irqrestore(&tdc->lock, flags);
+ return ret;
+ }
+ }
+
+ /* Check in pending list */
+ list_for_each_entry(sg_req, &tdc->pending_sg_req, node) {
+ dma_desc = sg_req->dma_desc;
+ if (dma_desc->txd.cookie == cookie) {
+ residual = dma_desc->bytes_requested -
+ (dma_desc->bytes_transferred %
+ dma_desc->bytes_requested);
+ dma_set_residue(txstate, residual);
+ ret = dma_desc->dma_status;
+ spin_unlock_irqrestore(&tdc->lock, flags);
+ return ret;
+ }
+ }
+
+ dev_dbg(tdc2dev(tdc), "cookie %d does not found\n", cookie);
+ spin_unlock_irqrestore(&tdc->lock, flags);
+ return ret;
+}
+
+struct dma_async_tx_descriptor *tegra_dma_prep_slave_sg(
+ struct dma_chan *dc, struct scatterlist *sgl, unsigned int sg_len,
+ enum dma_transfer_direction direction, unsigned long flags,
+ void *context)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+ const struct tegra_dma_ops *ops = tdc->tdma->ops;
+ struct tegra_dma_desc *dma_desc;
+ unsigned int i;
+ struct scatterlist *sg;
+ struct list_head req_list;
+ struct tegra_dma_sg_req sg_base, *sg_req = NULL;
+
+ if (!tdc->config_init) {
+ dev_err(tdc2dev(tdc), "dma channel is not configured\n");
+ return NULL;
+ }
+ if (sg_len < 1) {
+ dev_err(tdc2dev(tdc), "Invalid segment length %d\n", sg_len);
+ return NULL;
+ }
+
+ if (ops->get_xfer_params_sg(tdc, &sg_base, direction, flags) < 0)
+ return NULL;
+
+ INIT_LIST_HEAD(&req_list);
+
+ dma_desc = tegra_dma_desc_get(tdc);
+ if (!dma_desc) {
+ dev_err(tdc2dev(tdc), "Dma descriptors not available\n");
+ return NULL;
+ }
+ INIT_LIST_HEAD(&dma_desc->tx_list);
+ INIT_LIST_HEAD(&dma_desc->cb_node);
+ dma_desc->cb_count = 0;
+ dma_desc->bytes_requested = 0;
+ dma_desc->bytes_transferred = 0;
+ dma_desc->dma_status = DMA_IN_PROGRESS;
+
+ /* Make transfer requests */
+ for_each_sg(sgl, sg, sg_len, i) {
+ u32 len, mem;
+
+ mem = sg_dma_address(sg);
+ len = sg_dma_len(sg);
+
+ if ((len & 3) || (mem & 3) ||
+ (len > tdc->tdma->chip_data->max_dma_count)) {
+ dev_err(tdc2dev(tdc),
+ "Dma length/memory address is not supported\n");
+ tegra_dma_desc_put(tdc, dma_desc);
+ return NULL;
+ }
+
+ sg_req = tegra_dma_sg_req_get(tdc);
+ if (!sg_req) {
+ dev_err(tdc2dev(tdc), "Dma sg-req not available\n");
+ tegra_dma_desc_put(tdc, dma_desc);
+ return NULL;
+ }
+
+ dma_desc->bytes_requested += len;
+
+ ops->set_xfer_params(tdc, sg_req, &sg_base, direction, mem,
+ len);
+ sg_req->dma_desc = dma_desc;
+
+ list_add_tail(&sg_req->node, &dma_desc->tx_list);
+ }
+ sg_req->last_sg = true;
+ if (flags & DMA_CTRL_ACK)
+ dma_desc->txd.flags = DMA_CTRL_ACK;
+
+ /*
+ * Make sure that mode should not be conflicting with currently
+ * configured mode.
+ */
+ if (!tdc->isr_handler) {
+ tdc->isr_handler = handle_once_dma_done;
+ tdc->cyclic = false;
+ } else {
+ if (tdc->cyclic) {
+ dev_err(tdc2dev(tdc), "DMA configured in cyclic mode\n");
+ tegra_dma_desc_put(tdc, dma_desc);
+ return NULL;
+ }
+ }
+
+ return &dma_desc->txd;
+}
+
+struct dma_async_tx_descriptor *tegra_dma_prep_dma_cyclic(
+ struct dma_chan *dc, dma_addr_t buf_addr, size_t buf_len,
+ size_t period_len, enum dma_transfer_direction direction,
+ unsigned long flags)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+ const struct tegra_dma_ops *ops = tdc->tdma->ops;
+ struct tegra_dma_desc *dma_desc = NULL;
+ struct tegra_dma_sg_req sg_base, *sg_req = NULL;
+ int len;
+ size_t remain_len;
+ dma_addr_t mem = buf_addr;
+
+ if (!buf_len || !period_len) {
+ dev_err(tdc2dev(tdc), "Invalid buffer/period len\n");
+ return NULL;
+ }
+
+ if (!tdc->config_init) {
+ dev_err(tdc2dev(tdc), "DMA slave is not configured\n");
+ return NULL;
+ }
+
+ /*
+ * We allow to take more number of requests till DMA is
+ * not started. The driver will loop over all requests.
+ * Once DMA is started then new requests can be queued only after
+ * terminating the DMA.
+ */
+ if (tdc->busy) {
+ dev_err(tdc2dev(tdc), "Request not allowed when dma running\n");
+ return NULL;
+ }
+
+ /*
+ * We only support cycle transfer when buf_len is multiple of
+ * period_len.
+ */
+ if (buf_len % period_len) {
+ dev_err(tdc2dev(tdc), "buf_len is not multiple of period_len\n");
+ return NULL;
+ }
+
+ len = period_len;
+ if ((len & 3) || (buf_addr & 3) ||
+ (len > tdc->tdma->chip_data->max_dma_count)) {
+ dev_err(tdc2dev(tdc), "Req len/mem address is not correct\n");
+ return NULL;
+ }
+
+ if (ops->get_xfer_params_cyclic(tdc, &sg_base, direction, flags) < 0)
+ return NULL;
+
+ dma_desc = tegra_dma_desc_get(tdc);
+ if (!dma_desc) {
+ dev_err(tdc2dev(tdc), "not enough descriptors available\n");
+ return NULL;
+ }
+
+ INIT_LIST_HEAD(&dma_desc->tx_list);
+ INIT_LIST_HEAD(&dma_desc->cb_node);
+ dma_desc->cb_count = 0;
+
+ dma_desc->bytes_transferred = 0;
+ dma_desc->bytes_requested = buf_len;
+ remain_len = buf_len;
+
+ /* Split transfer equal to period size */
+ while (remain_len) {
+ sg_req = tegra_dma_sg_req_get(tdc);
+ if (!sg_req) {
+ dev_err(tdc2dev(tdc), "Dma sg-req not available\n");
+ tegra_dma_desc_put(tdc, dma_desc);
+ return NULL;
+ }
+
+ ops->set_xfer_params(tdc, sg_req, &sg_base, direction, mem,
+ len);
+ sg_req->dma_desc = dma_desc;
+
+ list_add_tail(&sg_req->node, &dma_desc->tx_list);
+ remain_len -= len;
+ mem += len;
+ }
+ sg_req->last_sg = true;
+ if (flags & DMA_CTRL_ACK)
+ dma_desc->txd.flags = DMA_CTRL_ACK;
+
+ /*
+ * Make sure that mode should not be conflicting with currently
+ * configured mode.
+ */
+ if (!tdc->isr_handler) {
+ tdc->isr_handler = handle_cont_sngl_cycle_dma_done;
+ tdc->cyclic = true;
+ } else {
+ if (!tdc->cyclic) {
+ dev_err(tdc2dev(tdc), "DMA configuration conflict\n");
+ tegra_dma_desc_put(tdc, dma_desc);
+ return NULL;
+ }
+ }
+
+ return &dma_desc->txd;
+}
+
+int tegra_dma_alloc_chan_resources(struct dma_chan *dc)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+ struct tegra_dma *tdma = tdc->tdma;
+
+ dma_cookie_init(&tdc->dma_chan);
+ tdc->config_init = false;
+
+ return pm_runtime_get_sync(tdma->dev);
+}
+
+void tegra_dma_free_chan_resources(struct dma_chan *dc)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+ struct tegra_dma *tdma = tdc->tdma;
+
+ struct tegra_dma_desc *dma_desc;
+ struct tegra_dma_sg_req *sg_req;
+ struct list_head dma_desc_list;
+ struct list_head sg_req_list;
+ unsigned long flags;
+
+ INIT_LIST_HEAD(&dma_desc_list);
+ INIT_LIST_HEAD(&sg_req_list);
+
+ dev_dbg(tdc2dev(tdc), "Freeing channel %d\n", tdc->id);
+
+ if (tdc->busy)
+ tegra_dma_terminate_all(dc);
+
+ spin_lock_irqsave(&tdc->lock, flags);
+ list_splice_init(&tdc->pending_sg_req, &sg_req_list);
+ list_splice_init(&tdc->free_sg_req, &sg_req_list);
+ list_splice_init(&tdc->free_dma_desc, &dma_desc_list);
+ INIT_LIST_HEAD(&tdc->cb_desc);
+ tdc->config_init = false;
+ tdc->isr_handler = NULL;
+ spin_unlock_irqrestore(&tdc->lock, flags);
+
+ while (!list_empty(&dma_desc_list)) {
+ dma_desc = list_first_entry(&dma_desc_list,
+ typeof(*dma_desc), node);
+ list_del(&dma_desc->node);
+ kfree(dma_desc);
+ }
+
+ while (!list_empty(&sg_req_list)) {
+ sg_req = list_first_entry(&sg_req_list, typeof(*sg_req), node);
+ list_del(&sg_req->node);
+ kfree(sg_req);
+ }
+ pm_runtime_put(tdma->dev);
+
+ tdc->slave_id = 0;
+}
diff --git a/drivers/dma/tegra-common.h b/drivers/dma/tegra-common.h
new file mode 100644
index 000000000000..e0d4d2b13cb8
--- /dev/null
+++ b/drivers/dma/tegra-common.h
@@ -0,0 +1,226 @@
+/*
+ * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/*
+ * tegra_dma_chip_data Tegra chip specific DMA data
+ * @nr_channels: Number of channels available in the controller.
+ * @channel_reg_size: Channel register size/stride.
+ * @max_dma_count: Maximum DMA transfer count supported by DMA controller.
+ * @support_channel_pause: Support channel wise pause of dma.
+ * @support_separate_wcount_reg: Support separate word count register.
+ */
+struct tegra_dma_chip_data {
+ int burst_time;
+ int nr_channels;
+ int channel_reg_size;
+ int max_dma_count;
+ bool support_channel_pause;
+ bool support_separate_wcount_reg;
+};
+
+/*
+ * DMA channel registers
+ */
+struct tegra_dma_channel_regs {
+ unsigned long csr;
+ unsigned long ahb_ptr;
+ unsigned long apb_ptr;
+ unsigned long ahb_seq;
+ unsigned long apb_seq;
+ unsigned long wcount;
+};
+
+/*
+ * tegra_dma_sg_req: Dma request details to configure hardware. This
+ * contains the details for one transfer to configure DMA hw.
+ * The client's request for data transfer can be broken into multiple
+ * sub-transfer as per requester details and hw support.
+ * This sub transfer get added in the list of transfer and point to Tegra
+ * DMA descriptor which manages the transfer details.
+ */
+struct tegra_dma_sg_req {
+ struct tegra_dma_channel_regs ch_regs;
+ int req_len;
+ bool configured;
+ bool last_sg;
+ struct list_head node;
+ struct tegra_dma_desc *dma_desc;
+};
+
+/*
+ * tegra_dma_desc: Tegra DMA descriptors which manages the client requests.
+ * This descriptor keep track of transfer status, callbacks and request
+ * counts etc.
+ */
+struct tegra_dma_desc {
+ struct dma_async_tx_descriptor txd;
+ int bytes_requested;
+ int bytes_transferred;
+ enum dma_status dma_status;
+ struct list_head node;
+ struct list_head tx_list;
+ struct list_head cb_node;
+ int cb_count;
+};
+
+struct tegra_dma_channel;
+
+typedef void (*dma_isr_handler)(struct tegra_dma_channel *tdc,
+ bool to_terminate);
+
+/*
+ * tegra_dma_channel: Channel specific information
+ */
+struct tegra_dma_channel {
+ struct dma_chan dma_chan;
+ char name[30];
+ bool config_init;
+ int id;
+ int irq;
+ void __iomem *chan_addr;
+ spinlock_t lock;
+ bool busy;
+ struct tegra_dma *tdma;
+ bool cyclic;
+
+ /* Different lists for managing the requests */
+ struct list_head free_sg_req;
+ struct list_head pending_sg_req;
+ struct list_head free_dma_desc;
+ struct list_head cb_desc;
+
+ /* ISR handler and tasklet for bottom half of isr handling */
+ dma_isr_handler isr_handler;
+ struct tasklet_struct tasklet;
+
+ /* Channel-slave specific configuration */
+ unsigned int slave_id;
+ struct dma_slave_config dma_sconfig;
+ struct tegra_dma_channel_regs channel_reg;
+};
+
+/*
+ * tegra_dma_ops: Tegra DMA function table
+ */
+struct tegra_dma_ops {
+ u32 (*get_xfer_count)(struct tegra_dma_channel *tdc);
+ int (*get_xfer_params_cyclic)(struct tegra_dma_channel *tdc,
+ struct tegra_dma_sg_req *sg_req,
+ enum dma_transfer_direction direction,
+ unsigned int flags);
+ int (*get_xfer_params_sg)(struct tegra_dma_channel *tdc,
+ struct tegra_dma_sg_req *sg_req,
+ enum dma_transfer_direction direction,
+ unsigned int flags);
+ u32 (*irq_clear)(struct tegra_dma_channel *tdc);
+ u32 (*irq_status)(struct tegra_dma_channel *tdc);
+ void (*pause)(struct tegra_dma_channel *tdc,
+ bool wait_for_burst_complete);
+ void (*program)(struct tegra_dma_channel *tdc,
+ struct tegra_dma_sg_req *sg_req);
+ void (*resume)(struct tegra_dma_channel *tdc);
+ void (*set_xfer_params)(struct tegra_dma_channel *tdc,
+ struct tegra_dma_sg_req *sg_req,
+ struct tegra_dma_sg_req *sg_base,
+ enum dma_transfer_direction direction,
+ u32 mem, u32 len);
+ void (*start)(struct tegra_dma_channel *tdc,
+ struct tegra_dma_sg_req *sg_req);
+ void (*stop)(struct tegra_dma_channel *tdc);
+};
+
+/*
+ * tegra_dma: Tegra DMA specific information
+ */
+struct tegra_dma {
+ struct dma_device dma_dev;
+ struct device *dev;
+ struct clk *dma_clk;
+ struct reset_control *rst;
+ spinlock_t global_lock;
+ void __iomem *base_addr;
+ const struct tegra_dma_chip_data *chip_data;
+ const struct tegra_dma_ops *ops;
+
+ /*
+ * Counter for managing global pausing of the DMA controller.
+ * Only applicable for devices that don't support individual
+ * channel pausing.
+ */
+ u32 global_pause_count;
+
+ /* Some register need to be cache before suspend */
+ u32 reg_gen;
+
+ /* Last member of the structure */
+ struct tegra_dma_channel channels[0];
+};
+
+static inline void tdma_write(struct tegra_dma *tdma, u32 reg, u32 val)
+{
+ writel(val, tdma->base_addr + reg);
+}
+
+static inline u32 tdma_read(struct tegra_dma *tdma, u32 reg)
+{
+ return readl(tdma->base_addr + reg);
+}
+
+static inline void tdc_write(struct tegra_dma_channel *tdc,
+ u32 reg, u32 val)
+{
+ writel(val, tdc->chan_addr + reg);
+}
+
+static inline u32 tdc_read(struct tegra_dma_channel *tdc, u32 reg)
+{
+ return readl(tdc->chan_addr + reg);
+}
+
+static inline struct tegra_dma_channel *to_tegra_dma_chan(struct dma_chan *dc)
+{
+ return container_of(dc, struct tegra_dma_channel, dma_chan);
+}
+
+static inline struct tegra_dma_desc *txd_to_tegra_dma_desc(
+ struct dma_async_tx_descriptor *td)
+{
+ return container_of(td, struct tegra_dma_desc, txd);
+}
+
+static inline struct device *tdc2dev(struct tegra_dma_channel *tdc)
+{
+ return &tdc->dma_chan.dev->device;
+}
+
+irqreturn_t tegra_dma_isr(int irq, void *dev_id);
+void tegra_dma_issue_pending(struct dma_chan *dc);
+int tegra_dma_slave_config(struct dma_chan *dc,
+ struct dma_slave_config *sconfig);
+void tegra_dma_tasklet(unsigned long data);
+enum dma_status tegra_dma_tx_status(struct dma_chan *dc, dma_cookie_t cookie,
+ struct dma_tx_state *txstate);
+int tegra_dma_terminate_all(struct dma_chan *dc);
+struct dma_async_tx_descriptor *tegra_dma_prep_slave_sg(
+ struct dma_chan *dc, struct scatterlist *sgl, unsigned int sg_len,
+ enum dma_transfer_direction direction, unsigned long flags,
+ void *context);
+struct dma_async_tx_descriptor *tegra_dma_prep_dma_cyclic(
+ struct dma_chan *dc, dma_addr_t buf_addr, size_t buf_len,
+ size_t period_len, enum dma_transfer_direction direction,
+ unsigned long flags);
+int tegra_dma_alloc_chan_resources(struct dma_chan *dc);
+void tegra_dma_free_chan_resources(struct dma_chan *dc);
diff --git a/drivers/dma/tegra20-apb-dma.c b/drivers/dma/tegra20-apb-dma.c
index 7947acdf23db..0895732aaa28 100644
--- a/drivers/dma/tegra20-apb-dma.c
+++ b/drivers/dma/tegra20-apb-dma.c
@@ -38,6 +38,8 @@
#include "dmaengine.h"
+#include "tegra-common.h"
+
#define TEGRA_APBDMA_GENERAL 0x0
#define TEGRA_APBDMA_GENERAL_ENABLE BIT(31)
@@ -114,279 +116,9 @@
/* Channel base address offset from APBDMA base address */
#define TEGRA_APBDMA_CHANNEL_BASE_ADD_OFFSET 0x1000
-struct tegra_dma;
-
-/*
- * tegra_dma_chip_data Tegra chip specific DMA data
- * @nr_channels: Number of channels available in the controller.
- * @channel_reg_size: Channel register size/stride.
- * @max_dma_count: Maximum DMA transfer count supported by DMA controller.
- * @support_channel_pause: Support channel wise pause of dma.
- * @support_separate_wcount_reg: Support separate word count register.
- */
-struct tegra_dma_chip_data {
- int nr_channels;
- int channel_reg_size;
- int max_dma_count;
- bool support_channel_pause;
- bool support_separate_wcount_reg;
-};
-
-/* DMA channel registers */
-struct tegra_dma_channel_regs {
- unsigned long csr;
- unsigned long ahb_ptr;
- unsigned long apb_ptr;
- unsigned long ahb_seq;
- unsigned long apb_seq;
- unsigned long wcount;
-};
-
-/*
- * tegra_dma_sg_req: Dma request details to configure hardware. This
- * contains the details for one transfer to configure DMA hw.
- * The client's request for data transfer can be broken into multiple
- * sub-transfer as per requester details and hw support.
- * This sub transfer get added in the list of transfer and point to Tegra
- * DMA descriptor which manages the transfer details.
- */
-struct tegra_dma_sg_req {
- struct tegra_dma_channel_regs ch_regs;
- int req_len;
- bool configured;
- bool last_sg;
- struct list_head node;
- struct tegra_dma_desc *dma_desc;
-};
-
-/*
- * tegra_dma_desc: Tegra DMA descriptors which manages the client requests.
- * This descriptor keep track of transfer status, callbacks and request
- * counts etc.
- */
-struct tegra_dma_desc {
- struct dma_async_tx_descriptor txd;
- int bytes_requested;
- int bytes_transferred;
- enum dma_status dma_status;
- struct list_head node;
- struct list_head tx_list;
- struct list_head cb_node;
- int cb_count;
-};
-
-struct tegra_dma_channel;
-
-typedef void (*dma_isr_handler)(struct tegra_dma_channel *tdc,
- bool to_terminate);
-
-/* tegra_dma_channel: Channel specific information */
-struct tegra_dma_channel {
- struct dma_chan dma_chan;
- char name[30];
- bool config_init;
- int id;
- int irq;
- void __iomem *chan_addr;
- spinlock_t lock;
- bool busy;
- struct tegra_dma *tdma;
- bool cyclic;
-
- /* Different lists for managing the requests */
- struct list_head free_sg_req;
- struct list_head pending_sg_req;
- struct list_head free_dma_desc;
- struct list_head cb_desc;
-
- /* ISR handler and tasklet for bottom half of isr handling */
- dma_isr_handler isr_handler;
- struct tasklet_struct tasklet;
-
- /* Channel-slave specific configuration */
- unsigned int slave_id;
- struct dma_slave_config dma_sconfig;
- struct tegra_dma_channel_regs channel_reg;
-};
-
-struct tegra_dma_ops {
- u32 (*get_xfer_count)(struct tegra_dma_channel *tdc);
- int (*get_xfer_params_cyclic)(struct tegra_dma_channel *tdc,
- struct tegra_dma_sg_req *sg_req,
- enum dma_transfer_direction direction,
- unsigned int flags);
- int (*get_xfer_params_sg)(struct tegra_dma_channel *tdc,
- struct tegra_dma_sg_req *sg_req,
- enum dma_transfer_direction direction,
- unsigned int flags);
- u32 (*irq_clear)(struct tegra_dma_channel *tdc);
- u32 (*irq_status)(struct tegra_dma_channel *tdc);
- void (*pause)(struct tegra_dma_channel *tdc,
- bool wait_for_burst_complete);
- void (*program)(struct tegra_dma_channel *tdc,
- struct tegra_dma_sg_req *sg_req);
- void (*resume)(struct tegra_dma_channel *tdc);
- void (*set_xfer_params)(struct tegra_dma_channel *tdc,
- struct tegra_dma_sg_req *sg_req,
- struct tegra_dma_sg_req *sg_base,
- enum dma_transfer_direction direction,
- u32 mem, u32 len);
- void (*start)(struct tegra_dma_channel *tdc,
- struct tegra_dma_sg_req *sg_req);
- void (*stop)(struct tegra_dma_channel *tdc);
-};
-
-/* tegra_dma: Tegra DMA specific information */
-struct tegra_dma {
- struct dma_device dma_dev;
- struct device *dev;
- struct clk *dma_clk;
- struct reset_control *rst;
- spinlock_t global_lock;
- void __iomem *base_addr;
- const struct tegra_dma_chip_data *chip_data;
- const struct tegra_dma_ops *ops;
-
- /*
- * Counter for managing global pausing of the DMA controller.
- * Only applicable for devices that don't support individual
- * channel pausing.
- */
- u32 global_pause_count;
-
- /* Some register need to be cache before suspend */
- u32 reg_gen;
-
- /* Last member of the structure */
- struct tegra_dma_channel channels[0];
-};
-
-static inline void tdma_write(struct tegra_dma *tdma, u32 reg, u32 val)
-{
- writel(val, tdma->base_addr + reg);
-}
-
-static inline u32 tdma_read(struct tegra_dma *tdma, u32 reg)
-{
- return readl(tdma->base_addr + reg);
-}
-
-static inline void tdc_write(struct tegra_dma_channel *tdc,
- u32 reg, u32 val)
-{
- writel(val, tdc->chan_addr + reg);
-}
-
-static inline u32 tdc_read(struct tegra_dma_channel *tdc, u32 reg)
-{
- return readl(tdc->chan_addr + reg);
-}
-
-static inline struct tegra_dma_channel *to_tegra_dma_chan(struct dma_chan *dc)
-{
- return container_of(dc, struct tegra_dma_channel, dma_chan);
-}
-
-static inline struct tegra_dma_desc *txd_to_tegra_dma_desc(
- struct dma_async_tx_descriptor *td)
-{
- return container_of(td, struct tegra_dma_desc, txd);
-}
-
-static inline struct device *tdc2dev(struct tegra_dma_channel *tdc)
-{
- return &tdc->dma_chan.dev->device;
-}
-
-static dma_cookie_t tegra_dma_tx_submit(struct dma_async_tx_descriptor *tx);
static int tegra_dma_runtime_suspend(struct device *dev);
static int tegra_dma_runtime_resume(struct device *dev);
-/* Get DMA desc from free list, if not there then allocate it. */
-static struct tegra_dma_desc *tegra_dma_desc_get(
- struct tegra_dma_channel *tdc)
-{
- struct tegra_dma_desc *dma_desc;
- unsigned long flags;
-
- spin_lock_irqsave(&tdc->lock, flags);
-
- /* Do not allocate if desc are waiting for ack */
- list_for_each_entry(dma_desc, &tdc->free_dma_desc, node) {
- if (async_tx_test_ack(&dma_desc->txd)) {
- list_del(&dma_desc->node);
- spin_unlock_irqrestore(&tdc->lock, flags);
- dma_desc->txd.flags = 0;
- return dma_desc;
- }
- }
-
- spin_unlock_irqrestore(&tdc->lock, flags);
-
- /* Allocate DMA desc */
- dma_desc = kzalloc(sizeof(*dma_desc), GFP_ATOMIC);
- if (!dma_desc) {
- dev_err(tdc2dev(tdc), "dma_desc alloc failed\n");
- return NULL;
- }
-
- dma_async_tx_descriptor_init(&dma_desc->txd, &tdc->dma_chan);
- dma_desc->txd.tx_submit = tegra_dma_tx_submit;
- dma_desc->txd.flags = 0;
- return dma_desc;
-}
-
-static void tegra_dma_desc_put(struct tegra_dma_channel *tdc,
- struct tegra_dma_desc *dma_desc)
-{
- unsigned long flags;
-
- spin_lock_irqsave(&tdc->lock, flags);
- if (!list_empty(&dma_desc->tx_list))
- list_splice_init(&dma_desc->tx_list, &tdc->free_sg_req);
- list_add_tail(&dma_desc->node, &tdc->free_dma_desc);
- spin_unlock_irqrestore(&tdc->lock, flags);
-}
-
-static struct tegra_dma_sg_req *tegra_dma_sg_req_get(
- struct tegra_dma_channel *tdc)
-{
- struct tegra_dma_sg_req *sg_req = NULL;
- unsigned long flags;
-
- spin_lock_irqsave(&tdc->lock, flags);
- if (!list_empty(&tdc->free_sg_req)) {
- sg_req = list_first_entry(&tdc->free_sg_req,
- typeof(*sg_req), node);
- list_del(&sg_req->node);
- spin_unlock_irqrestore(&tdc->lock, flags);
- return sg_req;
- }
- spin_unlock_irqrestore(&tdc->lock, flags);
-
- sg_req = kzalloc(sizeof(struct tegra_dma_sg_req), GFP_ATOMIC);
- if (!sg_req)
- dev_err(tdc2dev(tdc), "sg_req alloc failed\n");
- return sg_req;
-}
-
-static int tegra_dma_slave_config(struct dma_chan *dc,
- struct dma_slave_config *sconfig)
-{
- struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
-
- if (!list_empty(&tdc->pending_sg_req)) {
- dev_err(tdc2dev(tdc), "Configuration not allowed\n");
- return -EBUSY;
- }
-
- memcpy(&tdc->dma_sconfig, sconfig, sizeof(*sconfig));
- if (!tdc->slave_id)
- tdc->slave_id = sconfig->slave_id;
- tdc->config_init = true;
- return 0;
-}
-
static u32 tegra_dma_get_xfer_count(struct tegra_dma_channel *tdc)
{
u32 wcount;
@@ -409,7 +141,7 @@ static void tegra_dma_global_pause(struct tegra_dma_channel *tdc,
if (tdc->tdma->global_pause_count == 0) {
tdma_write(tdma, TEGRA_APBDMA_GENERAL, 0);
if (wait_for_burst_complete)
- udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME);
+ udelay(tdma->chip_data->burst_time);
}
tdc->tdma->global_pause_count++;
@@ -475,7 +207,7 @@ static void tegra_dma_pause(struct tegra_dma_channel *tdc,
tdc_write(tdc, TEGRA_APBDMA_CHAN_CSRE,
TEGRA_APBDMA_CHAN_CSRE_PAUSE);
if (wait_for_burst_complete)
- udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME);
+ udelay(tdma->chip_data->burst_time);
} else {
tegra_dma_global_pause(tdc, wait_for_burst_complete);
}
@@ -529,383 +261,6 @@ static void tegra_dma_start(struct tegra_dma_channel *tdc,
ch_regs->csr | TEGRA_APBDMA_CSR_ENB);
}
-static void tegra_dma_configure_for_next(struct tegra_dma_channel *tdc,
- struct tegra_dma_sg_req *nsg_req)
-{
- const struct tegra_dma_ops *ops = tdc->tdma->ops;
- unsigned long status;
-
- /*
- * The DMA controller reloads the new configuration for next transfer
- * after last burst of current transfer completes.
- * If there is no IEC status then this makes sure that last burst
- * has not be completed. There may be case that last burst is on
- * flight and so it can complete but because DMA is paused, it
- * will not generates interrupt as well as not reload the new
- * configuration.
- * If there is already IEC status then interrupt handler need to
- * load new configuration.
- */
- ops->pause(tdc, false);
- status = ops->irq_status(tdc);
-
- /*
- * If interrupt is pending then do nothing as the ISR will handle
- * the programing for new request.
- */
- if (status) {
- dev_err(tdc2dev(tdc),
- "Skipping new configuration as interrupt is pending\n");
- ops->resume(tdc);
- return;
- }
-
- /* Safe to program new configuration */
- ops->program(tdc, nsg_req);
- ops->resume(tdc);
-}
-
-static void tdc_start_head_req(struct tegra_dma_channel *tdc)
-{
- const struct tegra_dma_ops *ops = tdc->tdma->ops;
- struct tegra_dma_sg_req *sg_req;
-
- if (list_empty(&tdc->pending_sg_req))
- return;
-
- sg_req = list_first_entry(&tdc->pending_sg_req,
- typeof(*sg_req), node);
- ops->start(tdc, sg_req);
- sg_req->configured = true;
- tdc->busy = true;
-}
-
-static void tdc_configure_next_head_desc(struct tegra_dma_channel *tdc)
-{
- struct tegra_dma_sg_req *hsgreq;
- struct tegra_dma_sg_req *hnsgreq;
-
- if (list_empty(&tdc->pending_sg_req))
- return;
-
- hsgreq = list_first_entry(&tdc->pending_sg_req, typeof(*hsgreq), node);
- if (!list_is_last(&hsgreq->node, &tdc->pending_sg_req)) {
- hnsgreq = list_first_entry(&hsgreq->node,
- typeof(*hnsgreq), node);
- tegra_dma_configure_for_next(tdc, hnsgreq);
- }
-}
-
-static inline int get_current_xferred_count(struct tegra_dma_sg_req *sg_req,
- unsigned long wcount)
-{
- return sg_req->req_len - wcount;
-}
-
-static void tegra_dma_abort_all(struct tegra_dma_channel *tdc)
-{
- struct tegra_dma_sg_req *sgreq;
- struct tegra_dma_desc *dma_desc;
-
- while (!list_empty(&tdc->pending_sg_req)) {
- sgreq = list_first_entry(&tdc->pending_sg_req,
- typeof(*sgreq), node);
- list_move_tail(&sgreq->node, &tdc->free_sg_req);
- if (sgreq->last_sg) {
- dma_desc = sgreq->dma_desc;
- dma_desc->dma_status = DMA_ERROR;
- list_add_tail(&dma_desc->node, &tdc->free_dma_desc);
-
- /* Add in cb list if it is not there. */
- if (!dma_desc->cb_count)
- list_add_tail(&dma_desc->cb_node,
- &tdc->cb_desc);
- dma_desc->cb_count++;
- }
- }
- tdc->isr_handler = NULL;
-}
-
-static bool handle_continuous_head_request(struct tegra_dma_channel *tdc,
- struct tegra_dma_sg_req *last_sg_req, bool to_terminate)
-{
- const struct tegra_dma_ops *ops = tdc->tdma->ops;
- struct tegra_dma_sg_req *hsgreq = NULL;
-
- if (list_empty(&tdc->pending_sg_req)) {
- dev_err(tdc2dev(tdc), "Dma is running without req\n");
- ops->stop(tdc);
- return false;
- }
-
- /*
- * Check that head req on list should be in flight.
- * If it is not in flight then abort transfer as
- * looping of transfer can not continue.
- */
- hsgreq = list_first_entry(&tdc->pending_sg_req, typeof(*hsgreq), node);
- if (!hsgreq->configured) {
- ops->stop(tdc);
- dev_err(tdc2dev(tdc), "Error in dma transfer, aborting dma\n");
- tegra_dma_abort_all(tdc);
- return false;
- }
-
- /* Configure next request */
- if (!to_terminate)
- tdc_configure_next_head_desc(tdc);
- return true;
-}
-
-static void handle_once_dma_done(struct tegra_dma_channel *tdc,
- bool to_terminate)
-{
- struct tegra_dma_sg_req *sgreq;
- struct tegra_dma_desc *dma_desc;
-
- tdc->busy = false;
- sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq), node);
- dma_desc = sgreq->dma_desc;
- dma_desc->bytes_transferred += sgreq->req_len;
-
- list_del(&sgreq->node);
- if (sgreq->last_sg) {
- dma_desc->dma_status = DMA_COMPLETE;
- dma_cookie_complete(&dma_desc->txd);
- if (!dma_desc->cb_count)
- list_add_tail(&dma_desc->cb_node, &tdc->cb_desc);
- dma_desc->cb_count++;
- list_add_tail(&dma_desc->node, &tdc->free_dma_desc);
- }
- list_add_tail(&sgreq->node, &tdc->free_sg_req);
-
- /* Do not start DMA if it is going to be terminate */
- if (to_terminate || list_empty(&tdc->pending_sg_req))
- return;
-
- tdc_start_head_req(tdc);
-}
-
-static void handle_cont_sngl_cycle_dma_done(struct tegra_dma_channel *tdc,
- bool to_terminate)
-{
- struct tegra_dma_sg_req *sgreq;
- struct tegra_dma_desc *dma_desc;
- bool st;
-
- sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq), node);
- dma_desc = sgreq->dma_desc;
- dma_desc->bytes_transferred += sgreq->req_len;
-
- /* Callback need to be call */
- if (!dma_desc->cb_count)
- list_add_tail(&dma_desc->cb_node, &tdc->cb_desc);
- dma_desc->cb_count++;
-
- /* If not last req then put at end of pending list */
- if (!list_is_last(&sgreq->node, &tdc->pending_sg_req)) {
- list_move_tail(&sgreq->node, &tdc->pending_sg_req);
- sgreq->configured = false;
- st = handle_continuous_head_request(tdc, sgreq, to_terminate);
- if (!st)
- dma_desc->dma_status = DMA_ERROR;
- }
-}
-
-static void tegra_dma_tasklet(unsigned long data)
-{
- struct tegra_dma_channel *tdc = (struct tegra_dma_channel *)data;
- dma_async_tx_callback callback = NULL;
- void *callback_param = NULL;
- struct tegra_dma_desc *dma_desc;
- unsigned long flags;
- int cb_count;
-
- spin_lock_irqsave(&tdc->lock, flags);
- while (!list_empty(&tdc->cb_desc)) {
- dma_desc = list_first_entry(&tdc->cb_desc,
- typeof(*dma_desc), cb_node);
- list_del(&dma_desc->cb_node);
- callback = dma_desc->txd.callback;
- callback_param = dma_desc->txd.callback_param;
- cb_count = dma_desc->cb_count;
- dma_desc->cb_count = 0;
- spin_unlock_irqrestore(&tdc->lock, flags);
- while (cb_count-- && callback)
- callback(callback_param);
- spin_lock_irqsave(&tdc->lock, flags);
- }
- spin_unlock_irqrestore(&tdc->lock, flags);
-}
-
-static irqreturn_t tegra_dma_isr(int irq, void *dev_id)
-{
- struct tegra_dma_channel *tdc = dev_id;
- const struct tegra_dma_ops *ops = tdc->tdma->ops;
- unsigned long status;
- unsigned long flags;
-
- spin_lock_irqsave(&tdc->lock, flags);
-
- status = ops->irq_clear(tdc);
- if (status) {
- tdc->isr_handler(tdc, false);
- tasklet_schedule(&tdc->tasklet);
- spin_unlock_irqrestore(&tdc->lock, flags);
- return IRQ_HANDLED;
- }
-
- spin_unlock_irqrestore(&tdc->lock, flags);
- dev_info(tdc2dev(tdc),
- "Interrupt already served status 0x%08lx\n", status);
- return IRQ_NONE;
-}
-
-static dma_cookie_t tegra_dma_tx_submit(struct dma_async_tx_descriptor *txd)
-{
- struct tegra_dma_desc *dma_desc = txd_to_tegra_dma_desc(txd);
- struct tegra_dma_channel *tdc = to_tegra_dma_chan(txd->chan);
- unsigned long flags;
- dma_cookie_t cookie;
-
- spin_lock_irqsave(&tdc->lock, flags);
- dma_desc->dma_status = DMA_IN_PROGRESS;
- cookie = dma_cookie_assign(&dma_desc->txd);
- list_splice_tail_init(&dma_desc->tx_list, &tdc->pending_sg_req);
- spin_unlock_irqrestore(&tdc->lock, flags);
- return cookie;
-}
-
-static void tegra_dma_issue_pending(struct dma_chan *dc)
-{
- struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
- unsigned long flags;
-
- spin_lock_irqsave(&tdc->lock, flags);
- if (list_empty(&tdc->pending_sg_req)) {
- dev_err(tdc2dev(tdc), "No DMA request\n");
- goto end;
- }
- if (!tdc->busy) {
- tdc_start_head_req(tdc);
-
- /* Continuous single mode: Configure next req */
- if (tdc->cyclic) {
- /*
- * Wait for 1 burst time for configure DMA for
- * next transfer.
- */
- udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME);
- tdc_configure_next_head_desc(tdc);
- }
- }
-end:
- spin_unlock_irqrestore(&tdc->lock, flags);
-}
-
-static int tegra_dma_terminate_all(struct dma_chan *dc)
-{
- struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
- const struct tegra_dma_ops *ops = tdc->tdma->ops;
- struct tegra_dma_sg_req *sgreq;
- struct tegra_dma_desc *dma_desc;
- unsigned long flags;
- unsigned long status;
- unsigned long wcount;
- bool was_busy;
-
- spin_lock_irqsave(&tdc->lock, flags);
- if (list_empty(&tdc->pending_sg_req)) {
- spin_unlock_irqrestore(&tdc->lock, flags);
- return 0;
- }
-
- if (!tdc->busy)
- goto skip_dma_stop;
-
- /* Pause DMA before checking the queue status */
- ops->pause(tdc, true);
-
- status = ops->irq_status(tdc);
- if (status) {
- dev_dbg(tdc2dev(tdc), "%s():handling isr\n", __func__);
- tdc->isr_handler(tdc, true);
- }
-
- wcount = ops->get_xfer_count(tdc);
-
- was_busy = tdc->busy;
- ops->stop(tdc);
-
- if (!list_empty(&tdc->pending_sg_req) && was_busy) {
- sgreq = list_first_entry(&tdc->pending_sg_req,
- typeof(*sgreq), node);
- sgreq->dma_desc->bytes_transferred +=
- get_current_xferred_count(sgreq, wcount);
- }
- ops->resume(tdc);
-
-skip_dma_stop:
- tegra_dma_abort_all(tdc);
-
- while (!list_empty(&tdc->cb_desc)) {
- dma_desc = list_first_entry(&tdc->cb_desc,
- typeof(*dma_desc), cb_node);
- list_del(&dma_desc->cb_node);
- dma_desc->cb_count = 0;
- }
- spin_unlock_irqrestore(&tdc->lock, flags);
- return 0;
-}
-
-static enum dma_status tegra_dma_tx_status(struct dma_chan *dc,
- dma_cookie_t cookie, struct dma_tx_state *txstate)
-{
- struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
- struct tegra_dma_desc *dma_desc;
- struct tegra_dma_sg_req *sg_req;
- enum dma_status ret;
- unsigned long flags;
- unsigned int residual;
-
- ret = dma_cookie_status(dc, cookie, txstate);
- if (ret == DMA_COMPLETE)
- return ret;
-
- spin_lock_irqsave(&tdc->lock, flags);
-
- /* Check on wait_ack desc status */
- list_for_each_entry(dma_desc, &tdc->free_dma_desc, node) {
- if (dma_desc->txd.cookie == cookie) {
- residual = dma_desc->bytes_requested -
- (dma_desc->bytes_transferred %
- dma_desc->bytes_requested);
- dma_set_residue(txstate, residual);
- ret = dma_desc->dma_status;
- spin_unlock_irqrestore(&tdc->lock, flags);
- return ret;
- }
- }
-
- /* Check in pending list */
- list_for_each_entry(sg_req, &tdc->pending_sg_req, node) {
- dma_desc = sg_req->dma_desc;
- if (dma_desc->txd.cookie == cookie) {
- residual = dma_desc->bytes_requested -
- (dma_desc->bytes_transferred %
- dma_desc->bytes_requested);
- dma_set_residue(txstate, residual);
- ret = dma_desc->dma_status;
- spin_unlock_irqrestore(&tdc->lock, flags);
- return ret;
- }
- }
-
- dev_dbg(tdc2dev(tdc), "cookie %d does not found\n", cookie);
- spin_unlock_irqrestore(&tdc->lock, flags);
- return ret;
-}
-
static inline int get_bus_width(struct tegra_dma_channel *tdc,
enum dma_slave_buswidth slave_bw)
{
@@ -1063,259 +418,6 @@ static void tegra_dma_set_xfer_params(struct tegra_dma_channel *tdc,
sg_req->req_len = len;
}
-static struct dma_async_tx_descriptor *tegra_dma_prep_slave_sg(
- struct dma_chan *dc, struct scatterlist *sgl, unsigned int sg_len,
- enum dma_transfer_direction direction, unsigned long flags,
- void *context)
-{
- struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
- const struct tegra_dma_ops *ops = tdc->tdma->ops;
- struct tegra_dma_desc *dma_desc;
- unsigned int i;
- struct scatterlist *sg;
- struct list_head req_list;
- struct tegra_dma_sg_req sg_base, *sg_req = NULL;
-
- if (!tdc->config_init) {
- dev_err(tdc2dev(tdc), "dma channel is not configured\n");
- return NULL;
- }
- if (sg_len < 1) {
- dev_err(tdc2dev(tdc), "Invalid segment length %d\n", sg_len);
- return NULL;
- }
-
- if (ops->get_xfer_params_sg(tdc, &sg_base, direction, flags) < 0)
- return NULL;
-
- INIT_LIST_HEAD(&req_list);
-
- dma_desc = tegra_dma_desc_get(tdc);
- if (!dma_desc) {
- dev_err(tdc2dev(tdc), "Dma descriptors not available\n");
- return NULL;
- }
- INIT_LIST_HEAD(&dma_desc->tx_list);
- INIT_LIST_HEAD(&dma_desc->cb_node);
- dma_desc->cb_count = 0;
- dma_desc->bytes_requested = 0;
- dma_desc->bytes_transferred = 0;
- dma_desc->dma_status = DMA_IN_PROGRESS;
-
- /* Make transfer requests */
- for_each_sg(sgl, sg, sg_len, i) {
- u32 len, mem;
-
- mem = sg_dma_address(sg);
- len = sg_dma_len(sg);
-
- if ((len & 3) || (mem & 3) ||
- (len > tdc->tdma->chip_data->max_dma_count)) {
- dev_err(tdc2dev(tdc),
- "Dma length/memory address is not supported\n");
- tegra_dma_desc_put(tdc, dma_desc);
- return NULL;
- }
-
- sg_req = tegra_dma_sg_req_get(tdc);
- if (!sg_req) {
- dev_err(tdc2dev(tdc), "Dma sg-req not available\n");
- tegra_dma_desc_put(tdc, dma_desc);
- return NULL;
- }
-
- dma_desc->bytes_requested += len;
-
- ops->set_xfer_params(tdc, sg_req, &sg_base, direction, mem,
- len);
- sg_req->dma_desc = dma_desc;
-
- list_add_tail(&sg_req->node, &dma_desc->tx_list);
- }
- sg_req->last_sg = true;
- if (flags & DMA_CTRL_ACK)
- dma_desc->txd.flags = DMA_CTRL_ACK;
-
- /*
- * Make sure that mode should not be conflicting with currently
- * configured mode.
- */
- if (!tdc->isr_handler) {
- tdc->isr_handler = handle_once_dma_done;
- tdc->cyclic = false;
- } else {
- if (tdc->cyclic) {
- dev_err(tdc2dev(tdc), "DMA configured in cyclic mode\n");
- tegra_dma_desc_put(tdc, dma_desc);
- return NULL;
- }
- }
-
- return &dma_desc->txd;
-}
-
-static struct dma_async_tx_descriptor *tegra_dma_prep_dma_cyclic(
- struct dma_chan *dc, dma_addr_t buf_addr, size_t buf_len,
- size_t period_len, enum dma_transfer_direction direction,
- unsigned long flags)
-{
- struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
- const struct tegra_dma_ops *ops = tdc->tdma->ops;
- struct tegra_dma_desc *dma_desc = NULL;
- struct tegra_dma_sg_req sg_base, *sg_req = NULL;
- int len;
- size_t remain_len;
- dma_addr_t mem = buf_addr;
-
- if (!buf_len || !period_len) {
- dev_err(tdc2dev(tdc), "Invalid buffer/period len\n");
- return NULL;
- }
-
- if (!tdc->config_init) {
- dev_err(tdc2dev(tdc), "DMA slave is not configured\n");
- return NULL;
- }
-
- /*
- * We allow to take more number of requests till DMA is
- * not started. The driver will loop over all requests.
- * Once DMA is started then new requests can be queued only after
- * terminating the DMA.
- */
- if (tdc->busy) {
- dev_err(tdc2dev(tdc), "Request not allowed when dma running\n");
- return NULL;
- }
-
- /*
- * We only support cycle transfer when buf_len is multiple of
- * period_len.
- */
- if (buf_len % period_len) {
- dev_err(tdc2dev(tdc), "buf_len is not multiple of period_len\n");
- return NULL;
- }
-
- len = period_len;
- if ((len & 3) || (buf_addr & 3) ||
- (len > tdc->tdma->chip_data->max_dma_count)) {
- dev_err(tdc2dev(tdc), "Req len/mem address is not correct\n");
- return NULL;
- }
-
- if (ops->get_xfer_params_cyclic(tdc, &sg_base, direction, flags) < 0)
- return NULL;
-
- dma_desc = tegra_dma_desc_get(tdc);
- if (!dma_desc) {
- dev_err(tdc2dev(tdc), "not enough descriptors available\n");
- return NULL;
- }
-
- INIT_LIST_HEAD(&dma_desc->tx_list);
- INIT_LIST_HEAD(&dma_desc->cb_node);
- dma_desc->cb_count = 0;
-
- dma_desc->bytes_transferred = 0;
- dma_desc->bytes_requested = buf_len;
- remain_len = buf_len;
-
- /* Split transfer equal to period size */
- while (remain_len) {
- sg_req = tegra_dma_sg_req_get(tdc);
- if (!sg_req) {
- dev_err(tdc2dev(tdc), "Dma sg-req not available\n");
- tegra_dma_desc_put(tdc, dma_desc);
- return NULL;
- }
-
- ops->set_xfer_params(tdc, sg_req, &sg_base, direction, mem,
- len);
- sg_req->dma_desc = dma_desc;
-
- list_add_tail(&sg_req->node, &dma_desc->tx_list);
- remain_len -= len;
- mem += len;
- }
- sg_req->last_sg = true;
- if (flags & DMA_CTRL_ACK)
- dma_desc->txd.flags = DMA_CTRL_ACK;
-
- /*
- * Make sure that mode should not be conflicting with currently
- * configured mode.
- */
- if (!tdc->isr_handler) {
- tdc->isr_handler = handle_cont_sngl_cycle_dma_done;
- tdc->cyclic = true;
- } else {
- if (!tdc->cyclic) {
- dev_err(tdc2dev(tdc), "DMA configuration conflict\n");
- tegra_dma_desc_put(tdc, dma_desc);
- return NULL;
- }
- }
-
- return &dma_desc->txd;
-}
-
-static int tegra_dma_alloc_chan_resources(struct dma_chan *dc)
-{
- struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
- struct tegra_dma *tdma = tdc->tdma;
-
- dma_cookie_init(&tdc->dma_chan);
- tdc->config_init = false;
-
- return pm_runtime_get_sync(tdma->dev);
-}
-
-static void tegra_dma_free_chan_resources(struct dma_chan *dc)
-{
- struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
- struct tegra_dma *tdma = tdc->tdma;
-
- struct tegra_dma_desc *dma_desc;
- struct tegra_dma_sg_req *sg_req;
- struct list_head dma_desc_list;
- struct list_head sg_req_list;
- unsigned long flags;
-
- INIT_LIST_HEAD(&dma_desc_list);
- INIT_LIST_HEAD(&sg_req_list);
-
- dev_dbg(tdc2dev(tdc), "Freeing channel %d\n", tdc->id);
-
- if (tdc->busy)
- tegra_dma_terminate_all(dc);
-
- spin_lock_irqsave(&tdc->lock, flags);
- list_splice_init(&tdc->pending_sg_req, &sg_req_list);
- list_splice_init(&tdc->free_sg_req, &sg_req_list);
- list_splice_init(&tdc->free_dma_desc, &dma_desc_list);
- INIT_LIST_HEAD(&tdc->cb_desc);
- tdc->config_init = false;
- tdc->isr_handler = NULL;
- spin_unlock_irqrestore(&tdc->lock, flags);
-
- while (!list_empty(&dma_desc_list)) {
- dma_desc = list_first_entry(&dma_desc_list,
- typeof(*dma_desc), node);
- list_del(&dma_desc->node);
- kfree(dma_desc);
- }
-
- while (!list_empty(&sg_req_list)) {
- sg_req = list_first_entry(&sg_req_list, typeof(*sg_req), node);
- list_del(&sg_req->node);
- kfree(sg_req);
- }
- pm_runtime_put(tdma->dev);
-
- tdc->slave_id = 0;
-}
-
static struct dma_chan *tegra_dma_of_xlate(struct of_phandle_args *dma_spec,
struct of_dma *ofdma)
{
@@ -1335,6 +437,7 @@ static struct dma_chan *tegra_dma_of_xlate(struct of_phandle_args *dma_spec,
/* Tegra20 specific DMA controller information */
static const struct tegra_dma_chip_data tegra20_dma_chip_data = {
+ .burst_time = TEGRA_APBDMA_BURST_COMPLETE_TIME,
.nr_channels = 16,
.channel_reg_size = 0x20,
.max_dma_count = 1024UL * 64,
@@ -1344,6 +447,7 @@ static const struct tegra_dma_chip_data tegra20_dma_chip_data = {
/* Tegra30 specific DMA controller information */
static const struct tegra_dma_chip_data tegra30_dma_chip_data = {
+ .burst_time = TEGRA_APBDMA_BURST_COMPLETE_TIME,
.nr_channels = 32,
.channel_reg_size = 0x20,
.max_dma_count = 1024UL * 64,
@@ -1353,6 +457,7 @@ static const struct tegra_dma_chip_data tegra30_dma_chip_data = {
/* Tegra114 specific DMA controller information */
static const struct tegra_dma_chip_data tegra114_dma_chip_data = {
+ .burst_time = TEGRA_APBDMA_BURST_COMPLETE_TIME,
.nr_channels = 32,
.channel_reg_size = 0x20,
.max_dma_count = 1024UL * 64,
@@ -1362,6 +467,7 @@ static const struct tegra_dma_chip_data tegra114_dma_chip_data = {
/* Tegra148 specific DMA controller information */
static const struct tegra_dma_chip_data tegra148_dma_chip_data = {
+ .burst_time = TEGRA_APBDMA_BURST_COMPLETE_TIME,
.nr_channels = 32,
.channel_reg_size = 0x40,
.max_dma_count = 1024UL * 64,
--
2.1.4
Add device-tree binding documentation for the Tegra210 Audio DMA
controller.
Cc: Rob Herring <[email protected]>
Cc: Pawel Moll <[email protected]>
Cc: Mark Rutland <[email protected]>
Cc: Ian Campbell <[email protected]>
Cc: Kumar Gala <[email protected]>
Signed-off-by: Jon Hunter <[email protected]>
---
.../devicetree/bindings/dma/tegra210-adma.txt | 49 ++++++++++++++++++++++
1 file changed, 49 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/tegra210-adma.txt
diff --git a/Documentation/devicetree/bindings/dma/tegra210-adma.txt b/Documentation/devicetree/bindings/dma/tegra210-adma.txt
new file mode 100644
index 000000000000..38310d7e7e77
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/tegra210-adma.txt
@@ -0,0 +1,49 @@
+* NVIDIA Tegra Audio DMA controller
+
+Required properties:
+- compatible: Should be "nvidia,<chip>-adma"
+- reg: Should contain DMA registers location and length. This should include
+ all of the per-channel registers.
+- interrupt-parent: Phandle to the interrupt parent controller.
+- interrupts: Should contain all of the per-channel DMA interrupts.
+- clocks: Must contain two entries, one for the power-domain clock and one
+ for the module clock.
+ See ../clocks/clock-bindings.txt for details.
+- #dma-cells : Must be <1>. This dictates the length of DMA specifiers in
+ client nodes' dmas properties. The specifier represents the DMA request
+ select value for the peripheral. For more details, consult the Tegra TRM's
+ documentation of the APB DMA channel control register REQ_SEL field.
+
+Examples:
+
+adma: adma@702e2000 {
+ compatible = "nvidia,tegra210-adma";
+ reg = <0x0 0x702e2000 0x0 0x2000>;
+ interrupt-parent = <&tegra_agic>;
+ interrupts = <GIC_SPI INT_ADMA_EOT0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI INT_ADMA_EOT1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI INT_ADMA_EOT2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI INT_ADMA_EOT3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI INT_ADMA_EOT4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI INT_ADMA_EOT5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI INT_ADMA_EOT6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI INT_ADMA_EOT7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI INT_ADMA_EOT8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI INT_ADMA_EOT9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI INT_ADMA_EOT10 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI INT_ADMA_EOT11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI INT_ADMA_EOT12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI INT_ADMA_EOT13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI INT_ADMA_EOT14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI INT_ADMA_EOT15 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI INT_ADMA_EOT16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI INT_ADMA_EOT17 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI INT_ADMA_EOT18 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI INT_ADMA_EOT19 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI INT_ADMA_EOT20 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI INT_ADMA_EOT21 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>,
+ <&tegra_car TEGRA210_CLK_ADMA_APE>;
+ clock-names = "adma", "adma.ape";
+ #dma-cells = <1>;
+};
--
2.1.4
Add support for the Tegra210 Audio DMA controller that is used for
transferring data between system memory and the Audio sub-system.
This driver is based upon the work by Dara Ramesh <[email protected]>.
Signed-off-by: Jon Hunter <[email protected]>
---
drivers/dma/Kconfig | 12 +
drivers/dma/Makefile | 1 +
drivers/dma/tegra-common.c | 3 +-
drivers/dma/tegra-common.h | 42 ++-
drivers/dma/tegra20-apb-dma.c | 37 +--
drivers/dma/tegra210-adma.c | 710 ++++++++++++++++++++++++++++++++++++++++++
6 files changed, 782 insertions(+), 23 deletions(-)
create mode 100644 drivers/dma/tegra210-adma.c
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index dd79b0bf0876..25b474965d66 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -205,6 +205,18 @@ config TEGRA20_APB_DMA
This DMA controller transfers data from memory to peripheral fifo
or vice versa. It does not support memory to memory data transfer.
+config TEGRA210_ADMA
+ bool "NVIDIA Tegra210 ADMA support"
+ depends on ARCH_TEGRA
+ select DMA_ENGINE
+ select TEGRA_DMA_COMMON
+ help
+ Support for the NVIDIA Tegra210 ADMA controller driver. The
+ DMA controller is having multiple DMA channel and it configured
+ for audio. This DMA controller transfers data from memory to
+ peripheral fifo or vice versa. It does not support memory to
+ memory data transfer.
+
config S3C24XX_DMAC
tristate "Samsung S3C24XX DMA support"
depends on ARCH_S3C24XX
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index d9c2bf5ef0bd..9c5b8afc53a1 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -32,6 +32,7 @@ obj-$(CONFIG_SIRF_DMA) += sirf-dma.o
obj-$(CONFIG_TI_EDMA) += edma.o
obj-$(CONFIG_STE_DMA40) += ste_dma40.o ste_dma40_ll.o
obj-$(CONFIG_TEGRA20_APB_DMA) += tegra20-apb-dma.o
+obj-$(CONFIG_TEGRA210_ADMA) += tegra210-adma.o
obj-$(CONFIG_TEGRA_DMA_COMMON) += tegra-common.o
obj-$(CONFIG_S3C24XX_DMAC) += s3c24xx-dma.o
obj-$(CONFIG_PL330_DMA) += pl330.o
diff --git a/drivers/dma/tegra-common.c b/drivers/dma/tegra-common.c
index fff0a143f5bb..b3f7e3322c15 100644
--- a/drivers/dma/tegra-common.c
+++ b/drivers/dma/tegra-common.c
@@ -620,7 +620,8 @@ struct dma_async_tx_descriptor *tegra_dma_prep_dma_cyclic(
return NULL;
}
- if (ops->get_xfer_params_cyclic(tdc, &sg_base, direction, flags) < 0)
+ if (ops->get_xfer_params_cyclic(tdc, &sg_base, buf_len, period_len,
+ direction, flags) < 0)
return NULL;
dma_desc = tegra_dma_desc_get(tdc);
diff --git a/drivers/dma/tegra-common.h b/drivers/dma/tegra-common.h
index e0d4d2b13cb8..c1a369e7efa6 100644
--- a/drivers/dma/tegra-common.h
+++ b/drivers/dma/tegra-common.h
@@ -34,7 +34,7 @@ struct tegra_dma_chip_data {
/*
* DMA channel registers
*/
-struct tegra_dma_channel_regs {
+struct tegra_apb_chan_regs {
unsigned long csr;
unsigned long ahb_ptr;
unsigned long apb_ptr;
@@ -44,6 +44,18 @@ struct tegra_dma_channel_regs {
};
/*
+ * ADMA channel registers
+ */
+struct tegra_adma_chan_regs {
+ unsigned long ctrl;
+ unsigned long config;
+ unsigned long src_ptr;
+ unsigned long tgt_ptr;
+ unsigned long ahub_fifo_ctrl;
+ unsigned long tc;
+};
+
+/*
* tegra_dma_sg_req: Dma request details to configure hardware. This
* contains the details for one transfer to configure DMA hw.
* The client's request for data transfer can be broken into multiple
@@ -52,7 +64,10 @@ struct tegra_dma_channel_regs {
* DMA descriptor which manages the transfer details.
*/
struct tegra_dma_sg_req {
- struct tegra_dma_channel_regs ch_regs;
+ union {
+ struct tegra_apb_chan_regs apb_ch_regs;
+ struct tegra_adma_chan_regs adma_ch_regs;
+ };
int req_len;
bool configured;
bool last_sg;
@@ -109,7 +124,10 @@ struct tegra_dma_channel {
/* Channel-slave specific configuration */
unsigned int slave_id;
struct dma_slave_config dma_sconfig;
- struct tegra_dma_channel_regs channel_reg;
+ union {
+ struct tegra_apb_chan_regs apb_ch_regs;
+ struct tegra_adma_chan_regs adma_ch_regs;
+ };
};
/*
@@ -119,6 +137,7 @@ struct tegra_dma_ops {
u32 (*get_xfer_count)(struct tegra_dma_channel *tdc);
int (*get_xfer_params_cyclic)(struct tegra_dma_channel *tdc,
struct tegra_dma_sg_req *sg_req,
+ size_t buf_len, size_t period_len,
enum dma_transfer_direction direction,
unsigned int flags);
int (*get_xfer_params_sg)(struct tegra_dma_channel *tdc,
@@ -149,6 +168,7 @@ struct tegra_dma {
struct dma_device dma_dev;
struct device *dev;
struct clk *dma_clk;
+ struct clk *domain_clk;
struct reset_control *rst;
spinlock_t global_lock;
void __iomem *base_addr;
@@ -163,7 +183,10 @@ struct tegra_dma {
u32 global_pause_count;
/* Some register need to be cache before suspend */
- u32 reg_gen;
+ union {
+ u32 reg_gen;
+ u32 reg_global;
+ };
/* Last member of the structure */
struct tegra_dma_channel channels[0];
@@ -190,6 +213,17 @@ static inline u32 tdc_read(struct tegra_dma_channel *tdc, u32 reg)
return readl(tdc->chan_addr + reg);
}
+static inline void tdc_set_field(struct tegra_dma_channel *tdc, u32 reg,
+ u32 shift, u32 mask, u32 val)
+{
+ u32 t;
+
+ t = tdc_read(tdc, reg);
+ t &= ~(mask << shift);
+ t |= (val & mask) << shift;
+ tdc_write(tdc, reg, t);
+}
+
static inline struct tegra_dma_channel *to_tegra_dma_chan(struct dma_chan *dc)
{
return container_of(dc, struct tegra_dma_channel, dma_chan);
diff --git a/drivers/dma/tegra20-apb-dma.c b/drivers/dma/tegra20-apb-dma.c
index 0895732aaa28..b800f10860eb 100644
--- a/drivers/dma/tegra20-apb-dma.c
+++ b/drivers/dma/tegra20-apb-dma.c
@@ -188,13 +188,13 @@ static u32 tegra_dma_irq_clear(struct tegra_dma_channel *tdc)
static void tegra_dma_program(struct tegra_dma_channel *tdc,
struct tegra_dma_sg_req *nsg_req)
{
- tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, nsg_req->ch_regs.apb_ptr);
- tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, nsg_req->ch_regs.ahb_ptr);
+ tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, nsg_req->apb_ch_regs.apb_ptr);
+ tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, nsg_req->apb_ch_regs.ahb_ptr);
if (tdc->tdma->chip_data->support_separate_wcount_reg)
tdc_write(tdc, TEGRA_APBDMA_CHAN_WCOUNT,
- nsg_req->ch_regs.wcount);
+ nsg_req->apb_ch_regs.wcount);
tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,
- nsg_req->ch_regs.csr | TEGRA_APBDMA_CSR_ENB);
+ nsg_req->apb_ch_regs.csr | TEGRA_APBDMA_CSR_ENB);
nsg_req->configured = true;
}
@@ -246,7 +246,7 @@ static void tegra_dma_stop(struct tegra_dma_channel *tdc)
static void tegra_dma_start(struct tegra_dma_channel *tdc,
struct tegra_dma_sg_req *sg_req)
{
- struct tegra_dma_channel_regs *ch_regs = &sg_req->ch_regs;
+ struct tegra_apb_chan_regs *ch_regs = &sg_req->apb_ch_regs;
tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, ch_regs->csr);
tdc_write(tdc, TEGRA_APBDMA_CHAN_APBSEQ, ch_regs->apb_seq);
@@ -327,7 +327,7 @@ static inline int get_burst_size(struct tegra_dma_channel *tdc,
}
static int tegra_dma_get_xfer_params(struct tegra_dma_channel *tdc,
- struct tegra_dma_channel_regs *ch_regs,
+ struct tegra_apb_chan_regs *ch_regs,
enum dma_transfer_direction direction,
unsigned int flags)
{
@@ -367,7 +367,7 @@ static int tegra_dma_get_xfer_params_sg(struct tegra_dma_channel *tdc,
enum dma_transfer_direction direction,
unsigned int flags)
{
- struct tegra_dma_channel_regs *ch_regs = &sg_req->ch_regs;
+ struct tegra_apb_chan_regs *ch_regs = &sg_req->apb_ch_regs;
int ret;
ret = tegra_dma_get_xfer_params(tdc, ch_regs, direction, flags);
@@ -381,16 +381,17 @@ static int tegra_dma_get_xfer_params_sg(struct tegra_dma_channel *tdc,
static int tegra_dma_get_xfer_params_cyclic(struct tegra_dma_channel *tdc,
struct tegra_dma_sg_req *sg_req,
+ size_t buf_len, size_t period_len,
enum dma_transfer_direction direction,
unsigned int flags)
{
- struct tegra_dma_channel_regs *ch_regs = &sg_req->ch_regs;
+ struct tegra_apb_chan_regs *ch_regs = &sg_req->apb_ch_regs;
return tegra_dma_get_xfer_params(tdc, ch_regs, direction, flags);
}
static void tegra_dma_prep_wcount(struct tegra_dma_channel *tdc,
- struct tegra_dma_channel_regs *ch_regs, u32 len)
+ struct tegra_apb_chan_regs *ch_regs, u32 len)
{
u32 len_field = (len - 4) & 0xFFFC;
@@ -406,13 +407,13 @@ static void tegra_dma_set_xfer_params(struct tegra_dma_channel *tdc,
enum dma_transfer_direction direction,
u32 mem, u32 len)
{
- sg_req->ch_regs.ahb_seq |= get_burst_size(tdc, direction, len);
- sg_req->ch_regs.apb_ptr = sg_base->ch_regs.apb_ptr;
- sg_req->ch_regs.ahb_ptr = mem;
- sg_req->ch_regs.csr = sg_base->ch_regs.csr;
- tegra_dma_prep_wcount(tdc, &sg_req->ch_regs, len);
- sg_req->ch_regs.apb_seq = sg_base->ch_regs.apb_seq;
- sg_req->ch_regs.ahb_seq = sg_base->ch_regs.ahb_seq;
+ sg_req->apb_ch_regs.ahb_seq |= get_burst_size(tdc, direction, len);
+ sg_req->apb_ch_regs.apb_ptr = sg_base->apb_ch_regs.apb_ptr;
+ sg_req->apb_ch_regs.ahb_ptr = mem;
+ sg_req->apb_ch_regs.csr = sg_base->apb_ch_regs.csr;
+ tegra_dma_prep_wcount(tdc, &sg_req->apb_ch_regs, len);
+ sg_req->apb_ch_regs.apb_seq = sg_base->apb_ch_regs.apb_seq;
+ sg_req->apb_ch_regs.ahb_seq = sg_base->apb_ch_regs.ahb_seq;
sg_req->configured = false;
sg_req->last_sg = false;
sg_req->req_len = len;
@@ -742,7 +743,7 @@ static int tegra_dma_pm_suspend(struct device *dev)
tdma->reg_gen = tdma_read(tdma, TEGRA_APBDMA_GENERAL);
for (i = 0; i < tdma->chip_data->nr_channels; i++) {
struct tegra_dma_channel *tdc = &tdma->channels[i];
- struct tegra_dma_channel_regs *ch_reg = &tdc->channel_reg;
+ struct tegra_apb_chan_regs *ch_reg = &tdc->apb_ch_regs;
ch_reg->csr = tdc_read(tdc, TEGRA_APBDMA_CHAN_CSR);
ch_reg->ahb_ptr = tdc_read(tdc, TEGRA_APBDMA_CHAN_AHBPTR);
@@ -773,7 +774,7 @@ static int tegra_dma_pm_resume(struct device *dev)
for (i = 0; i < tdma->chip_data->nr_channels; i++) {
struct tegra_dma_channel *tdc = &tdma->channels[i];
- struct tegra_dma_channel_regs *ch_reg = &tdc->channel_reg;
+ struct tegra_apb_chan_regs *ch_reg = &tdc->apb_ch_regs;
tdc_write(tdc, TEGRA_APBDMA_CHAN_APBSEQ, ch_reg->apb_seq);
tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, ch_reg->apb_ptr);
diff --git a/drivers/dma/tegra210-adma.c b/drivers/dma/tegra210-adma.c
new file mode 100644
index 000000000000..23e4ee15f147
--- /dev/null
+++ b/drivers/dma/tegra210-adma.c
@@ -0,0 +1,710 @@
+/*
+ * ADMA driver for Nvidia's Tegra210 ADMA controller.
+ *
+ * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/bitops.h>
+#include <linux/clk.h>
+#include <linux/dmaengine.h>
+#include <linux/dma-mapping.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_dma.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/pm.h>
+#include <linux/pm_runtime.h>
+#include <linux/slab.h>
+#include <linux/clk/tegra.h>
+
+#include "dmaengine.h"
+
+#include "tegra-common.h"
+
+/* Register offsets from ADMA*_BASE */
+#define ADMA_CH_CMD 0x00
+#define ADMA_CH_STATUS 0x0c
+#define ADMA_CH_STATUS_TRANSFER_PAUSED BIT(1)
+#define ADMA_CH_STATUS_TRANSFER_ENABLED BIT(0)
+
+#define ADMA_CH_INT_STATUS 0x10
+#define ADMA_CH_INT_TD_STATUS BIT(0)
+
+#define ADMA_CH_INT_CLEAR 0x1c
+#define ADMA_CH_CTRL 0x24
+#define ADMA_CH_CTRL_TX_REQUEST_SELECT_SHIFT 28
+#define ADMA_CH_CTRL_TX_REQUEST_SELECT_MASK \
+ (0xf << ADMA_CH_CTRL_TX_REQUEST_SELECT_SHIFT)
+#define ADMA_CH_CTRL_RX_REQUEST_SELECT_SHIFT 24
+#define ADMA_CH_CTRL_RX_REQUEST_SELECT_MASK \
+ (0xf << ADMA_CH_CTRL_RX_REQUEST_SELECT_SHIFT)
+#define ADMA_CH_CTRL_TRANSFER_DIRECTION_SHIFT 12
+#define ADMA_CH_CTRL_TRANSFER_DIRECTION_MASK \
+ (0xf << ADMA_CH_CTRL_TRANSFER_DIRECTION_SHIFT)
+#define ADMA_CH_CTRL_TRANSFER_MODE_SHIFT 8
+#define ADMA_CH_CTRL_TRANSFER_MODE_MASK \
+ (0x7 << ADMA_CH_CTRL_TRANSFER_MODE_SHIFT)
+#define ADMA_CH_CTRL_TRANSFER_PAUSE_SHIFT 0
+#define ADMA_CH_CTRL_TRANSFER_PAUSE_MASK \
+ (0x1 << ADMA_CH_CTRL_TRANSFER_PAUSE_SHIFT)
+#define ADMA_CH_CTRL_TRANSFER_PAUSE BIT(0)
+
+#define ADMA_CH_CONFIG 0x28
+#define ADMA_CH_CONFIG_SOURCE_MEMORY_BUFFER_SHIFT 28
+#define ADMA_CH_CONFIG_SOURCE_MEMORY_BUFFER_MASK \
+ (0x7 << ADMA_CH_CONFIG_SOURCE_MEMORY_BUFFER_SHIFT)
+#define ADMA_CH_CONFIG_TARGET_MEMORY_BUFFER_SHIFT 24
+#define ADMA_CH_CONFIG_TARGET_MEMORY_BUFFER_MASK \
+ (0x7 << ADMA_CH_CONFIG_TARGET_MEMORY_BUFFER_SHIFT)
+#define ADMA_CH_CONFIG_BURST_SIZE_SHIFT 20
+#define ADMA_CH_CONFIG_BURST_SIZE_MASK \
+ (0x7 << ADMA_CH_CONFIG_BURST_SIZE_SHIFT)
+#define ADMA_CH_CONFIG_MAX_MEM_BUFFERS 8
+
+#define ADMA_CH_AHUB_FIFO_CTRL 0x2c
+#define ADMA_CH_AHUB_FIFO_CTRL_FETCHING_POLICY_SHIFT 31
+#define ADMA_CH_AHUB_FIFO_CTRL_TX_FIFO_SIZE_SHIFT 8
+#define ADMA_CH_AHUB_FIFO_CTRL_TX_FIFO_SIZE_MASK \
+ (0xf << ADMA_CH_AHUB_FIFO_CTRL_TX_FIFO_SIZE_SHIFT)
+#define ADMA_CH_AHUB_FIFO_CTRL_RX_FIFO_SIZE_SHIFT 0
+#define ADMA_CH_AHUB_FIFO_CTRL_RX_FIFO_SIZE_MASK \
+ (0xf << ADMA_CH_AHUB_FIFO_CTRL_RX_FIFO_SIZE_SHIFT)
+
+#define ADMA_CH_TC_STATUS 0x30
+#define ADMA_CH_TC_STATUS_COUNT_MASK 0x3ffffffc
+
+#define ADMA_CH_LOWER_SOURCE_ADDR 0x34
+#define ADMA_CH_LOWER_TARGET_ADDR 0x3c
+#define ADMA_CH_TC 0x44
+
+#define ADMA_GLOBAL_CMD 0xc00
+#define ADMA_GLOBAL_SOFT_RESET 0xc04
+#define ADMA_GLOBAL_INT_CLEAR 0xc20
+#define ADMA_GLOBAL_CTRL 0xc24
+
+#define ADMA_BURSTSIZE_16 5
+#define ADMA_FIFO_DEFAULT_SIZE 3
+#define ADMA_MODE_ONESHOT 1
+#define ADMA_MODE_CONTINUOUS 2
+#define AHUB_TO_MEMORY 2
+#define MEMORY_TO_AHUB 4
+
+/*
+ * If any burst is in flight and ADMA paused then this is the time to complete
+ * on-flight burst and update ADMA status register.
+ */
+#define TEGRA_ADMA_BURST_COMPLETE_TIME 20
+
+static int tegra_adma_runtime_suspend(struct device *dev);
+static int tegra_adma_runtime_resume(struct device *dev);
+
+static int tegra_adma_global_soft_reset(struct tegra_dma *tdma)
+{
+ u32 status;
+
+ /* Clear any interrupts */
+ tdma_write(tdma, ADMA_GLOBAL_INT_CLEAR, 0x1);
+
+ /* Assert soft reset */
+ tdma_write(tdma, ADMA_GLOBAL_SOFT_RESET, 0x1);
+
+ /* Wait for reset to clear */
+ return readx_poll_timeout(readl,
+ tdma->base_addr + ADMA_GLOBAL_SOFT_RESET,
+ status, status == 0,
+ TEGRA_ADMA_BURST_COMPLETE_TIME, 10000);
+}
+
+static u32 tegra_adma_get_xfer_count(struct tegra_dma_channel *tdc)
+{
+ u32 wcount = tdc_read(tdc, ADMA_CH_TC_STATUS);
+
+ return wcount & ADMA_CH_TC_STATUS_COUNT_MASK;
+}
+
+static u32 tegra_adma_irq_status(struct tegra_dma_channel *tdc)
+{
+ u32 status = tdc_read(tdc, ADMA_CH_INT_STATUS);
+
+ return status & ADMA_CH_INT_TD_STATUS;
+}
+
+static u32 tegra_adma_irq_clear(struct tegra_dma_channel *tdc)
+{
+ u32 status = tegra_adma_irq_status(tdc);
+
+ if (status) {
+ dev_dbg(tdc2dev(tdc), "%s():clearing interrupt\n", __func__);
+ tdc_write(tdc, ADMA_CH_INT_CLEAR, status);
+ }
+
+ return status;
+}
+
+static void tegra_adma_pause(struct tegra_dma_channel *tdc,
+ bool wait_for_burst_complete)
+{
+ u32 status;
+
+ tdc_set_field(tdc, ADMA_CH_CTRL, ADMA_CH_CTRL_TRANSFER_PAUSE_SHIFT,
+ ADMA_CH_CTRL_TRANSFER_PAUSE_MASK, 1);
+
+ if (readx_poll_timeout(readl, tdc->chan_addr + ADMA_CH_STATUS, status,
+ status & ADMA_CH_STATUS_TRANSFER_PAUSED,
+ TEGRA_ADMA_BURST_COMPLETE_TIME, 10000))
+ dev_err(tdc2dev(tdc), "%s(): unable to pause DMA\n", __func__);
+}
+
+static void tegra_adma_program(struct tegra_dma_channel *tdc,
+ struct tegra_dma_sg_req *nsg_req)
+{
+ tdc_write(tdc, ADMA_CH_LOWER_SOURCE_ADDR,
+ nsg_req->adma_ch_regs.src_ptr);
+ tdc_write(tdc, ADMA_CH_LOWER_TARGET_ADDR,
+ nsg_req->adma_ch_regs.tgt_ptr);
+ tdc_write(tdc, ADMA_CH_TC, nsg_req->adma_ch_regs.tc);
+ tdc_write(tdc, ADMA_CH_CTRL, nsg_req->adma_ch_regs.ctrl);
+ tdc_write(tdc, ADMA_CH_AHUB_FIFO_CTRL,
+ nsg_req->adma_ch_regs.ahub_fifo_ctrl);
+ tdc_write(tdc, ADMA_CH_CONFIG, nsg_req->adma_ch_regs.config);
+ tdc_write(tdc, ADMA_CH_CMD, 1);
+ nsg_req->configured = true;
+}
+
+static void tegra_adma_resume(struct tegra_dma_channel *tdc)
+{
+ tdc_set_field(tdc, ADMA_CH_CTRL, ADMA_CH_CTRL_TRANSFER_PAUSE_SHIFT,
+ ADMA_CH_CTRL_TRANSFER_PAUSE_MASK, 0);
+}
+
+static void tegra_adma_stop(struct tegra_dma_channel *tdc)
+{
+ u32 status;
+
+ /* TODO: Do we need to disable interrupts here? */
+
+ /* Disable ADMA */
+ tdc_write(tdc, ADMA_CH_CMD, 0);
+
+ /* Clear interrupt status */
+ tegra_adma_irq_clear(tdc);
+
+ if (readx_poll_timeout(readl, tdc->chan_addr + ADMA_CH_STATUS, status,
+ !(status & ADMA_CH_STATUS_TRANSFER_ENABLED),
+ TEGRA_ADMA_BURST_COMPLETE_TIME, 10000))
+ dev_err(tdc2dev(tdc), "%s(): unable to stop DMA\n", __func__);
+ else
+ tdc->busy = false;
+}
+
+static void tegra_adma_start(struct tegra_dma_channel *tdc,
+ struct tegra_dma_sg_req *sg_req)
+{
+ struct tegra_adma_chan_regs *ch_regs = &sg_req->adma_ch_regs;
+
+ /* Update transfer done count for position calculation */
+ tdc->adma_ch_regs.tc = ch_regs->tc;
+ tdc_write(tdc, ADMA_CH_TC, ch_regs->tc);
+ tdc_write(tdc, ADMA_CH_CTRL, ch_regs->ctrl);
+ tdc_write(tdc, ADMA_CH_LOWER_SOURCE_ADDR, ch_regs->src_ptr);
+ tdc_write(tdc, ADMA_CH_LOWER_TARGET_ADDR, ch_regs->tgt_ptr);
+ tdc_write(tdc, ADMA_CH_AHUB_FIFO_CTRL, ch_regs->ahub_fifo_ctrl);
+ tdc_write(tdc, ADMA_CH_CONFIG, ch_regs->config);
+ /* Start ADMA */
+ tdc_write(tdc, ADMA_CH_CMD, 1);
+}
+
+static int tegra_adma_get_xfer_params(struct tegra_dma_channel *tdc,
+ struct tegra_adma_chan_regs *ch_regs,
+ enum dma_transfer_direction direction)
+{
+ u32 burst_size, ctrl, ctrl_mask, slave_id, fifo_mask, fifo_shift;
+
+ ch_regs->ahub_fifo_ctrl = tdc_read(tdc, ADMA_CH_AHUB_FIFO_CTRL);
+ ch_regs->config = tdc_read(tdc, ADMA_CH_CONFIG);
+ ch_regs->ctrl = tdc_read(tdc, ADMA_CH_CTRL);
+ slave_id = tdc->dma_sconfig.slave_id;
+
+ switch (direction) {
+ case DMA_MEM_TO_DEV:
+ burst_size = fls(tdc->dma_sconfig.dst_maxburst);
+ ctrl_mask = ADMA_CH_CTRL_TX_REQUEST_SELECT_MASK;
+ ctrl = MEMORY_TO_AHUB << ADMA_CH_CTRL_TRANSFER_DIRECTION_SHIFT;
+ ctrl |= slave_id << ADMA_CH_CTRL_TX_REQUEST_SELECT_SHIFT;
+ fifo_mask = ADMA_CH_AHUB_FIFO_CTRL_TX_FIFO_SIZE_MASK;
+ fifo_shift = ADMA_CH_AHUB_FIFO_CTRL_TX_FIFO_SIZE_SHIFT;
+ break;
+ case DMA_DEV_TO_MEM:
+ burst_size = fls(tdc->dma_sconfig.src_maxburst);
+ ctrl_mask = ADMA_CH_CTRL_RX_REQUEST_SELECT_MASK;
+ ctrl = AHUB_TO_MEMORY << ADMA_CH_CTRL_TRANSFER_DIRECTION_SHIFT;
+ ctrl |= slave_id << ADMA_CH_CTRL_RX_REQUEST_SELECT_SHIFT;
+ fifo_mask = ADMA_CH_AHUB_FIFO_CTRL_RX_FIFO_SIZE_MASK;
+ fifo_shift = ADMA_CH_AHUB_FIFO_CTRL_RX_FIFO_SIZE_SHIFT;
+ break;
+ default:
+ dev_err(tdc2dev(tdc), "Dma direction is not supported\n");
+ return -EINVAL;
+ }
+
+ if (!burst_size || burst_size > ADMA_BURSTSIZE_16)
+ burst_size = ADMA_BURSTSIZE_16;
+
+ ch_regs->ahub_fifo_ctrl &= ~fifo_mask;
+ ch_regs->ahub_fifo_ctrl |= ADMA_FIFO_DEFAULT_SIZE << fifo_shift;
+ ch_regs->config &= ~ADMA_CH_CONFIG_BURST_SIZE_MASK;
+ ch_regs->config |= burst_size << ADMA_CH_CONFIG_BURST_SIZE_SHIFT;
+ ch_regs->ctrl &= ~(ctrl_mask | ADMA_CH_CTRL_TRANSFER_DIRECTION_MASK);
+ ch_regs->ctrl |= ctrl;
+
+ return -EINVAL;
+}
+
+static int tegra_adma_get_xfer_params_sg(struct tegra_dma_channel *tdc,
+ struct tegra_dma_sg_req *sg_base,
+ enum dma_transfer_direction direction,
+ unsigned int flags)
+{
+ struct tegra_adma_chan_regs *ch_regs = &sg_base->adma_ch_regs;
+ int ret;
+
+ ret = tegra_adma_get_xfer_params(tdc, ch_regs, direction);
+ if (ret < 0)
+ return ret;
+
+ ch_regs->ctrl &= ~ADMA_CH_CTRL_TRANSFER_MODE_MASK;
+ ch_regs->ctrl |= ADMA_MODE_ONESHOT << ADMA_CH_CTRL_TRANSFER_MODE_SHIFT;
+
+ return 0;
+}
+
+static int tegra_adma_get_xfer_params_cyclic(struct tegra_dma_channel *tdc,
+ struct tegra_dma_sg_req *sg_base,
+ size_t buf_len, size_t period_len,
+ enum dma_transfer_direction direction,
+ unsigned int flags)
+{
+ struct tegra_adma_chan_regs *ch_regs = &sg_base->adma_ch_regs;
+ unsigned int num_bufs, mask, shift;
+ int ret;
+
+ ret = tegra_adma_get_xfer_params(tdc, ch_regs, direction);
+ if (ret < 0)
+ return ret;
+
+ ch_regs->ctrl &= ~ADMA_CH_CTRL_TRANSFER_MODE_MASK;
+ ch_regs->ctrl |= ADMA_MODE_CONTINUOUS <<
+ ADMA_CH_CTRL_TRANSFER_MODE_SHIFT;
+
+ num_bufs = buf_len / period_len;
+
+ if (num_bufs <= ADMA_CH_CONFIG_MAX_MEM_BUFFERS) {
+ if (direction == DMA_MEM_TO_DEV) {
+ mask = ADMA_CH_CONFIG_SOURCE_MEMORY_BUFFER_MASK;
+ shift = ADMA_CH_CONFIG_SOURCE_MEMORY_BUFFER_SHIFT;
+ } else {
+ mask = ADMA_CH_CONFIG_TARGET_MEMORY_BUFFER_MASK;
+ shift = ADMA_CH_CONFIG_TARGET_MEMORY_BUFFER_SHIFT;
+ }
+ ch_regs->config &= ~mask;
+ ch_regs->config |= (num_bufs - 1) << shift;
+ }
+
+ return 0;
+}
+
+static void tegra_adma_set_xfer_params(struct tegra_dma_channel *tdc,
+ struct tegra_dma_sg_req *sg_req,
+ struct tegra_dma_sg_req *sg_base,
+ enum dma_transfer_direction direction,
+ u32 mem, u32 len)
+{
+ if (direction == DMA_MEM_TO_DEV)
+ sg_req->adma_ch_regs.src_ptr = mem;
+ else
+ sg_req->adma_ch_regs.tgt_ptr = mem;
+
+ sg_req->adma_ch_regs.tc = len;
+ sg_req->adma_ch_regs.ctrl = sg_base->adma_ch_regs.ctrl;
+ sg_req->adma_ch_regs.ahub_fifo_ctrl =
+ sg_base->adma_ch_regs.ahub_fifo_ctrl;
+ sg_req->adma_ch_regs.config = sg_base->adma_ch_regs.config;
+ sg_req->configured = false;
+ sg_req->last_sg = false;
+ sg_req->req_len = len;
+}
+
+static struct dma_chan *tegra_dma_of_xlate(struct of_phandle_args *dma_spec,
+ struct of_dma *ofdma)
+{
+ struct tegra_dma *tdma = ofdma->of_dma_data;
+ struct dma_chan *chan;
+
+ chan = dma_get_any_slave_channel(&tdma->dma_dev);
+ if (!chan)
+ return NULL;
+
+ return chan;
+}
+
+static const struct tegra_dma_chip_data tegra210_adma_chip_data = {
+ .burst_time = TEGRA_ADMA_BURST_COMPLETE_TIME,
+ .channel_reg_size = 0x80,
+ .max_dma_count = 1024UL * 64,
+ .nr_channels = 10,
+};
+
+static const struct of_device_id tegra_adma_of_match[] = {
+ {
+ .compatible = "nvidia,tegra210-adma",
+ .data = &tegra210_adma_chip_data,
+ }, {
+ },
+};
+MODULE_DEVICE_TABLE(of, tegra_adma_of_match);
+
+static struct platform_device_id tegra_adma_devtype[] = {
+ {
+ .name = "tegra210-adma",
+ .driver_data = (unsigned long)&tegra210_adma_chip_data,
+ },
+};
+
+static const struct tegra_dma_ops tegra_adma_ops = {
+ .get_xfer_count = tegra_adma_get_xfer_count,
+ .get_xfer_params_sg = tegra_adma_get_xfer_params_sg,
+ .get_xfer_params_cyclic = tegra_adma_get_xfer_params_cyclic,
+ .irq_clear = tegra_adma_irq_clear,
+ .irq_status = tegra_adma_irq_status,
+ .pause = tegra_adma_pause,
+ .program = tegra_adma_program,
+ .resume = tegra_adma_resume,
+ .set_xfer_params = tegra_adma_set_xfer_params,
+ .start = tegra_adma_start,
+ .stop = tegra_adma_stop,
+};
+
+static struct device *dma_device;
+
+static int tegra_adma_probe(struct platform_device *pdev)
+{
+ struct resource *res;
+ struct tegra_dma *tdma;
+ int ret, i;
+
+ const struct tegra_dma_chip_data *cdata = NULL;
+ const struct of_device_id *match;
+
+ if (!pdev->dev.of_node) {
+ dev_err(&pdev->dev, "No device tree node for ADMA driver");
+ return -ENODEV;
+ }
+
+ match = of_match_device(of_match_ptr(tegra_adma_of_match),
+ &pdev->dev);
+ if (!match) {
+ dev_err(&pdev->dev, "Error: No device match found\n");
+ return -ENODEV;
+ }
+ cdata = match->data;
+
+ tdma = devm_kzalloc(&pdev->dev, sizeof(*tdma) + cdata->nr_channels *
+ sizeof(struct tegra_dma_channel), GFP_KERNEL);
+ if (!tdma)
+ return -ENOMEM;
+
+ tdma->dev = &pdev->dev;
+ tdma->chip_data = cdata;
+ platform_set_drvdata(pdev, tdma);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ dev_err(&pdev->dev, "No mem resource for ADMA\n");
+ return -EINVAL;
+ }
+
+ tdma->base_addr = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(tdma->base_addr))
+ return PTR_ERR(tdma->base_addr);
+
+ tdma->dma_clk = devm_clk_get(&pdev->dev, "adma");
+ if (IS_ERR(tdma->dma_clk)) {
+ dev_err(&pdev->dev, "Error: Missing controller clock\n");
+ return PTR_ERR(tdma->dma_clk);
+ }
+
+ tdma->domain_clk = devm_clk_get(&pdev->dev, "adma.ape");
+ if (IS_ERR(tdma->domain_clk)) {
+ dev_err(&pdev->dev, "Error: Missing APE clock\n");
+ return PTR_ERR(tdma->domain_clk);
+ }
+
+ spin_lock_init(&tdma->global_lock);
+
+ dma_device = &pdev->dev;
+
+ pm_runtime_enable(&pdev->dev);
+ if (!pm_runtime_enabled(&pdev->dev))
+ ret = tegra_adma_runtime_resume(&pdev->dev);
+ else
+ ret = pm_runtime_get_sync(&pdev->dev);
+
+ if (ret)
+ goto err_pm_disable;
+
+ /* Reset ADMA controller */
+ ret = tegra_adma_global_soft_reset(tdma);
+ if (ret)
+ return ret;
+
+ INIT_LIST_HEAD(&tdma->dma_dev.channels);
+ for (i = 0; i < cdata->nr_channels; i++) {
+ struct tegra_dma_channel *tdc = &tdma->channels[i];
+
+ tdc->chan_addr = tdma->base_addr + cdata->channel_reg_size * i;
+
+ tdc->irq = platform_get_irq(pdev, i);
+ if (tdc->irq < 0) {
+ ret = -EPROBE_DEFER;
+ dev_err(&pdev->dev, "No irq resource for chan %d\n", i);
+ goto err_irq;
+ }
+
+ snprintf(tdc->name, sizeof(tdc->name), "adma.%d", i);
+ ret = devm_request_irq(&pdev->dev, tdc->irq,
+ tegra_dma_isr, 0, tdc->name, tdc);
+ if (ret) {
+ dev_err(&pdev->dev,
+ "request_irq failed with err %d channel %d\n",
+ ret, i);
+ goto err_irq;
+ }
+
+ tdc->dma_chan.device = &tdma->dma_dev;
+ dma_cookie_init(&tdc->dma_chan);
+ list_add_tail(&tdc->dma_chan.device_node,
+ &tdma->dma_dev.channels);
+ tdc->tdma = tdma;
+ tdc->id = i;
+
+ tasklet_init(&tdc->tasklet, tegra_dma_tasklet,
+ (unsigned long)tdc);
+ spin_lock_init(&tdc->lock);
+
+ INIT_LIST_HEAD(&tdc->pending_sg_req);
+ INIT_LIST_HEAD(&tdc->free_sg_req);
+ INIT_LIST_HEAD(&tdc->free_dma_desc);
+ INIT_LIST_HEAD(&tdc->cb_desc);
+ }
+
+ dma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask);
+ dma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask);
+ dma_cap_set(DMA_CYCLIC, tdma->dma_dev.cap_mask);
+
+ tdma->dma_dev.dev = &pdev->dev;
+ tdma->dma_dev.device_alloc_chan_resources =
+ tegra_dma_alloc_chan_resources;
+ tdma->dma_dev.device_free_chan_resources =
+ tegra_dma_free_chan_resources;
+ tdma->dma_dev.device_prep_slave_sg = tegra_dma_prep_slave_sg;
+ tdma->dma_dev.device_prep_dma_cyclic = tegra_dma_prep_dma_cyclic;
+ tdma->dma_dev.device_tx_status = tegra_dma_tx_status;
+ tdma->dma_dev.device_issue_pending = tegra_dma_issue_pending;
+
+ tdma->ops = &tegra_adma_ops;
+
+ /* Enable global ADMA registers */
+ tdma_write(tdma, ADMA_GLOBAL_CMD, 1);
+
+ ret = dma_async_device_register(&tdma->dma_dev);
+ if (ret < 0) {
+ dev_err(&pdev->dev,
+ "Tegra210 ADMA driver registration failed %d\n", ret);
+ goto err_irq;
+ }
+
+ ret = of_dma_controller_register(pdev->dev.of_node,
+ tegra_dma_of_xlate, tdma);
+ if (ret < 0) {
+ dev_err(&pdev->dev,
+ "Tegra210 ADMA OF registration failed %d\n", ret);
+ goto err_unregister_dma_dev;
+ }
+
+ pm_runtime_put(&pdev->dev);
+
+ dev_info(&pdev->dev, "Tegra210 ADMA driver register %d channels\n",
+ cdata->nr_channels);
+ return 0;
+
+err_unregister_dma_dev:
+ dma_async_device_unregister(&tdma->dma_dev);
+err_irq:
+ while (--i >= 0) {
+ struct tegra_dma_channel *tdc = &tdma->channels[i];
+
+ tasklet_kill(&tdc->tasklet);
+ }
+ if (!pm_runtime_status_suspended(&pdev->dev))
+ tegra_adma_runtime_suspend(&pdev->dev);
+err_pm_disable:
+ pm_runtime_disable(&pdev->dev);
+
+ return ret;
+}
+
+static int tegra_adma_remove(struct platform_device *pdev)
+{
+ struct tegra_dma *tdma = platform_get_drvdata(pdev);
+ int i;
+ struct tegra_dma_channel *tdc;
+
+ dma_async_device_unregister(&tdma->dma_dev);
+
+ for (i = 0; i < tdma->chip_data->nr_channels; ++i) {
+ tdc = &tdma->channels[i];
+ tasklet_kill(&tdc->tasklet);
+ }
+
+ if (!pm_runtime_status_suspended(&pdev->dev))
+ tegra_adma_runtime_suspend(&pdev->dev);
+
+ pm_runtime_disable(&pdev->dev);
+
+ return 0;
+}
+
+static int tegra_adma_runtime_suspend(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct tegra_dma *tdma = platform_get_drvdata(pdev);
+
+ clk_disable_unprepare(tdma->dma_clk);
+ clk_disable_unprepare(tdma->domain_clk);
+ return 0;
+}
+
+static int tegra_adma_runtime_resume(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct tegra_dma *tdma = platform_get_drvdata(pdev);
+ int ret;
+
+ ret = clk_prepare_enable(tdma->domain_clk);
+ if (ret < 0) {
+ dev_err(dev, "clk_prepare_enable failed: %d\n", ret);
+ return ret;
+ }
+
+ ret = clk_prepare_enable(tdma->dma_clk);
+ if (ret < 0) {
+ dev_err(dev, "clk_prepare_enable failed: %d\n", ret);
+ return ret;
+ }
+ return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int tegra_adma_pm_suspend(struct device *dev)
+{
+ struct tegra_dma *tdma = dev_get_drvdata(dev);
+ int i;
+ int ret;
+
+ ret = pm_runtime_get_sync(dev);
+ if (ret < 0)
+ return ret;
+
+ tdma->reg_global = tdma_read(tdma, ADMA_GLOBAL_CMD);
+ for (i = 0; i < tdma->chip_data->nr_channels; i++) {
+ struct tegra_dma_channel *tdc = &tdma->channels[i];
+ struct tegra_adma_chan_regs *ch_reg = &tdc->adma_ch_regs;
+
+ ch_reg->tc = tdc_read(tdc, ADMA_CH_TC);
+ ch_reg->src_ptr = tdc_read(tdc, ADMA_CH_LOWER_SOURCE_ADDR);
+ ch_reg->tgt_ptr = tdc_read(tdc, ADMA_CH_LOWER_TARGET_ADDR);
+ ch_reg->ctrl = tdc_read(tdc, ADMA_CH_CTRL);
+ ch_reg->ahub_fifo_ctrl =
+ tdc_read(tdc, ADMA_CH_AHUB_FIFO_CTRL);
+ ch_reg->config = tdc_read(tdc, ADMA_CH_CONFIG);
+ }
+ pm_runtime_put(dev);
+ return 0;
+}
+
+static int tegra_adma_pm_resume(struct device *dev)
+{
+ struct tegra_dma *tdma = dev_get_drvdata(dev);
+ int i;
+ int ret;
+
+ ret = pm_runtime_get_sync(dev);
+ if (ret < 0)
+ return ret;
+
+ tdma_write(tdma, ADMA_GLOBAL_CMD, tdma->reg_global);
+
+ for (i = 0; i < tdma->chip_data->nr_channels; i++) {
+ struct tegra_dma_channel *tdc = &tdma->channels[i];
+ struct tegra_adma_chan_regs *ch_reg = &tdc->adma_ch_regs;
+
+ tdc_write(tdc, ADMA_CH_TC, ch_reg->tc);
+ tdc_write(tdc, ADMA_CH_LOWER_SOURCE_ADDR, ch_reg->src_ptr);
+ tdc_write(tdc, ADMA_CH_LOWER_TARGET_ADDR, ch_reg->tgt_ptr);
+ tdc_write(tdc, ADMA_CH_CTRL, ch_reg->ctrl);
+ tdc_write(tdc, ADMA_CH_AHUB_FIFO_CTRL,
+ ch_reg->ahub_fifo_ctrl);
+ tdc_write(tdc, ADMA_CH_CONFIG, ch_reg->config);
+ }
+ pm_runtime_put(dev);
+ return 0;
+}
+#endif
+
+static const struct dev_pm_ops tegra_adma_dev_pm_ops = {
+#ifdef CONFIG_PM
+ .runtime_suspend = tegra_adma_runtime_suspend,
+ .runtime_resume = tegra_adma_runtime_resume,
+#endif
+ SET_SYSTEM_SLEEP_PM_OPS(tegra_adma_pm_suspend, tegra_adma_pm_resume)
+};
+
+static struct platform_driver tegra_admac_driver = {
+ .driver = {
+ .name = "tegra-adma",
+ .owner = THIS_MODULE,
+ .pm = &tegra_adma_dev_pm_ops,
+ .of_match_table = of_match_ptr(tegra_adma_of_match),
+ },
+ .probe = tegra_adma_probe,
+ .remove = tegra_adma_remove,
+ .id_table = tegra_adma_devtype,
+};
+
+module_platform_driver(tegra_admac_driver);
+
+MODULE_ALIAS("platform:tegra210-adma");
+MODULE_DESCRIPTION("NVIDIA Tegra ADMA Controller driver");
+MODULE_AUTHOR("Dara Ramesh <[email protected]>");
+MODULE_AUTHOR("Jon Hunter <[email protected]>");
+MODULE_LICENSE("GPL v2");
--
2.1.4
On Tue, Aug 18, 2015 at 02:49:09PM +0100, Jon Hunter wrote:
> @@ -1543,7 +1531,7 @@ static int tegra_dma_pm_suspend(struct device *dev)
> int ret;
>
> /* Enable clock before accessing register */
> - ret = tegra_dma_runtime_resume(dev);
> + ret = pm_runtime_get_sync(dev);
why is this required ?
--
~Vinod
On Tue, Aug 18, 2015 at 02:49:15PM +0100, Jon Hunter wrote:
> +#define AHUB_TO_MEMORY 2
> +#define MEMORY_TO_AHUB 4
namespace this aptly as well
> +static void tegra_adma_stop(struct tegra_dma_channel *tdc)
> +{
> + u32 status;
> +
> + /* TODO: Do we need to disable interrupts here? */
when?
> +static void tegra_adma_start(struct tegra_dma_channel *tdc,
> + struct tegra_dma_sg_req *sg_req)
> +{
> + struct tegra_adma_chan_regs *ch_regs = &sg_req->adma_ch_regs;
> +
> + /* Update transfer done count for position calculation */
> + tdc->adma_ch_regs.tc = ch_regs->tc;
> + tdc_write(tdc, ADMA_CH_TC, ch_regs->tc);
> + tdc_write(tdc, ADMA_CH_CTRL, ch_regs->ctrl);
> + tdc_write(tdc, ADMA_CH_LOWER_SOURCE_ADDR, ch_regs->src_ptr);
> + tdc_write(tdc, ADMA_CH_LOWER_TARGET_ADDR, ch_regs->tgt_ptr);
> + tdc_write(tdc, ADMA_CH_AHUB_FIFO_CTRL, ch_regs->ahub_fifo_ctrl);
> + tdc_write(tdc, ADMA_CH_CONFIG, ch_regs->config);
empty line here please
> +static int tegra_adma_get_xfer_params(struct tegra_dma_channel *tdc,
> + struct tegra_adma_chan_regs *ch_regs,
> + enum dma_transfer_direction direction)
> +{
> + u32 burst_size, ctrl, ctrl_mask, slave_id, fifo_mask, fifo_shift;
> +
> + ch_regs->ahub_fifo_ctrl = tdc_read(tdc, ADMA_CH_AHUB_FIFO_CTRL);
> + ch_regs->config = tdc_read(tdc, ADMA_CH_CONFIG);
> + ch_regs->ctrl = tdc_read(tdc, ADMA_CH_CTRL);
> + slave_id = tdc->dma_sconfig.slave_id;
> +
> + switch (direction) {
> + case DMA_MEM_TO_DEV:
> + burst_size = fls(tdc->dma_sconfig.dst_maxburst);
> + ctrl_mask = ADMA_CH_CTRL_TX_REQUEST_SELECT_MASK;
> + ctrl = MEMORY_TO_AHUB << ADMA_CH_CTRL_TRANSFER_DIRECTION_SHIFT;
> + ctrl |= slave_id << ADMA_CH_CTRL_TX_REQUEST_SELECT_SHIFT;
> + fifo_mask = ADMA_CH_AHUB_FIFO_CTRL_TX_FIFO_SIZE_MASK;
> + fifo_shift = ADMA_CH_AHUB_FIFO_CTRL_TX_FIFO_SIZE_SHIFT;
> + break;
Empty line here pls
> + case DMA_DEV_TO_MEM:
> + burst_size = fls(tdc->dma_sconfig.src_maxburst);
> + ctrl_mask = ADMA_CH_CTRL_RX_REQUEST_SELECT_MASK;
> + ctrl = AHUB_TO_MEMORY << ADMA_CH_CTRL_TRANSFER_DIRECTION_SHIFT;
> + ctrl |= slave_id << ADMA_CH_CTRL_RX_REQUEST_SELECT_SHIFT;
> + fifo_mask = ADMA_CH_AHUB_FIFO_CTRL_RX_FIFO_SIZE_MASK;
> + fifo_shift = ADMA_CH_AHUB_FIFO_CTRL_RX_FIFO_SIZE_SHIFT;
> + break;
here too...
> + default:
> + dev_err(tdc2dev(tdc), "Dma direction is not supported\n");
> + return -EINVAL;
> + }
> +
> + if (!burst_size || burst_size > ADMA_BURSTSIZE_16)
> + burst_size = ADMA_BURSTSIZE_16;
> +
> + ch_regs->ahub_fifo_ctrl &= ~fifo_mask;
> + ch_regs->ahub_fifo_ctrl |= ADMA_FIFO_DEFAULT_SIZE << fifo_shift;
> + ch_regs->config &= ~ADMA_CH_CONFIG_BURST_SIZE_MASK;
> + ch_regs->config |= burst_size << ADMA_CH_CONFIG_BURST_SIZE_SHIFT;
> + ch_regs->ctrl &= ~(ctrl_mask | ADMA_CH_CTRL_TRANSFER_DIRECTION_MASK);
> + ch_regs->ctrl |= ctrl;
> +
> + return -EINVAL;
??
> +static int tegra_adma_pm_suspend(struct device *dev)
> +{
> + struct tegra_dma *tdma = dev_get_drvdata(dev);
> + int i;
> + int ret;
> +
> + ret = pm_runtime_get_sync(dev);
why is this required :)
> +static int tegra_adma_pm_resume(struct device *dev)
> +{
> + struct tegra_dma *tdma = dev_get_drvdata(dev);
> + int i;
> + int ret;
> +
> + ret = pm_runtime_get_sync(dev);
and this
--
~Vinod
On 23/08/15 15:17, Vinod Koul wrote:
> On Tue, Aug 18, 2015 at 02:49:09PM +0100, Jon Hunter wrote:
>
>> @@ -1543,7 +1531,7 @@ static int tegra_dma_pm_suspend(struct device *dev)
>> int ret;
>>
>> /* Enable clock before accessing register */
>> - ret = tegra_dma_runtime_resume(dev);
>> + ret = pm_runtime_get_sync(dev);
>
> why is this required ?
Because the clock could be disabled when this function is called. This
function saves the DMA context so that if the context is lost during
suspend, it can be restored.
Cheers
Jon
On 23/08/15 15:33, Vinod Koul wrote:
> On Tue, Aug 18, 2015 at 02:49:15PM +0100, Jon Hunter wrote:
>> +#define AHUB_TO_MEMORY 2
>> +#define MEMORY_TO_AHUB 4
>
> namespace this aptly as well
>
>> +static void tegra_adma_stop(struct tegra_dma_channel *tdc)
>> +{
>> + u32 status;
>> +
>> + /* TODO: Do we need to disable interrupts here? */
>
> when?
Once everyone is happy with the RFC in general.
>> +static void tegra_adma_start(struct tegra_dma_channel *tdc,
>> + struct tegra_dma_sg_req *sg_req)
>> +{
>> + struct tegra_adma_chan_regs *ch_regs = &sg_req->adma_ch_regs;
>> +
>> + /* Update transfer done count for position calculation */
>> + tdc->adma_ch_regs.tc = ch_regs->tc;
>> + tdc_write(tdc, ADMA_CH_TC, ch_regs->tc);
>> + tdc_write(tdc, ADMA_CH_CTRL, ch_regs->ctrl);
>> + tdc_write(tdc, ADMA_CH_LOWER_SOURCE_ADDR, ch_regs->src_ptr);
>> + tdc_write(tdc, ADMA_CH_LOWER_TARGET_ADDR, ch_regs->tgt_ptr);
>> + tdc_write(tdc, ADMA_CH_AHUB_FIFO_CTRL, ch_regs->ahub_fifo_ctrl);
>> + tdc_write(tdc, ADMA_CH_CONFIG, ch_regs->config);
> empty line here please
Ok.
>> +static int tegra_adma_get_xfer_params(struct tegra_dma_channel *tdc,
>> + struct tegra_adma_chan_regs *ch_regs,
>> + enum dma_transfer_direction direction)
>> +{
>> + u32 burst_size, ctrl, ctrl_mask, slave_id, fifo_mask, fifo_shift;
>> +
>> + ch_regs->ahub_fifo_ctrl = tdc_read(tdc, ADMA_CH_AHUB_FIFO_CTRL);
>> + ch_regs->config = tdc_read(tdc, ADMA_CH_CONFIG);
>> + ch_regs->ctrl = tdc_read(tdc, ADMA_CH_CTRL);
>> + slave_id = tdc->dma_sconfig.slave_id;
>> +
>> + switch (direction) {
>> + case DMA_MEM_TO_DEV:
>> + burst_size = fls(tdc->dma_sconfig.dst_maxburst);
>> + ctrl_mask = ADMA_CH_CTRL_TX_REQUEST_SELECT_MASK;
>> + ctrl = MEMORY_TO_AHUB << ADMA_CH_CTRL_TRANSFER_DIRECTION_SHIFT;
>> + ctrl |= slave_id << ADMA_CH_CTRL_TX_REQUEST_SELECT_SHIFT;
>> + fifo_mask = ADMA_CH_AHUB_FIFO_CTRL_TX_FIFO_SIZE_MASK;
>> + fifo_shift = ADMA_CH_AHUB_FIFO_CTRL_TX_FIFO_SIZE_SHIFT;
>> + break;
> Empty line here pls
Ok, any reason why? Other dma drivers don't appear to do this.
>> + case DMA_DEV_TO_MEM:
>> + burst_size = fls(tdc->dma_sconfig.src_maxburst);
>> + ctrl_mask = ADMA_CH_CTRL_RX_REQUEST_SELECT_MASK;
>> + ctrl = AHUB_TO_MEMORY << ADMA_CH_CTRL_TRANSFER_DIRECTION_SHIFT;
>> + ctrl |= slave_id << ADMA_CH_CTRL_RX_REQUEST_SELECT_SHIFT;
>> + fifo_mask = ADMA_CH_AHUB_FIFO_CTRL_RX_FIFO_SIZE_MASK;
>> + fifo_shift = ADMA_CH_AHUB_FIFO_CTRL_RX_FIFO_SIZE_SHIFT;
>> + break;
>
> here too...
>
>> + default:
>> + dev_err(tdc2dev(tdc), "Dma direction is not supported\n");
>> + return -EINVAL;
>> + }
>> +
>> + if (!burst_size || burst_size > ADMA_BURSTSIZE_16)
>> + burst_size = ADMA_BURSTSIZE_16;
>> +
>> + ch_regs->ahub_fifo_ctrl &= ~fifo_mask;
>> + ch_regs->ahub_fifo_ctrl |= ADMA_FIFO_DEFAULT_SIZE << fifo_shift;
>> + ch_regs->config &= ~ADMA_CH_CONFIG_BURST_SIZE_MASK;
>> + ch_regs->config |= burst_size << ADMA_CH_CONFIG_BURST_SIZE_SHIFT;
>> + ch_regs->ctrl &= ~(ctrl_mask | ADMA_CH_CTRL_TRANSFER_DIRECTION_MASK);
>> + ch_regs->ctrl |= ctrl;
>> +
>> + return -EINVAL;
> ??
Thanks. That's an error. Will fix.
>> +static int tegra_adma_pm_suspend(struct device *dev)
>> +{
>> + struct tegra_dma *tdma = dev_get_drvdata(dev);
>> + int i;
>> + int ret;
>> +
>> + ret = pm_runtime_get_sync(dev);
> why is this required :)
To ensure that the clocks are enabled before the registers are read.
This function saves the dma context before suspend, in case the hardware
state is lost.
>> +static int tegra_adma_pm_resume(struct device *dev)
>> +{
>> + struct tegra_dma *tdma = dev_get_drvdata(dev);
>> + int i;
>> + int ret;
>> +
>> + ret = pm_runtime_get_sync(dev);
> and this
Same here.
Cheers
Jon
On Mon, Aug 24, 2015 at 09:47:13AM +0100, Jon Hunter wrote:
>
> On 23/08/15 15:17, Vinod Koul wrote:
> > On Tue, Aug 18, 2015 at 02:49:09PM +0100, Jon Hunter wrote:
> >
> >> @@ -1543,7 +1531,7 @@ static int tegra_dma_pm_suspend(struct device *dev)
> >> int ret;
> >>
> >> /* Enable clock before accessing register */
> >> - ret = tegra_dma_runtime_resume(dev);
> >> + ret = pm_runtime_get_sync(dev);
> >
> > why is this required ?
>
> Because the clock could be disabled when this function is called. This
> function saves the DMA context so that if the context is lost during
> suspend, it can be restored.
Have you verified this? Coz my understanding is that when PM does suspend it
will esnure you are runtime resume if runtime suspended and then will do
suspend.
So you do not need to do above
--
~Vinod
On Mon, Aug 24, 2015 at 09:55:03AM +0100, Jon Hunter wrote:
> >> +static int tegra_adma_get_xfer_params(struct tegra_dma_channel *tdc,
> >> + struct tegra_adma_chan_regs *ch_regs,
> >> + enum dma_transfer_direction direction)
> >> +{
> >> + u32 burst_size, ctrl, ctrl_mask, slave_id, fifo_mask, fifo_shift;
> >> +
> >> + ch_regs->ahub_fifo_ctrl = tdc_read(tdc, ADMA_CH_AHUB_FIFO_CTRL);
> >> + ch_regs->config = tdc_read(tdc, ADMA_CH_CONFIG);
> >> + ch_regs->ctrl = tdc_read(tdc, ADMA_CH_CTRL);
> >> + slave_id = tdc->dma_sconfig.slave_id;
> >> +
> >> + switch (direction) {
> >> + case DMA_MEM_TO_DEV:
> >> + burst_size = fls(tdc->dma_sconfig.dst_maxburst);
> >> + ctrl_mask = ADMA_CH_CTRL_TX_REQUEST_SELECT_MASK;
> >> + ctrl = MEMORY_TO_AHUB << ADMA_CH_CTRL_TRANSFER_DIRECTION_SHIFT;
> >> + ctrl |= slave_id << ADMA_CH_CTRL_TX_REQUEST_SELECT_SHIFT;
> >> + fifo_mask = ADMA_CH_AHUB_FIFO_CTRL_TX_FIFO_SIZE_MASK;
> >> + fifo_shift = ADMA_CH_AHUB_FIFO_CTRL_TX_FIFO_SIZE_SHIFT;
> >> + break;
> > Empty line here pls
>
> Ok, any reason why? Other dma drivers don't appear to do this.
This improves readablity. It is a good idea to sprinkle empty lines between
logial blocks
> >> +static int tegra_adma_pm_suspend(struct device *dev)
> >> +{
> >> + struct tegra_dma *tdma = dev_get_drvdata(dev);
> >> + int i;
> >> + int ret;
> >> +
> >> + ret = pm_runtime_get_sync(dev);
> > why is this required :)
>
> To ensure that the clocks are enabled before the registers are read.
> This function saves the dma context before suspend, in case the hardware
> state is lost.
I think same reason here too, so based on my other argument, this may not be
required!
--
~Vinod
On 24/08/15 10:22, Vinod Koul wrote:
> On Mon, Aug 24, 2015 at 09:47:13AM +0100, Jon Hunter wrote:
>>
>> On 23/08/15 15:17, Vinod Koul wrote:
>>> On Tue, Aug 18, 2015 at 02:49:09PM +0100, Jon Hunter wrote:
>>>
>>>> @@ -1543,7 +1531,7 @@ static int tegra_dma_pm_suspend(struct device *dev)
>>>> int ret;
>>>>
>>>> /* Enable clock before accessing register */
>>>> - ret = tegra_dma_runtime_resume(dev);
>>>> + ret = pm_runtime_get_sync(dev);
>>>
>>> why is this required ?
>>
>> Because the clock could be disabled when this function is called. This
>> function saves the DMA context so that if the context is lost during
>> suspend, it can be restored.
>
> Have you verified this? Coz my understanding is that when PM does suspend it
> will esnure you are runtime resume if runtime suspended and then will do
> suspend.
> So you do not need to do above
I see what you are saying. I did some testing with ftrace today to trace
rpm and suspend/resume calls. If the dma controller is runtime suspended
and I do not call pm_runtime_get_sync() above then I do not see any
runtime resume of the dma controller prior to suspend. Now I was hoping
that this would cause a complete kernel crash but it did not and so the
DMA clock did not appear to be needed here (at least on the one board I
tested). However, I would not go as far as to remove this and prefer to
keep as above.
Furthermore, other drivers do similar things, including the sirf dma
controller (see sirf-dma.c).
Cheers
Jon
On Mon, Aug 24, 2015 at 02:22:49PM +0100, Jon Hunter wrote:
>
> On 24/08/15 10:22, Vinod Koul wrote:
> > On Mon, Aug 24, 2015 at 09:47:13AM +0100, Jon Hunter wrote:
> >>
> >> On 23/08/15 15:17, Vinod Koul wrote:
> >>> On Tue, Aug 18, 2015 at 02:49:09PM +0100, Jon Hunter wrote:
> >>>
> >>>> @@ -1543,7 +1531,7 @@ static int tegra_dma_pm_suspend(struct device *dev)
> >>>> int ret;
> >>>>
> >>>> /* Enable clock before accessing register */
> >>>> - ret = tegra_dma_runtime_resume(dev);
> >>>> + ret = pm_runtime_get_sync(dev);
> >>>
> >>> why is this required ?
> >>
> >> Because the clock could be disabled when this function is called. This
> >> function saves the DMA context so that if the context is lost during
> >> suspend, it can be restored.
> >
> > Have you verified this? Coz my understanding is that when PM does suspend it
> > will esnure you are runtime resume if runtime suspended and then will do
> > suspend.
> > So you do not need to do above
>
> I see what you are saying. I did some testing with ftrace today to trace
> rpm and suspend/resume calls. If the dma controller is runtime suspended
> and I do not call pm_runtime_get_sync() above then I do not see any
> runtime resume of the dma controller prior to suspend. Now I was hoping
> that this would cause a complete kernel crash but it did not and so the
> DMA clock did not appear to be needed here (at least on the one board I
> tested). However, I would not go as far as to remove this and prefer to
> keep as above.
Okay am adding Rafael here for his recommendations.
I have tested in past and if my driver was runtime suspended we were resumed
prior to being suspended. So I am not sure why you did not see that
behaviour, and if that is right we don't need to force resume here
--
~Vinod
On Monday, August 24, 2015 07:51:43 PM Vinod Koul wrote:
> On Mon, Aug 24, 2015 at 02:22:49PM +0100, Jon Hunter wrote:
> >
> > On 24/08/15 10:22, Vinod Koul wrote:
> > > On Mon, Aug 24, 2015 at 09:47:13AM +0100, Jon Hunter wrote:
> > >>
> > >> On 23/08/15 15:17, Vinod Koul wrote:
> > >>> On Tue, Aug 18, 2015 at 02:49:09PM +0100, Jon Hunter wrote:
> > >>>
> > >>>> @@ -1543,7 +1531,7 @@ static int tegra_dma_pm_suspend(struct device *dev)
> > >>>> int ret;
> > >>>>
> > >>>> /* Enable clock before accessing register */
> > >>>> - ret = tegra_dma_runtime_resume(dev);
> > >>>> + ret = pm_runtime_get_sync(dev);
> > >>>
> > >>> why is this required ?
> > >>
> > >> Because the clock could be disabled when this function is called. This
> > >> function saves the DMA context so that if the context is lost during
> > >> suspend, it can be restored.
> > >
> > > Have you verified this? Coz my understanding is that when PM does suspend it
> > > will esnure you are runtime resume if runtime suspended and then will do
> > > suspend.
> > > So you do not need to do above
> >
> > I see what you are saying. I did some testing with ftrace today to trace
> > rpm and suspend/resume calls. If the dma controller is runtime suspended
> > and I do not call pm_runtime_get_sync() above then I do not see any
> > runtime resume of the dma controller prior to suspend. Now I was hoping
> > that this would cause a complete kernel crash but it did not and so the
> > DMA clock did not appear to be needed here (at least on the one board I
> > tested). However, I would not go as far as to remove this and prefer to
> > keep as above.
>
> Okay am adding Rafael here for his recommendations.
Well, and what is the question I'm supposed to answer, exactly?
I was in Seattle last week, so haven't been following this closely.
> I have tested in past and if my driver was runtime suspended we were resumed
> prior to being suspended. So I am not sure why you did not see that
> behaviour, and if that is right we don't need to force resume here
We're adding code for skipping runtime-resume-before-system-suspend, because
it is not desirable in general.
The rule of thumb is that if you know you need to change the device's settings
(eg. because of wakeup being enabled or not) for system suspend and that
requires the device to be resumed, resume it. It can stay suspended
otherwise.
Thanks,
Rafael
On 25/08/15 01:04, Rafael J. Wysocki wrote:
> On Monday, August 24, 2015 07:51:43 PM Vinod Koul wrote:
>> On Mon, Aug 24, 2015 at 02:22:49PM +0100, Jon Hunter wrote:
>>>
>>> On 24/08/15 10:22, Vinod Koul wrote:
>>>> On Mon, Aug 24, 2015 at 09:47:13AM +0100, Jon Hunter wrote:
>>>>>
>>>>> On 23/08/15 15:17, Vinod Koul wrote:
>>>>>> On Tue, Aug 18, 2015 at 02:49:09PM +0100, Jon Hunter wrote:
>>>>>>
>>>>>>> @@ -1543,7 +1531,7 @@ static int tegra_dma_pm_suspend(struct device *dev)
>>>>>>> int ret;
>>>>>>>
>>>>>>> /* Enable clock before accessing register */
>>>>>>> - ret = tegra_dma_runtime_resume(dev);
>>>>>>> + ret = pm_runtime_get_sync(dev);
>>>>>>
>>>>>> why is this required ?
>>>>>
>>>>> Because the clock could be disabled when this function is called. This
>>>>> function saves the DMA context so that if the context is lost during
>>>>> suspend, it can be restored.
>>>>
>>>> Have you verified this? Coz my understanding is that when PM does suspend it
>>>> will esnure you are runtime resume if runtime suspended and then will do
>>>> suspend.
>>>> So you do not need to do above
>>>
>>> I see what you are saying. I did some testing with ftrace today to trace
>>> rpm and suspend/resume calls. If the dma controller is runtime suspended
>>> and I do not call pm_runtime_get_sync() above then I do not see any
>>> runtime resume of the dma controller prior to suspend. Now I was hoping
>>> that this would cause a complete kernel crash but it did not and so the
>>> DMA clock did not appear to be needed here (at least on the one board I
>>> tested). However, I would not go as far as to remove this and prefer to
>>> keep as above.
>>
>> Okay am adding Rafael here for his recommendations.
>
> Well, and what is the question I'm supposed to answer, exactly?
>
> I was in Seattle last week, so haven't been following this closely.
>
>> I have tested in past and if my driver was runtime suspended we were resumed
>> prior to being suspended. So I am not sure why you did not see that
>> behaviour, and if that is right we don't need to force resume here
>
> We're adding code for skipping runtime-resume-before-system-suspend, because
> it is not desirable in general.
>
> The rule of thumb is that if you know you need to change the device's settings
> (eg. because of wakeup being enabled or not) for system suspend and that
> requires the device to be resumed, resume it. It can stay suspended
> otherwise.
Thanks Rafael.
Vinod, thinking about this some more, I am wondering if it is just
better to get rid of the suspend/resume callbacks and simply handling
the state in the runtime suspend/resume callbacks. I think that would be
safe too, because once the clock has been disabled, then who knows what
the context state will be.
Cheers
Jon
On 8/25/2015 11:37 AM, Jon Hunter wrote:
> On 25/08/15 01:04, Rafael J. Wysocki wrote:
>> On Monday, August 24, 2015 07:51:43 PM Vinod Koul wrote:
>>> On Mon, Aug 24, 2015 at 02:22:49PM +0100, Jon Hunter wrote:
>>>> On 24/08/15 10:22, Vinod Koul wrote:
>>>>> On Mon, Aug 24, 2015 at 09:47:13AM +0100, Jon Hunter wrote:
>>>>>> On 23/08/15 15:17, Vinod Koul wrote:
>>>>>>> On Tue, Aug 18, 2015 at 02:49:09PM +0100, Jon Hunter wrote:
>>>>>>>
>>>>>>>> @@ -1543,7 +1531,7 @@ static int tegra_dma_pm_suspend(struct device *dev)
>>>>>>>> int ret;
>>>>>>>>
>>>>>>>> /* Enable clock before accessing register */
>>>>>>>> - ret = tegra_dma_runtime_resume(dev);
>>>>>>>> + ret = pm_runtime_get_sync(dev);
>>>>>>> why is this required ?
>>>>>> Because the clock could be disabled when this function is called. This
>>>>>> function saves the DMA context so that if the context is lost during
>>>>>> suspend, it can be restored.
>>>>> Have you verified this? Coz my understanding is that when PM does suspend it
>>>>> will esnure you are runtime resume if runtime suspended and then will do
>>>>> suspend.
>>>>> So you do not need to do above
>>>> I see what you are saying. I did some testing with ftrace today to trace
>>>> rpm and suspend/resume calls. If the dma controller is runtime suspended
>>>> and I do not call pm_runtime_get_sync() above then I do not see any
>>>> runtime resume of the dma controller prior to suspend. Now I was hoping
>>>> that this would cause a complete kernel crash but it did not and so the
>>>> DMA clock did not appear to be needed here (at least on the one board I
>>>> tested). However, I would not go as far as to remove this and prefer to
>>>> keep as above.
>>> Okay am adding Rafael here for his recommendations.
>> Well, and what is the question I'm supposed to answer, exactly?
>>
>> I was in Seattle last week, so haven't been following this closely.
>>
>>> I have tested in past and if my driver was runtime suspended we were resumed
>>> prior to being suspended. So I am not sure why you did not see that
>>> behaviour, and if that is right we don't need to force resume here
>> We're adding code for skipping runtime-resume-before-system-suspend, because
>> it is not desirable in general.
>>
>> The rule of thumb is that if you know you need to change the device's settings
>> (eg. because of wakeup being enabled or not) for system suspend and that
>> requires the device to be resumed, resume it. It can stay suspended
>> otherwise.
> Thanks Rafael.
>
> Vinod, thinking about this some more, I am wondering if it is just
> better to get rid of the suspend/resume callbacks and simply handling
> the state in the runtime suspend/resume callbacks. I think that would be
> safe too, because once the clock has been disabled, then who knows what
> the context state will be.
One caveat here: system suspend may be invoked at any time, so you need
to ensure that the device is properly suspended when that happens.
I believe you at least need a ->suspend callback for that.
Cheers,
Rafael
On 25/08/15 23:46, Rafael J. Wysocki wrote:
> On 8/25/2015 11:37 AM, Jon Hunter wrote:
[snip]
>> Vinod, thinking about this some more, I am wondering if it is just
>> better to get rid of the suspend/resume callbacks and simply handling
>> the state in the runtime suspend/resume callbacks. I think that would be
>> safe too, because once the clock has been disabled, then who knows what
>> the context state will be.
>
> One caveat here: system suspend may be invoked at any time, so you need
> to ensure that the device is properly suspended when that happens.
>
> I believe you at least need a ->suspend callback for that.
Thanks, makes sense.
On a related note, I see a few drivers, including this DMA driver doing
the following in the driver ->remove callback.
pm_runtime_disable(&pdev->dev);
!pm_runtime_status_suspended(&pdev->dev))
tegra_dma_runtime_suspend(&pdev->dev);
I understand that the code is trying to ensure that the device is
suspended regardless of whether rpm is enabled or not in the kernel
config. However, looking at the pm_runtime_status_suspended() function,
AFAICT, it will always return false above as the disable_depth will be
greater than 0. So I am concerned that the tegra_dma_runtime_suspend()
is called even when not needed? However, I could also be missing
something here.
Cheers
Jon