Resending due to lack of any response to the original series
Add PCI, NAND, and TWD Support to the Broadcom Northstar Plus SoC device
tree file. Since no driver changes are needed to enable these pieces of
hardware, only the device tree changes are required to make them
functional.
Jon Mason (3):
ARM: dts: NSP: Add PCI support
ARM: dts: NSP: Add NAND Support to DT
ARM: dts: NSP: Add TWD Support to DT
arch/arm/boot/dts/bcm-nsp.dtsi | 104 ++++++++++++++++++++++++++++++++++++++-
arch/arm/boot/dts/bcm958625k.dts | 50 +++++++++++++++++++
2 files changed, 153 insertions(+), 1 deletion(-)
--
1.9.1
Add PCI support to the Northstar Plus SoC. This uses the existing
pcie-iproc driver. So, all that is needed is device tree entries in the
DTS.
Signed-off-by: Jon Mason <[email protected]>
---
arch/arm/boot/dts/bcm-nsp.dtsi | 74 +++++++++++++++++++++++++++++++++++++++-
arch/arm/boot/dts/bcm958625k.dts | 12 +++++++
2 files changed, 85 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index 58aca27..85fb1c8 100644
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -96,7 +96,7 @@
axi {
compatible = "simple-bus";
- ranges = <0x00000000 0x18000000 0x00001000>;
+ ranges = <0x00000000 0x18000000 0x00015000>;
#address-cells = <1>;
#size-cells = <1>;
@@ -115,5 +115,77 @@
clock-frequency = <62499840>;
status = "disabled";
};
+
+ pcie0: pcie@18012000 {
+ compatible = "brcm,iproc-pcie";
+ reg = <0x12000 0x1000>;
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_NONE>;
+
+ linux,pci-domain = <0>;
+
+ bus-range = <0x00 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+
+ /* Note: The HW does not support I/O resources. So,
+ * only the memory resource range is being specified.
+ */
+ ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>;
+
+ status = "disabled";
+ };
+
+ pcie1: pcie@18013000 {
+ compatible = "brcm,iproc-pcie";
+ reg = <0x13000 0x1000>;
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 137 IRQ_TYPE_NONE>;
+
+ linux,pci-domain = <1>;
+
+ bus-range = <0x00 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+
+ /* Note: The HW does not support I/O resources. So,
+ * only the memory resource range is being specified.
+ */
+ ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>;
+
+ status = "disabled";
+ };
+
+ pcie2: pcie@18014000 {
+ compatible = "brcm,iproc-pcie";
+ reg = <0x14000 0x1000>;
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 143 IRQ_TYPE_NONE>;
+
+ linux,pci-domain = <2>;
+
+ bus-range = <0x00 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+
+ /* Note: The HW does not support I/O resources. So,
+ * only the memory resource range is being specified.
+ */
+ ranges = <0x82000000 0 0x48000000 0x48000000 0 0x8000000>;
+
+ status = "disabled";
+ };
};
};
diff --git a/arch/arm/boot/dts/bcm958625k.dts b/arch/arm/boot/dts/bcm958625k.dts
index 16303db..4859268 100644
--- a/arch/arm/boot/dts/bcm958625k.dts
+++ b/arch/arm/boot/dts/bcm958625k.dts
@@ -55,3 +55,15 @@
&uart1 {
status = "okay";
};
+
+&pcie0 {
+ status = "okay";
+};
+
+&pcie1 {
+ status = "okay";
+};
+
+&pcie2 {
+ status = "okay";
+};
--
1.9.1
Add NAND support to the device tree for the Broadcom Northstar Plus SoC.
Since no driver changes are needed to enable this hardware, only the
device tree changes are required to make this functional.
Signed-off-by: Jon Mason <[email protected]>
---
arch/arm/boot/dts/bcm-nsp.dtsi | 16 +++++++++++++++-
arch/arm/boot/dts/bcm958625k.dts | 38 ++++++++++++++++++++++++++++++++++++++
2 files changed, 53 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index 85fb1c8..62bc86f 100644
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -96,7 +96,7 @@
axi {
compatible = "simple-bus";
- ranges = <0x00000000 0x18000000 0x00015000>;
+ ranges = <0x00000000 0x18000000 0x0011ba08>;
#address-cells = <1>;
#size-cells = <1>;
@@ -187,5 +187,19 @@
status = "disabled";
};
+
+ nand: nand@18026000 {
+ compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
+ reg = <0x026000 0x600>,
+ <0x11b408 0x600>,
+ <0x026f00 0x20>;
+ reg-names = "nand", "iproc-idm", "iproc-ext";
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ brcm,nand-has-wp;
+ };
};
};
diff --git a/arch/arm/boot/dts/bcm958625k.dts b/arch/arm/boot/dts/bcm958625k.dts
index 4859268..b966955 100644
--- a/arch/arm/boot/dts/bcm958625k.dts
+++ b/arch/arm/boot/dts/bcm958625k.dts
@@ -67,3 +67,41 @@
&pcie2 {
status = "okay";
};
+
+&nand {
+ nandcs@0 {
+ compatible = "brcm,nandcs";
+ reg = <0>;
+ nand-on-flash-bbt;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ nand-ecc-strength = <24>;
+ nand-ecc-step-size = <1024>;
+
+ brcm,nand-oob-sector-size = <27>;
+
+ partition@0 {
+ label = "nboot";
+ reg = <0x00000000 0x00200000>;
+ read-only;
+ };
+ partition@1 {
+ label = "nenv";
+ reg = <0x00200000 0x00400000>;
+ };
+ partition@2 {
+ label = "nsystem";
+ reg = <0x00600000 0x00a00000>;
+ };
+ partition@3 {
+ label = "nrootfs";
+ reg = <0x01000000 0x03000000>;
+ };
+ partition@4 {
+ label = "ncustfs";
+ reg = <0x04000000 0x3c000000>;
+ };
+ };
+};
--
1.9.1
Add support for the ARM TWD Timer and Watchdog to the Northstar Plus
device tree.
Signed-off-by: Jon Mason <[email protected]>
---
arch/arm/boot/dts/bcm-nsp.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index 62bc86f..4bcdd28 100644
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -80,6 +80,22 @@
interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&periph_clk>;
};
+
+ twd-timer@19020600 {
+ compatible = "arm,cortex-a9-twd-timer";
+ reg = <0x0600 0x20>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ clocks = <&periph_clk>;
+ };
+
+ twd-watchdog@19020620 {
+ compatible = "arm,cortex-a9-twd-wdt";
+ reg = <0x0620 0x20>;
+ interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ clocks = <&periph_clk>;
+ };
};
clocks {
--
1.9.1
On 02/11/15 10:40, Jon Mason wrote:
> Resending due to lack of any response to the original series
>
> Add PCI, NAND, and TWD Support to the Broadcom Northstar Plus SoC device
> tree file. Since no driver changes are needed to enable these pieces of
> hardware, only the device tree changes are required to make them
> functional.
Series applied to devicetree/next, thanks Jon!
--
Florian