This patch serie adds support for TS-4800 board. This board,
manufactured by Technologic Systems, is based on an IMX515.
The first stage bootloader, called TS-BOOTROM, enables the watchdog,
so a watchdog driver is required to prevent board from rebooting.
The current device tree is minimal but it allows to get a shell on the
board.
Changes in v5:
- watchdog: changed iteration stop condition in set_timeout to be less
error prone
Changes in v4:
- syscon: rewrite DT property reading to be clearer
- watchdog: made fixes suggested by Guenter (now uses
watchdog_init_timeout, u32 instead of u16, fixed error checking in
probe, cleaned set_timeout)
Changes in v3:
- Rebased on v4.3
- Changed vendor prefix from "ts" to "technologic"
- Added a DT option to generic syscon driver to allow regmap configuration
- Dropped custom mfd driver, use generic syscon driver instead.
Changes in v2:
- Added a mfd driver to handle syscon registers
- The watchdog driver now uses the regmap (created by the mfd driver)
to access the feed register
- Remove watchdog's dependency on SOC_IMX51
Damien Riegel (5):
of: add vendor prefix for Technologic Systems
mfd: syscon: add a DT property to set value width
watchdog: ts4800: add driver for TS-4800 watchdog
ARM: imx_v6_v7_defconfig: add TS-4800 watchdog
ARM: dts: TS-4800: add basic device tree
.../devicetree/bindings/arm/technologic.txt | 6 +
Documentation/devicetree/bindings/mfd/syscon.txt | 3 +
.../devicetree/bindings/vendor-prefixes.txt | 1 +
.../devicetree/bindings/watchdog/ts4800-wdt.txt | 25 +++
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/imx51-ts4800.dts | 190 ++++++++++++++++++
arch/arm/configs/imx_v6_v7_defconfig | 1 +
drivers/mfd/syscon.c | 13 ++
drivers/watchdog/Kconfig | 10 +
drivers/watchdog/Makefile | 1 +
drivers/watchdog/ts4800_wdt.c | 215 +++++++++++++++++++++
11 files changed, 467 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/arm/technologic.txt
create mode 100644 Documentation/devicetree/bindings/watchdog/ts4800-wdt.txt
create mode 100644 arch/arm/boot/dts/imx51-ts4800.dts
create mode 100644 drivers/watchdog/ts4800_wdt.c
--
2.5.0
Signed-off-by: Damien Riegel <[email protected]>
Acked-by: Lee Jones <[email protected]>
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 82d2ac9..0a70537 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -223,6 +223,7 @@ toshiba Toshiba Corporation
toumaz Toumaz
tplink TP-LINK Technologies Co., Ltd.
truly Truly Semiconductors Limited
+technologic Technologic Systems
usi Universal Scientific Industrial Co., Ltd.
v3 V3 Semiconductor
variscite Variscite Ltd.
--
2.5.0
Currently syscon has a fixed configuration of 32 bits for register and
values widths. In some cases, it would be desirable to be able to
customize the value width.
For example, certain boards (like the ones manufactured by Technologic
Systems) have a FPGA that is memory-mapped, but its registers are only
16-bit wide.
This patch adds an optional "bus-width" DT binding for syscon that
allows to change the width for the data bus (i.e. val_bits). If this
property is provided, it will also adjust the register stride to
bus-width / 8. If not provided, the default configuration is used.
Signed-off-by: Damien Riegel <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Acked-by: Lee Jones <[email protected]>
---
Documentation/devicetree/bindings/mfd/syscon.txt | 3 +++
drivers/mfd/syscon.c | 13 +++++++++++++
2 files changed, 16 insertions(+)
diff --git a/Documentation/devicetree/bindings/mfd/syscon.txt b/Documentation/devicetree/bindings/mfd/syscon.txt
index fe8150b..4c9d187 100644
--- a/Documentation/devicetree/bindings/mfd/syscon.txt
+++ b/Documentation/devicetree/bindings/mfd/syscon.txt
@@ -13,6 +13,9 @@ Required properties:
- compatible: Should contain "syscon".
- reg: the register region can be accessed from syscon
+Optional property:
+- bus-width: width of the data bus. Can be <8>, <16>, <32>, or <64>.
+
Examples:
gpr: iomuxc-gpr@020e0000 {
compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
diff --git a/drivers/mfd/syscon.c b/drivers/mfd/syscon.c
index 176bf0f..5a93d80 100644
--- a/drivers/mfd/syscon.c
+++ b/drivers/mfd/syscon.c
@@ -47,6 +47,7 @@ static struct syscon *of_syscon_register(struct device_node *np)
struct syscon *syscon;
struct regmap *regmap;
void __iomem *base;
+ u32 bus_width;
int ret;
struct regmap_config syscon_config = syscon_regmap_config;
@@ -69,6 +70,18 @@ static struct syscon *of_syscon_register(struct device_node *np)
else if (of_property_read_bool(np, "little-endian"))
syscon_config.val_format_endian = REGMAP_ENDIAN_LITTLE;
+ /*
+ * search for bus-width property in DT. If it is not provided, default
+ * to 32-bit. regmap_init_mmio will return an error if syscon_config's
+ * values are invalid so there is no need to check them here.
+ */
+ ret = of_property_read_u32(np, "bus-width", &bus_width);
+ if (ret)
+ bus_width = 32;
+
+ syscon_config.val_bits = bus_width;
+ syscon_config.reg_stride = syscon_config.val_bits / 8;
+
regmap = regmap_init_mmio(NULL, base, &syscon_config);
if (IS_ERR(regmap)) {
pr_err("regmap init failed\n");
--
2.5.0
This watchdog is instantiated in a FPGA that is memory mapped. It is
made of only one register, called the feed register. Writing to this
register will re-arm the watchdog for a given time (and enable it if it
was disable). It can be disabled by writing a special value into it.
It is part of a syscon block, and the watchdog register offset in this
block varies from board to board. This offset is passed in the syscon
property after the phandle to the syscon node.
Signed-off-by: Damien Riegel <[email protected]>
---
.../devicetree/bindings/watchdog/ts4800-wdt.txt | 25 +++
drivers/watchdog/Kconfig | 10 +
drivers/watchdog/Makefile | 1 +
drivers/watchdog/ts4800_wdt.c | 215 +++++++++++++++++++++
4 files changed, 251 insertions(+)
create mode 100644 Documentation/devicetree/bindings/watchdog/ts4800-wdt.txt
create mode 100644 drivers/watchdog/ts4800_wdt.c
diff --git a/Documentation/devicetree/bindings/watchdog/ts4800-wdt.txt b/Documentation/devicetree/bindings/watchdog/ts4800-wdt.txt
new file mode 100644
index 0000000..388c60f
--- /dev/null
+++ b/Documentation/devicetree/bindings/watchdog/ts4800-wdt.txt
@@ -0,0 +1,25 @@
+Technologic Systems Watchdog
+
+Required properties:
+- compatible: must be "technologic,ts4800-wdt"
+- syscon: phandle / integer array that points to the syscon node which
+ describes the FPGA's syscon registers.
+ - phandle to FPGA's syscon
+ - offset to the watchdog register
+
+Optional property:
+- timeout-sec: contains the watchdog timeout in seconds.
+
+Example:
+
+syscon: syscon@b0010000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0xb0010000 0x3d>;
+ bus-width = <16>;
+
+ wdt@e {
+ compatible = "technologic,ts4800-wdt";
+ syscon = <&syscon 0xe>;
+ timeout-sec = <10>;
+ };
+}
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 79e1aa1..2914594 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -426,6 +426,16 @@ config NUC900_WATCHDOG
To compile this driver as a module, choose M here: the
module will be called nuc900_wdt.
+config TS4800_WATCHDOG
+ tristate "TS-4800 Watchdog"
+ depends on OF
+ select WATCHDOG_CORE
+ select MFD_SYSCON
+ help
+ Technologic Systems TS-4800 has watchdog timer implemented in
+ an external FPGA. Say Y here if you want to support for the
+ watchdog timer on TS-4800 board.
+
config TS72XX_WATCHDOG
tristate "TS-72XX SBC Watchdog"
depends on MACH_TS72XX
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 0c616e3..3863ce0 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -53,6 +53,7 @@ obj-$(CONFIG_RN5T618_WATCHDOG) += rn5t618_wdt.o
obj-$(CONFIG_COH901327_WATCHDOG) += coh901327_wdt.o
obj-$(CONFIG_STMP3XXX_RTC_WATCHDOG) += stmp3xxx_rtc_wdt.o
obj-$(CONFIG_NUC900_WATCHDOG) += nuc900_wdt.o
+obj-$(CONFIG_TS4800_WATCHDOG) += ts4800_wdt.o
obj-$(CONFIG_TS72XX_WATCHDOG) += ts72xx_wdt.o
obj-$(CONFIG_IMX2_WDT) += imx2_wdt.o
obj-$(CONFIG_UX500_WATCHDOG) += ux500_wdt.o
diff --git a/drivers/watchdog/ts4800_wdt.c b/drivers/watchdog/ts4800_wdt.c
new file mode 100644
index 0000000..2b8de86
--- /dev/null
+++ b/drivers/watchdog/ts4800_wdt.c
@@ -0,0 +1,215 @@
+/*
+ * Watchdog driver for TS-4800 based boards
+ *
+ * Copyright (c) 2015 - Savoir-faire Linux
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/watchdog.h>
+
+static bool nowayout = WATCHDOG_NOWAYOUT;
+module_param(nowayout, bool, 0);
+MODULE_PARM_DESC(nowayout,
+ "Watchdog cannot be stopped once started (default="
+ __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
+
+/* possible feed values */
+#define TS4800_WDT_FEED_2S 0x1
+#define TS4800_WDT_FEED_10S 0x2
+#define TS4800_WDT_DISABLE 0x3
+
+struct ts4800_wdt {
+ struct watchdog_device wdd;
+ struct regmap *regmap;
+ u32 feed_offset;
+ u32 feed_val;
+};
+
+/*
+ * TS-4800 supports the following timeout values:
+ *
+ * value desc
+ * ---------------------
+ * 0 feed for 338ms
+ * 1 feed for 2.706s
+ * 2 feed for 10.824s
+ * 3 disable watchdog
+ *
+ * Keep the regmap/timeout map ordered by timeout
+ */
+static const struct {
+ const int timeout;
+ const int regval;
+} ts4800_wdt_map[] = {
+ { 2, TS4800_WDT_FEED_2S },
+ { 10, TS4800_WDT_FEED_10S },
+};
+
+#define MAX_TIMEOUT_INDEX (ARRAY_SIZE(ts4800_wdt_map) - 1)
+
+static void ts4800_write_feed(struct ts4800_wdt *wdt, u32 val)
+{
+ regmap_write(wdt->regmap, wdt->feed_offset, val);
+}
+
+static int ts4800_wdt_start(struct watchdog_device *wdd)
+{
+ struct ts4800_wdt *wdt = watchdog_get_drvdata(wdd);
+
+ ts4800_write_feed(wdt, wdt->feed_val);
+ return 0;
+}
+
+static int ts4800_wdt_stop(struct watchdog_device *wdd)
+{
+ struct ts4800_wdt *wdt = watchdog_get_drvdata(wdd);
+
+ ts4800_write_feed(wdt, TS4800_WDT_DISABLE);
+ return 0;
+}
+
+static int ts4800_wdt_set_timeout(struct watchdog_device *wdd,
+ unsigned int timeout)
+{
+ struct ts4800_wdt *wdt = watchdog_get_drvdata(wdd);
+ int i;
+
+ for (i = 0; i < MAX_TIMEOUT_INDEX; i++) {
+ if (ts4800_wdt_map[i].timeout >= timeout)
+ break;
+ }
+
+ wdd->timeout = ts4800_wdt_map[i].timeout;
+ wdt->feed_val = ts4800_wdt_map[i].regval;
+
+ return 0;
+}
+
+static const struct watchdog_ops ts4800_wdt_ops = {
+ .owner = THIS_MODULE,
+ .start = ts4800_wdt_start,
+ .stop = ts4800_wdt_stop,
+ .set_timeout = ts4800_wdt_set_timeout,
+};
+
+static const struct watchdog_info ts4800_wdt_info = {
+ .options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING,
+ .identity = "TS-4800 Watchdog",
+};
+
+static int ts4800_wdt_probe(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ struct device_node *syscon_np;
+ struct watchdog_device *wdd;
+ struct ts4800_wdt *wdt;
+ u32 reg;
+ int ret;
+
+ syscon_np = of_parse_phandle(np, "syscon", 0);
+ if (!syscon_np) {
+ dev_err(&pdev->dev, "no syscon property\n");
+ return -ENODEV;
+ }
+
+ ret = of_property_read_u32_index(np, "syscon", 1, ®);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "no offset in syscon\n");
+ return ret;
+ }
+
+ /* allocate memory for watchdog struct */
+ wdt = devm_kzalloc(&pdev->dev, sizeof(*wdt), GFP_KERNEL);
+ if (!wdt)
+ return -ENOMEM;
+
+ /* set regmap and offset to know where to write */
+ wdt->feed_offset = reg;
+ wdt->regmap = syscon_node_to_regmap(syscon_np);
+ if (IS_ERR(wdt->regmap)) {
+ dev_err(&pdev->dev, "cannot get parent's regmap\n");
+ return PTR_ERR(wdt->regmap);
+ }
+
+ /* Initialize struct watchdog_device */
+ wdd = &wdt->wdd;
+ wdd->parent = &pdev->dev;
+ wdd->info = &ts4800_wdt_info;
+ wdd->ops = &ts4800_wdt_ops;
+ wdd->min_timeout = ts4800_wdt_map[0].timeout;
+ wdd->max_timeout = ts4800_wdt_map[MAX_TIMEOUT_INDEX].timeout;
+
+ watchdog_set_drvdata(wdd, wdt);
+ watchdog_set_nowayout(wdd, nowayout);
+ watchdog_init_timeout(wdd, 0, &pdev->dev);
+
+ /*
+ * As this watchdog supports only a few values, ts4800_wdt_set_timeout
+ * must be called to initialize timeout and feed_val with valid values.
+ * Default to maximum timeout if none, or an invalid one, is provided in
+ * device tree.
+ */
+ if (!wdd->timeout)
+ wdd->timeout = wdd->max_timeout;
+ ts4800_wdt_set_timeout(wdd, wdd->timeout);
+
+ /*
+ * The feed register is write-only, so it is not possible to determine
+ * watchdog's state. Disable it to be in a known state.
+ */
+ ts4800_wdt_stop(wdd);
+
+ ret = watchdog_register_device(wdd);
+ if (ret) {
+ dev_err(&pdev->dev,
+ "failed to register watchdog device\n");
+ return ret;
+ }
+
+ platform_set_drvdata(pdev, wdt);
+
+ dev_info(&pdev->dev,
+ "initialized (timeout = %d sec, nowayout = %d)\n",
+ wdd->timeout, nowayout);
+
+ return 0;
+}
+
+static int ts4800_wdt_remove(struct platform_device *pdev)
+{
+ struct ts4800_wdt *wdt = platform_get_drvdata(pdev);
+
+ watchdog_unregister_device(&wdt->wdd);
+
+ return 0;
+}
+
+static const struct of_device_id ts4800_wdt_of_match[] = {
+ { .compatible = "technologic,ts4800-wdt", },
+ { },
+};
+MODULE_DEVICE_TABLE(of, ts4800_wdt_of_match);
+
+static struct platform_driver ts4800_wdt_driver = {
+ .probe = ts4800_wdt_probe,
+ .remove = ts4800_wdt_remove,
+ .driver = {
+ .name = "ts4800_wdt",
+ .of_match_table = ts4800_wdt_of_match,
+ },
+};
+
+module_platform_driver(ts4800_wdt_driver);
+
+MODULE_AUTHOR("Damien Riegel <[email protected]>");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:ts4800_wdt");
--
2.5.0
The TS-4800, based on an IMX.515, needs its watchdog support in order to
work.
Signed-off-by: Damien Riegel <[email protected]>
---
arch/arm/configs/imx_v6_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index 79194c6..8968166 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -195,6 +195,7 @@ CONFIG_THERMAL=y
CONFIG_CPU_THERMAL=y
CONFIG_IMX_THERMAL=y
CONFIG_WATCHDOG=y
+CONFIG_TS4800_WATCHDOG=y
CONFIG_IMX2_WDT=y
CONFIG_MFD_DA9052_I2C=y
CONFIG_MFD_MC13XXX_SPI=y
--
2.5.0
This device tree adds support for TS-4800 by Technologic Systems. This
board is based on MX51-babbage, but there are some subtle differences in
the pins used, and there is an additional FPGA that is memory-mapped.
More details here:
http://wiki.embeddedarm.com/wiki/TS-4800
Signed-off-by: Damien Riegel <[email protected]>
---
.../devicetree/bindings/arm/technologic.txt | 6 +
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/imx51-ts4800.dts | 190 +++++++++++++++++++++
3 files changed, 198 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/arm/technologic.txt
create mode 100644 arch/arm/boot/dts/imx51-ts4800.dts
diff --git a/Documentation/devicetree/bindings/arm/technologic.txt b/Documentation/devicetree/bindings/arm/technologic.txt
new file mode 100644
index 0000000..8422988
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/technologic.txt
@@ -0,0 +1,6 @@
+Technologic Systems Platforms Device Tree Bindings
+--------------------------------------------------
+
+TS-4800 board
+Required root node properties:
+ - compatible = "technologic,imx51-ts4800", "fsl,imx51";
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index bb8fa02..41b9985 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -258,7 +258,8 @@ dtb-$(CONFIG_SOC_IMX51) += \
imx51-apf51dev.dtb \
imx51-babbage.dtb \
imx51-digi-connectcore-jsk.dtb \
- imx51-eukrea-mbimxsd51-baseboard.dtb
+ imx51-eukrea-mbimxsd51-baseboard.dtb \
+ imx51-ts4800.dtb
dtb-$(CONFIG_SOC_IMX53) += \
imx53-ard.dtb \
imx53-m53evk.dtb \
diff --git a/arch/arm/boot/dts/imx51-ts4800.dts b/arch/arm/boot/dts/imx51-ts4800.dts
new file mode 100644
index 0000000..fac2058
--- /dev/null
+++ b/arch/arm/boot/dts/imx51-ts4800.dts
@@ -0,0 +1,190 @@
+/*
+ * Copyright 2015 Savoir-faire Linux
+ *
+ * This device tree is based on imx51-babbage.dts
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+#include "imx51.dtsi"
+
+/ {
+ model = "Technologic Systems TS-4800";
+ compatible = "technologic,imx51-ts4800", "fsl,imx51";
+
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ memory {
+ reg = <0x90000000 0x10000000>;
+ };
+
+ soc {
+ fpga {
+ compatible = "simple-bus";
+ reg = <0xb0000000 0x1d000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ syscon: syscon@b0010000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0xb0010000 0x3d>;
+ bus-width = <16>;
+
+ wdt@e {
+ compatible = "technologic,ts4800-wdt";
+ syscon = <&syscon 0xe>;
+ };
+ };
+ };
+ };
+
+ clocks {
+ ckih1 {
+ clock-frequency = <22579200>;
+ };
+
+ ckih2 {
+ clock-frequency = <24576000>;
+ };
+ };
+};
+
+&esdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_esdhc1>;
+ cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec>;
+ phy-mode = "mii";
+ phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
+ phy-reset-duration = <1>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+ rtc: m41t00@68 {
+ compatible = "stm,m41t00";
+ reg = <0x68>;
+ };
+};
+
+
+&iomuxc {
+ imx51-ts4800 {
+
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
+ MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
+ MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
+ MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */
+ >;
+ };
+
+ pinctrl_esdhc1: esdhc1grp {
+ fsl,pins = <
+ MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
+ MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
+ MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
+ MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
+ MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
+ MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
+ MX51_PAD_GPIO1_0__GPIO1_0 0x100
+ MX51_PAD_GPIO1_1__GPIO1_1 0x100
+ >;
+ };
+
+ pinctrl_fec: fecgrp {
+ fsl,pins = <
+ MX51_PAD_EIM_EB2__FEC_MDIO 0x000001f5
+ MX51_PAD_EIM_EB3__FEC_RDATA1 0x00000085
+ MX51_PAD_EIM_CS2__FEC_RDATA2 0x00000085
+ MX51_PAD_EIM_CS3__FEC_RDATA3 0x00000085
+ MX51_PAD_EIM_CS4__FEC_RX_ER 0x00000180
+ MX51_PAD_EIM_CS5__FEC_CRS 0x00000180
+ MX51_PAD_DISP2_DAT10__FEC_COL 0x00000180
+ MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x00000180
+ MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x00002180
+ MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x00002004
+ MX51_PAD_NANDF_CS2__FEC_TX_ER 0x00002004
+ MX51_PAD_DI2_PIN2__FEC_MDC 0x00002004
+ MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x00002004
+ MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x00002004
+ MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x00002004
+ MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x00002004
+ MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x00002180
+ MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x000020a4
+ MX51_PAD_EIM_A20__GPIO2_14 0x00000085 /* Phy Reset */
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
+ MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
+ MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
+ MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
+ MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
+ MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX51_PAD_EIM_D25__UART3_RXD 0x1c5
+ MX51_PAD_EIM_D26__UART3_TXD 0x1c5
+ MX51_PAD_EIM_D27__UART3_RTS 0x1c5
+ MX51_PAD_EIM_D24__UART3_CTS 0x1c5
+ >;
+ };
+
+ };
+};
--
2.5.0
On Tue, Nov 24, 2015 at 01:00:51PM -0500, Damien Riegel wrote:
> This watchdog is instantiated in a FPGA that is memory mapped. It is
> made of only one register, called the feed register. Writing to this
> register will re-arm the watchdog for a given time (and enable it if it
> was disable). It can be disabled by writing a special value into it.
>
> It is part of a syscon block, and the watchdog register offset in this
> block varies from board to board. This offset is passed in the syscon
> property after the phandle to the syscon node.
>
> Signed-off-by: Damien Riegel <[email protected]>
Reviewed-by: Guenter Roeck <[email protected]>
On Tue, Nov 24, 2015 at 01:00:53PM -0500, Damien Riegel wrote:
> This device tree adds support for TS-4800 by Technologic Systems. This
> board is based on MX51-babbage, but there are some subtle differences in
> the pins used, and there is an additional FPGA that is memory-mapped.
>
> More details here:
> http://wiki.embeddedarm.com/wiki/TS-4800
>
> Signed-off-by: Damien Riegel <[email protected]>
> ---
> .../devicetree/bindings/arm/technologic.txt | 6 +
Please put binding doc into a separate patch, and have device tree
maintainers and list on copy of that patch.
> arch/arm/boot/dts/Makefile | 3 +-
> arch/arm/boot/dts/imx51-ts4800.dts | 190 +++++++++++++++++++++
> 3 files changed, 198 insertions(+), 1 deletion(-)
> create mode 100644 Documentation/devicetree/bindings/arm/technologic.txt
> create mode 100644 arch/arm/boot/dts/imx51-ts4800.dts
>
> diff --git a/Documentation/devicetree/bindings/arm/technologic.txt b/Documentation/devicetree/bindings/arm/technologic.txt
> new file mode 100644
> index 0000000..8422988
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/technologic.txt
> @@ -0,0 +1,6 @@
> +Technologic Systems Platforms Device Tree Bindings
> +--------------------------------------------------
> +
> +TS-4800 board
> +Required root node properties:
> + - compatible = "technologic,imx51-ts4800", "fsl,imx51";
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index bb8fa02..41b9985 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -258,7 +258,8 @@ dtb-$(CONFIG_SOC_IMX51) += \
> imx51-apf51dev.dtb \
> imx51-babbage.dtb \
> imx51-digi-connectcore-jsk.dtb \
> - imx51-eukrea-mbimxsd51-baseboard.dtb
> + imx51-eukrea-mbimxsd51-baseboard.dtb \
> + imx51-ts4800.dtb
> dtb-$(CONFIG_SOC_IMX53) += \
> imx53-ard.dtb \
> imx53-m53evk.dtb \
> diff --git a/arch/arm/boot/dts/imx51-ts4800.dts b/arch/arm/boot/dts/imx51-ts4800.dts
> new file mode 100644
> index 0000000..fac2058
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx51-ts4800.dts
> @@ -0,0 +1,190 @@
> +/*
> + * Copyright 2015 Savoir-faire Linux
> + *
> + * This device tree is based on imx51-babbage.dts
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +/dts-v1/;
> +#include "imx51.dtsi"
> +
> +/ {
> + model = "Technologic Systems TS-4800";
> + compatible = "technologic,imx51-ts4800", "fsl,imx51";
> +
> + chosen {
> + stdout-path = &uart1;
> + };
> +
> + memory {
> + reg = <0x90000000 0x10000000>;
> + };
> +
> + soc {
> + fpga {
For node with 'reg' property, it should be named in form of
name@unit-adderss.
> + compatible = "simple-bus";
> + reg = <0xb0000000 0x1d000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + syscon: syscon@b0010000 {
> + compatible = "syscon", "simple-mfd";
> + reg = <0xb0010000 0x3d>;
> + bus-width = <16>;
> +
> + wdt@e {
> + compatible = "technologic,ts4800-wdt";
> + syscon = <&syscon 0xe>;
> + };
> + };
> + };
> + };
> +
> + clocks {
> + ckih1 {
> + clock-frequency = <22579200>;
> + };
> +
> + ckih2 {
> + clock-frequency = <24576000>;
> + };
> + };
> +};
> +
> +&esdhc1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_esdhc1>;
> + cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
> + wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
> + status = "okay";
> +};
> +
> +&fec {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_fec>;
> + phy-mode = "mii";
> + phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
> + phy-reset-duration = <1>;
> + status = "okay";
> +};
> +
> +&uart1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart1>;
> + status = "okay";
> +};
> +
> +&uart2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart2>;
> + status = "okay";
> +};
> +
> +&uart3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart3>;
> + status = "okay";
> +};
> +
> +&i2c2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c2>;
> + status = "okay";
> +
> + rtc: m41t00@68 {
> + compatible = "stm,m41t00";
> + reg = <0x68>;
> + };
> +};
We generally sort device nodes alphabetically expect pin controller.
That said, &i2c2 should be put after &fec.
> +
> +
> +&iomuxc {
> + imx51-ts4800 {
With commit 5fcdf6a7ed95 (pinctrl: imx: Allow parsing DT without function
nodes) in place, we should be able to save this level of node.
Shawn
> +
> + pinctrl_ecspi1: ecspi1grp {
> + fsl,pins = <
> + MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
> + MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
> + MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
> + MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */
> + >;
> + };
> +
> + pinctrl_esdhc1: esdhc1grp {
> + fsl,pins = <
> + MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
> + MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
> + MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
> + MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
> + MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
> + MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
> + MX51_PAD_GPIO1_0__GPIO1_0 0x100
> + MX51_PAD_GPIO1_1__GPIO1_1 0x100
> + >;
> + };
> +
> + pinctrl_fec: fecgrp {
> + fsl,pins = <
> + MX51_PAD_EIM_EB2__FEC_MDIO 0x000001f5
> + MX51_PAD_EIM_EB3__FEC_RDATA1 0x00000085
> + MX51_PAD_EIM_CS2__FEC_RDATA2 0x00000085
> + MX51_PAD_EIM_CS3__FEC_RDATA3 0x00000085
> + MX51_PAD_EIM_CS4__FEC_RX_ER 0x00000180
> + MX51_PAD_EIM_CS5__FEC_CRS 0x00000180
> + MX51_PAD_DISP2_DAT10__FEC_COL 0x00000180
> + MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x00000180
> + MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x00002180
> + MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x00002004
> + MX51_PAD_NANDF_CS2__FEC_TX_ER 0x00002004
> + MX51_PAD_DI2_PIN2__FEC_MDC 0x00002004
> + MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x00002004
> + MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x00002004
> + MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x00002004
> + MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x00002004
> + MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x00002180
> + MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x000020a4
> + MX51_PAD_EIM_A20__GPIO2_14 0x00000085 /* Phy Reset */
> + >;
> + };
> +
> + pinctrl_i2c2: i2c2grp {
> + fsl,pins = <
> + MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
> + MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
> + >;
> + };
> +
> + pinctrl_uart1: uart1grp {
> + fsl,pins = <
> + MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
> + MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
> + MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
> + MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
> + >;
> + };
> +
> + pinctrl_uart2: uart2grp {
> + fsl,pins = <
> + MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
> + MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
> + >;
> + };
> +
> + pinctrl_uart3: uart3grp {
> + fsl,pins = <
> + MX51_PAD_EIM_D25__UART3_RXD 0x1c5
> + MX51_PAD_EIM_D26__UART3_TXD 0x1c5
> + MX51_PAD_EIM_D27__UART3_RTS 0x1c5
> + MX51_PAD_EIM_D24__UART3_CTS 0x1c5
> + >;
> + };
> +
> + };
> +};
> --
> 2.5.0
>
>