Hi,
This mini-series came out as a result of discussions during EZChip platform
code review.
This switches ARC timers to DT based probe and removes the homebrew clk API
we had before.
@Rob could you please take a look at the DT bindings.
@Daniel any comments would be appreciated !
Thx,
-Vineet
changes since v1:
- Primarily timer0/timer1 folded into one (more details in respective patches)
[v1]
http://lists.infradead.org/pipermail/linux-snps-arc/2016-February/000445.html
Alexey Brodkin (3):
ARC: use fixed frequencies in arc_set_early_base_baud()
ARC: [plat-axs] Don't use arc_{get|set}_core_freq() for manipulating
core clk
ARC: RIP arc_{get|set}_core_freq() clk API
Noam Camus (2):
ARC: clockevent: switch to cpu notifier for clockevent setup
ARC: clockevent: Prepare for DT based probe
Vineet Gupta (4):
ARC: [dts] Add clk feeding into timers to DTs
ARC: [dts] Introduce Timer bindings
ARC: clockevent: DT based probe
ARC: clocksource: DT based probe
.../devicetree/bindings/timer/snps,arc-timer.txt | 26 +++
.../devicetree/bindings/timer/snps,archs-gfrc.txt | 14 ++
.../devicetree/bindings/timer/snps,archs-rtc.txt | 14 ++
arch/arc/Kconfig | 3 +-
arch/arc/boot/dts/abilis_tb10x.dtsi | 14 ++
arch/arc/boot/dts/axc001.dtsi | 6 +
arch/arc/boot/dts/axc003.dtsi | 6 +
arch/arc/boot/dts/axc003_idu.dtsi | 6 +
arch/arc/boot/dts/nsim_700.dts | 6 +
arch/arc/boot/dts/nsim_hs.dts | 6 +
arch/arc/boot/dts/nsim_hs_idu.dts | 6 +
arch/arc/boot/dts/nsimosci.dts | 6 +
arch/arc/boot/dts/nsimosci_hs.dts | 6 +
arch/arc/boot/dts/nsimosci_hs_idu.dts | 6 +
arch/arc/boot/dts/skeleton.dtsi | 14 ++
arch/arc/boot/dts/skeleton_hs.dtsi | 20 ++
arch/arc/boot/dts/skeleton_hs_idu.dtsi | 14 ++
arch/arc/boot/dts/vdk_axc003.dtsi | 6 +
arch/arc/boot/dts/vdk_axc003_idu.dtsi | 6 +
arch/arc/include/asm/clk.h | 22 --
arch/arc/include/asm/irq.h | 10 -
arch/arc/kernel/Makefile | 2 +-
arch/arc/kernel/clk.c | 21 --
arch/arc/kernel/devtree.c | 13 +-
arch/arc/kernel/intc-compact.c | 2 +
arch/arc/kernel/mcip.c | 4 +-
arch/arc/kernel/setup.c | 17 +-
arch/arc/kernel/smp.c | 2 -
arch/arc/kernel/time.c | 224 +++++++++++++--------
arch/arc/plat-axs10x/axs10x.c | 27 ++-
30 files changed, 361 insertions(+), 168 deletions(-)
create mode 100644 Documentation/devicetree/bindings/timer/snps,arc-timer.txt
create mode 100644 Documentation/devicetree/bindings/timer/snps,archs-gfrc.txt
create mode 100644 Documentation/devicetree/bindings/timer/snps,archs-rtc.txt
delete mode 100644 arch/arc/include/asm/clk.h
delete mode 100644 arch/arc/kernel/clk.c
--
2.5.0
This allows us to introduce timers in DT in next commit
Cc: Daniel Lezcano <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: [email protected]
Signed-off-by: Vineet Gupta <[email protected]>
---
arch/arc/boot/dts/axc001.dtsi | 6 ++++++
arch/arc/boot/dts/axc003.dtsi | 6 ++++++
arch/arc/boot/dts/axc003_idu.dtsi | 6 ++++++
arch/arc/boot/dts/nsim_700.dts | 6 ++++++
arch/arc/boot/dts/nsim_hs.dts | 6 ++++++
arch/arc/boot/dts/nsim_hs_idu.dts | 6 ++++++
arch/arc/boot/dts/nsimosci.dts | 6 ++++++
arch/arc/boot/dts/nsimosci_hs.dts | 6 ++++++
arch/arc/boot/dts/nsimosci_hs_idu.dts | 6 ++++++
arch/arc/boot/dts/vdk_axc003.dtsi | 6 ++++++
arch/arc/boot/dts/vdk_axc003_idu.dtsi | 6 ++++++
11 files changed, 66 insertions(+)
diff --git a/arch/arc/boot/dts/axc001.dtsi b/arch/arc/boot/dts/axc001.dtsi
index e7a83d19c5a3..40bcecfc3687 100644
--- a/arch/arc/boot/dts/axc001.dtsi
+++ b/arch/arc/boot/dts/axc001.dtsi
@@ -26,6 +26,12 @@
ranges = <0x00000000 0xf0000000 0x10000000>;
+ core_clk: core_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <750000000>;
+ };
+
core_intc: arc700-intc@cpu {
compatible = "snps,arc700-intc";
interrupt-controller;
diff --git a/arch/arc/boot/dts/axc003.dtsi b/arch/arc/boot/dts/axc003.dtsi
index b0e3ccdf8fc7..cabe0deeb2d8 100644
--- a/arch/arc/boot/dts/axc003.dtsi
+++ b/arch/arc/boot/dts/axc003.dtsi
@@ -25,6 +25,12 @@
ranges = <0x00000000 0xf0000000 0x10000000>;
+ core_clk: core_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <90000000>;
+ };
+
core_intc: archs-intc@cpu {
compatible = "snps,archs-intc";
interrupt-controller;
diff --git a/arch/arc/boot/dts/axc003_idu.dtsi b/arch/arc/boot/dts/axc003_idu.dtsi
index f87ae409c8ed..8955881db794 100644
--- a/arch/arc/boot/dts/axc003_idu.dtsi
+++ b/arch/arc/boot/dts/axc003_idu.dtsi
@@ -25,6 +25,12 @@
ranges = <0x00000000 0xf0000000 0x10000000>;
+ core_clk: core_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <90000000>;
+ };
+
core_intc: archs-intc@cpu {
compatible = "snps,archs-intc";
interrupt-controller;
diff --git a/arch/arc/boot/dts/nsim_700.dts b/arch/arc/boot/dts/nsim_700.dts
index 987921f711c1..5d5e373e0ebc 100644
--- a/arch/arc/boot/dts/nsim_700.dts
+++ b/arch/arc/boot/dts/nsim_700.dts
@@ -32,6 +32,12 @@
/* child and parent address space 1:1 mapped */
ranges;
+ core_clk: core_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <80000000>;
+ };
+
core_intc: interrupt-controller {
compatible = "snps,arc700-intc";
interrupt-controller;
diff --git a/arch/arc/boot/dts/nsim_hs.dts b/arch/arc/boot/dts/nsim_hs.dts
index bd46aec88c6a..cbd08fa38339 100644
--- a/arch/arc/boot/dts/nsim_hs.dts
+++ b/arch/arc/boot/dts/nsim_hs.dts
@@ -38,6 +38,12 @@
/* only perip space at end of low mem accessible */
ranges = <0x80000000 0x0 0x80000000 0x80000000>;
+ core_clk: core_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <80000000>;
+ };
+
core_intc: core-interrupt-controller {
compatible = "snps,archs-intc";
interrupt-controller;
diff --git a/arch/arc/boot/dts/nsim_hs_idu.dts b/arch/arc/boot/dts/nsim_hs_idu.dts
index cc82781727a1..99eabe1a2bf6 100644
--- a/arch/arc/boot/dts/nsim_hs_idu.dts
+++ b/arch/arc/boot/dts/nsim_hs_idu.dts
@@ -29,6 +29,12 @@
/* child and parent address space 1:1 mapped */
ranges;
+ core_clk: core_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <80000000>;
+ };
+
core_intc: core-interrupt-controller {
compatible = "snps,archs-intc";
interrupt-controller;
diff --git a/arch/arc/boot/dts/nsimosci.dts b/arch/arc/boot/dts/nsimosci.dts
index 1c169dc74ad1..bc3161ab8f82 100644
--- a/arch/arc/boot/dts/nsimosci.dts
+++ b/arch/arc/boot/dts/nsimosci.dts
@@ -35,6 +35,12 @@
/* child and parent address space 1:1 mapped */
ranges;
+ core_clk: core_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <20000000>;
+ };
+
intc: interrupt-controller {
compatible = "snps,arc700-intc";
interrupt-controller;
diff --git a/arch/arc/boot/dts/nsimosci_hs.dts b/arch/arc/boot/dts/nsimosci_hs.dts
index 9444956156d9..273dcce2cc66 100644
--- a/arch/arc/boot/dts/nsimosci_hs.dts
+++ b/arch/arc/boot/dts/nsimosci_hs.dts
@@ -35,6 +35,12 @@
/* child and parent address space 1:1 mapped */
ranges;
+ core_clk: core_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <20000000>;
+ };
+
core_intc: core-interrupt-controller {
compatible = "snps,archs-intc";
interrupt-controller;
diff --git a/arch/arc/boot/dts/nsimosci_hs_idu.dts b/arch/arc/boot/dts/nsimosci_hs_idu.dts
index ff11388ee484..8fe60967a4c5 100644
--- a/arch/arc/boot/dts/nsimosci_hs_idu.dts
+++ b/arch/arc/boot/dts/nsimosci_hs_idu.dts
@@ -33,6 +33,12 @@
/* child and parent address space 1:1 mapped */
ranges;
+ core_clk: core_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <5000000>;
+ };
+
core_intc: core-interrupt-controller {
compatible = "snps,archs-intc";
interrupt-controller;
diff --git a/arch/arc/boot/dts/vdk_axc003.dtsi b/arch/arc/boot/dts/vdk_axc003.dtsi
index 035759ee62a5..ad4ee43bd2ac 100644
--- a/arch/arc/boot/dts/vdk_axc003.dtsi
+++ b/arch/arc/boot/dts/vdk_axc003.dtsi
@@ -25,6 +25,12 @@
ranges = <0x00000000 0xf0000000 0x10000000>;
+ core_clk: core_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ };
+
core_intc: archs-intc@cpu {
compatible = "snps,archs-intc";
interrupt-controller;
diff --git a/arch/arc/boot/dts/vdk_axc003_idu.dtsi b/arch/arc/boot/dts/vdk_axc003_idu.dtsi
index 90e18f404889..a3cb6263c581 100644
--- a/arch/arc/boot/dts/vdk_axc003_idu.dtsi
+++ b/arch/arc/boot/dts/vdk_axc003_idu.dtsi
@@ -26,6 +26,12 @@
ranges = <0x00000000 0xf0000000 0x10000000>;
+ core_clk: core_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ };
+
core_intc: archs-intc@cpu {
compatible = "snps,archs-intc";
interrupt-controller;
--
2.5.0
ARC Timers have historically been probed directly.
As precursor to start probing Timers thru DT introduce these bindings
Note that to keep series bisectable, these bindings are not yet used in
code.
Cc: Daniel Lezcano <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: [email protected]
Signed-off-by: Vineet Gupta <[email protected]>
---
Changes v1 -> v2
- snps,arc-timer[0-1] folded into single snps-arc-timer [Rob]
- Node name in DT example fixed: [Rob]
"timer1: timer_clksrc {" -> timer@1 {
- Introduced 64bit RTC in skeleton_hs.dtsi [Vineet]
v1:
- http://lists.infradead.org/pipermail/linux-snps-arc/2016-February/000447.html
Signed-off-by: Vineet Gupta <[email protected]>
---
.../devicetree/bindings/timer/snps,arc-timer.txt | 26 ++++++++++++++++++++++
.../devicetree/bindings/timer/snps,archs-gfrc.txt | 14 ++++++++++++
.../devicetree/bindings/timer/snps,archs-rtc.txt | 14 ++++++++++++
arch/arc/boot/dts/abilis_tb10x.dtsi | 14 ++++++++++++
arch/arc/boot/dts/skeleton.dtsi | 14 ++++++++++++
arch/arc/boot/dts/skeleton_hs.dtsi | 20 +++++++++++++++++
arch/arc/boot/dts/skeleton_hs_idu.dtsi | 14 ++++++++++++
7 files changed, 116 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/snps,arc-timer.txt
create mode 100644 Documentation/devicetree/bindings/timer/snps,archs-gfrc.txt
create mode 100644 Documentation/devicetree/bindings/timer/snps,archs-rtc.txt
diff --git a/Documentation/devicetree/bindings/timer/snps,arc-timer.txt b/Documentation/devicetree/bindings/timer/snps,arc-timer.txt
new file mode 100644
index 000000000000..9e02be24e805
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/snps,arc-timer.txt
@@ -0,0 +1,26 @@
+Synopsys ARC Local Timer with Interrupt Capabilities
+- Found on all ARC CPUs (ARC700/ARCHS)
+- Can be optionally programmed to interrupt on Limit
+- Two idential copies TIMER0 and TIMER1 exist in ARC cores and historically
+ TIMER0 used as clockevent provider (true for all ARC cores)
+ TIMER1 used for clocksource (mandatory for ARC700, optional for ARC HS)
+
+Required properties:
+
+- compatible : should be "snps,arc-timer"
+- interrupts : single Interrupt going into parent intc
+ (16 for ARCHS cores, 3 for ARC700 cores)
+- clocks : phandle to the source clock
+
+Optional properties:
+
+- interrupt-parent : phandle to parent intc
+
+Example:
+
+ timer@0 {
+ compatible = "snps,arc-timer0";
+ interrupts = <3>;
+ interrupt-parent = <&core_intc>;
+ clocks = <&core_clk>;
+ };
diff --git a/Documentation/devicetree/bindings/timer/snps,archs-gfrc.txt b/Documentation/devicetree/bindings/timer/snps,archs-gfrc.txt
new file mode 100644
index 000000000000..aaab100f54e7
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/snps,archs-gfrc.txt
@@ -0,0 +1,14 @@
+Synopsys ARC Free Running 64-bit Global Timer for ARC HS CPUs
+- clocksource provider for SMP SoC
+
+Required properties:
+
+- compatible : should be "snps,archs-gfrc"
+- clocks : phandle to the source clock
+
+Example:
+
+ timer@1 {
+ compatible = "snps,archs-gfrc";
+ clocks = <&core_clk>;
+ };
diff --git a/Documentation/devicetree/bindings/timer/snps,archs-rtc.txt b/Documentation/devicetree/bindings/timer/snps,archs-rtc.txt
new file mode 100644
index 000000000000..13f756fa1d6d
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/snps,archs-rtc.txt
@@ -0,0 +1,14 @@
+Synopsys ARC Free Running 64-bit Local Timer for ARC HS CPUs
+- clocksource provider for UP SoC
+
+Required properties:
+
+- compatible : should be "snps,archs-rtc"
+- clocks : phandle to the source clock
+
+Example:
+
+ timer@1 {
+ compatible = "snps,arc-rtc";
+ clocks = <&core_clk>;
+ };
diff --git a/arch/arc/boot/dts/abilis_tb10x.dtsi b/arch/arc/boot/dts/abilis_tb10x.dtsi
index cfb5052239a1..eadbe71dfa22 100644
--- a/arch/arc/boot/dts/abilis_tb10x.dtsi
+++ b/arch/arc/boot/dts/abilis_tb10x.dtsi
@@ -35,6 +35,20 @@
};
};
+ /* TIMER0 with interrupt for clockevent */
+ timer@0 {
+ compatible = "snps,arc-timer";
+ interrupts = <3>;
+ interrupt-parent = <&intc>;
+ clocks = <&cpu_clk>;
+ };
+
+ /* TIMER1 for free running clocksource */
+ timer@1 {
+ compatible = "snps,arc-timer";
+ clocks = <&cpu_clk>;
+ };
+
soc100 {
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/arc/boot/dts/skeleton.dtsi b/arch/arc/boot/dts/skeleton.dtsi
index 296d371a335c..f6109c2feba7 100644
--- a/arch/arc/boot/dts/skeleton.dtsi
+++ b/arch/arc/boot/dts/skeleton.dtsi
@@ -30,6 +30,20 @@
};
};
+ /* TIMER0 with interrupt for clockevent */
+ timer@0 {
+ compatible = "snps,arc-timer";
+ interrupts = <3>;
+ interrupt-parent = <&core_intc>;
+ clocks = <&core_clk>;
+ };
+
+ /* TIMER1 for free running clocksource */
+ timer@1 {
+ compatible = "snps,arc-timer";
+ clocks = <&core_clk>;
+ };
+
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>; /* 256M */
diff --git a/arch/arc/boot/dts/skeleton_hs.dtsi b/arch/arc/boot/dts/skeleton_hs.dtsi
index a53876669030..49caeabca37a 100644
--- a/arch/arc/boot/dts/skeleton_hs.dtsi
+++ b/arch/arc/boot/dts/skeleton_hs.dtsi
@@ -25,6 +25,26 @@
};
};
+ /* TIMER0 with interrupt for clockevent */
+ timer@0 {
+ compatible = "snps,arc-timer";
+ interrupts = <16>;
+ interrupt-parent = <&core_intc>;
+ clocks = <&core_clk>;
+ };
+
+ /* 64-bit Local RTC: preferred clocksource for UP */
+ timer@1 {
+ compatible = "snps,archs-timer-rtc";
+ clocks = <&core_clk>;
+ };
+
+ /* TIMER1 for free running clocksource: Fallback if rtc not found */
+ timer@2 {
+ compatible = "snps,arc-timer";
+ clocks = <&core_clk>;
+ };
+
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>; /* 256M */
diff --git a/arch/arc/boot/dts/skeleton_hs_idu.dtsi b/arch/arc/boot/dts/skeleton_hs_idu.dtsi
index 74898d017f7a..7e301ff16200 100644
--- a/arch/arc/boot/dts/skeleton_hs_idu.dtsi
+++ b/arch/arc/boot/dts/skeleton_hs_idu.dtsi
@@ -25,6 +25,20 @@
};
};
+ /* TIMER0 with interrupt for clockevent */
+ timer@0 {
+ compatible = "snps,arc-timer";
+ interrupts = <16>;
+ interrupt-parent = <&core_intc>;
+ clocks = <&core_clk>;
+ };
+
+ /* 64-bit Global Free Running Counter */
+ timer@1 {
+ compatible = "snps,archs-timer-gfrc";
+ clocks = <&core_clk>;
+ };
+
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>; /* 256M */
--
2.5.0
From: Noam Camus <[email protected]>
ARC Timers so far have been handled as "legacy" w/o explicit description
in DT. This poses challenge for newer platforms wanting to use them.
This series will eventually help move timers over to DT.
This patch does a small change of using a CPU notifier to set clockevent
on non-boot CPUs. So explicit setup is done only on boot CPU (which will
later be done by DT)
Cc: Daniel Lezcano <[email protected]>
Signed-off-by: Noam Camus <[email protected]>
[vgupta: broken off from a bigger patch]
Signed-off-by: Vineet Gupta <[email protected]>
---
Changes v1 -> v2
- Rebased on 4.5-rc6 (some changes due to interim changes)
- Reduced the extraneous header includes
- Fixed @ret handling in arc_clockevent_setup()
- Fix snafu in a adapting patch from EZChip tree:
nps_timer_cpu_nb -> arc_timer_cpu_nb
v1:
- http://lists.infradead.org/pipermail/linux-snps-arc/2016-February/000454.html
Signed-off-by: Vineet Gupta <[email protected]>
---
arch/arc/include/asm/irq.h | 1 -
arch/arc/kernel/smp.c | 2 --
arch/arc/kernel/time.c | 62 ++++++++++++++++++++++++++++++----------------
3 files changed, 41 insertions(+), 24 deletions(-)
diff --git a/arch/arc/include/asm/irq.h b/arch/arc/include/asm/irq.h
index f9c735ede4fc..5c0b5abda67a 100644
--- a/arch/arc/include/asm/irq.h
+++ b/arch/arc/include/asm/irq.h
@@ -25,6 +25,5 @@
#include <asm-generic/irq.h>
extern void arc_init_IRQ(void);
-void arc_local_timer_setup(void);
#endif
diff --git a/arch/arc/kernel/smp.c b/arch/arc/kernel/smp.c
index 96cb0d8887e5..74e7ce4c1508 100644
--- a/arch/arc/kernel/smp.c
+++ b/arch/arc/kernel/smp.c
@@ -138,8 +138,6 @@ void start_kernel_secondary(void)
if (machine_desc->init_per_cpu)
machine_desc->init_per_cpu(cpu);
- arc_local_timer_setup();
-
local_irq_enable();
preempt_disable();
cpu_startup_entry(CPUHP_ONLINE);
diff --git a/arch/arc/kernel/time.c b/arch/arc/kernel/time.c
index 146da3cbcc99..e97be743d47b 100644
--- a/arch/arc/kernel/time.c
+++ b/arch/arc/kernel/time.c
@@ -29,17 +29,14 @@
* which however is currently broken
*/
-#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/module.h>
-#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/time.h>
#include <linux/init.h>
-#include <linux/timex.h>
-#include <linux/profile.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
+#include <linux/cpu.h>
#include <asm/irq.h>
#include <asm/arcregs.h>
#include <asm/clk.h>
@@ -183,6 +180,8 @@ static struct clocksource arc_counter = {
/********** Clock Event Device *********/
+static int arc_timer_irq = TIMER0_IRQ;
+
/*
* Arm the timer to interrupt after @cycles
* The distinction for oneshot/periodic is done in arc_event_timer_ack() below
@@ -218,7 +217,6 @@ static DEFINE_PER_CPU(struct clock_event_device, arc_clockevent_device) = {
.features = CLOCK_EVT_FEAT_ONESHOT |
CLOCK_EVT_FEAT_PERIODIC,
.rating = 300,
- .irq = TIMER0_IRQ, /* hardwired, no need for resources */
.set_next_event = arc_clkevent_set_next_event,
.set_state_periodic = arc_clkevent_set_periodic,
};
@@ -244,29 +242,52 @@ static irqreturn_t timer_irq_handler(int irq, void *dev_id)
return IRQ_HANDLED;
}
+static int arc_timer_cpu_notify(struct notifier_block *self,
+ unsigned long action, void *hcpu)
+{
+ struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device);
+
+ evt->cpumask = cpumask_of(smp_processor_id());
+
+ switch (action & ~CPU_TASKS_FROZEN) {
+ case CPU_STARTING:
+ clockevents_config_and_register(evt, arc_get_core_freq(),
+ 0, ULONG_MAX);
+ enable_percpu_irq(arc_timer_irq, 0);
+ break;
+ case CPU_DYING:
+ disable_percpu_irq(arc_timer_irq);
+ break;
+ }
+
+ return NOTIFY_OK;
+}
+
+static struct notifier_block arc_timer_cpu_nb = {
+ .notifier_call = arc_timer_cpu_notify,
+};
+
/*
- * Setup the local event timer for @cpu
+ * clockevent setup for boot CPU
*/
-void arc_local_timer_setup()
+static void __init arc_clockevent_setup(void)
{
struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device);
- int cpu = smp_processor_id();
- int irq = TIMER0_IRQ;
+ int ret;
- evt->cpumask = cpumask_of(cpu);
+ register_cpu_notifier(&arc_timer_cpu_nb);
+
+ evt->cpumask = cpumask_of(smp_processor_id());
clockevents_config_and_register(evt, arc_get_core_freq(),
0, ARC_TIMER_MAX);
- if (!cpu) {
- int rc;
-
- rc = request_percpu_irq(irq, timer_irq_handler,
- "Timer0 (per-cpu-tick)", evt);
- if (rc)
- panic("Percpu IRQ request failed for TIMER\n");
- }
+ /* Needs apriori irq_set_percpu_devid() done in intc map function */
+ ret = request_percpu_irq(arc_timer_irq, timer_irq_handler,
+ "Timer0 (per-cpu-tick)", evt);
+ if (ret)
+ pr_err("Unable to register interrupt\n");
- enable_percpu_irq(irq, 0);
+ enable_percpu_irq(arc_timer_irq, 0);
}
/*
@@ -291,6 +312,5 @@ void __init time_init(void)
*/
clocksource_register_hz(&arc_counter, arc_get_core_freq());
- /* sets up the periodic event timer */
- arc_local_timer_setup();
+ arc_clockevent_setup();
}
--
2.5.0
- timer frequency is derived from DT (no longer rely on top level
DT "clock-frequency" probed early and exported by asm/clk.h)
- TIMER0_IRQ need not be exported across arch code, confided to intc as
it is property of same
Cc: Noam Camus <[email protected]>
Cc: Daniel Lezcano <[email protected]>
Signed-off-by: Vineet Gupta <[email protected]>
---
Changes v1 -> v2
- Rebased on 4.5-rc6
- Fix snafu in a adapting patch from EZChip tree
v1:
- http://lists.infradead.org/pipermail/linux-snps-arc/2016-February/000449.html
Signed-off-by: Vineet Gupta <[email protected]>
---
arch/arc/include/asm/irq.h | 9 --------
arch/arc/kernel/intc-compact.c | 2 ++
arch/arc/kernel/time.c | 49 +++++++++++++++++++++++++++++-------------
3 files changed, 36 insertions(+), 24 deletions(-)
diff --git a/arch/arc/include/asm/irq.h b/arch/arc/include/asm/irq.h
index 5c0b5abda67a..a6ac89dc228f 100644
--- a/arch/arc/include/asm/irq.h
+++ b/arch/arc/include/asm/irq.h
@@ -12,15 +12,6 @@
#define NR_CPU_IRQS 32 /* number of interrupt lines of ARC770 CPU */
#define NR_IRQS 128 /* allow some CPU external IRQ handling */
-/* Platform Independent IRQs */
-#ifdef CONFIG_ISA_ARCOMPACT
-#define TIMER0_IRQ 3
-#define TIMER1_IRQ 4
-#else
-#define TIMER0_IRQ 16
-#define TIMER1_IRQ 17
-#endif
-
#include <linux/interrupt.h>
#include <asm-generic/irq.h>
diff --git a/arch/arc/kernel/intc-compact.c b/arch/arc/kernel/intc-compact.c
index 4195eedeb6d1..d31bc647146d 100644
--- a/arch/arc/kernel/intc-compact.c
+++ b/arch/arc/kernel/intc-compact.c
@@ -14,6 +14,8 @@
#include <linux/irqchip.h>
#include <asm/irq.h>
+#define TIMER0_IRQ 3 /* Fixed by ISA */
+
/*
* Early Hardware specific Interrupt setup
* -Platform independent, needed for each CPU (not foldable into init_IRQ)
diff --git a/arch/arc/kernel/time.c b/arch/arc/kernel/time.c
index 848353a27ac8..693545df9827 100644
--- a/arch/arc/kernel/time.c
+++ b/arch/arc/kernel/time.c
@@ -30,19 +30,15 @@
*/
#include <linux/interrupt.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/time.h>
-#include <linux/init.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/cpu.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
#include <asm/irq.h>
#include <asm/arcregs.h>
-#include <asm/clk.h>
-#include <asm/mach_desc.h>
#include <asm/mcip.h>
@@ -59,6 +55,24 @@
#define ARC_TIMER_MAX 0xFFFFFFFF
+static unsigned long arc_timer_freq;
+
+static void noinline arc_get_timer_clk(struct device_node *node)
+{
+ struct clk *clk;
+ int ret;
+
+ clk = of_clk_get(node, 0);
+ if (IS_ERR(clk))
+ panic("Can't get timer clock");
+
+ ret = clk_prepare_enable(clk);
+ if (ret)
+ pr_err("Couldn't enable parent clock\n");
+
+ arc_timer_freq = clk_get_rate(clk);
+}
+
/********** Clock Source Device *********/
#ifdef CONFIG_ARC_HAS_GFRC
@@ -182,7 +196,7 @@ static struct clocksource arc_counter = {
/********** Clock Event Device *********/
-static int arc_timer_irq = TIMER0_IRQ;
+static int arc_timer_irq;
/*
* Arm the timer to interrupt after @cycles
@@ -210,7 +224,7 @@ static int arc_clkevent_set_periodic(struct clock_event_device *dev)
* At X Hz, 1 sec = 1000ms -> X cycles;
* 10ms -> X / 100 cycles
*/
- arc_timer_event_setup(arc_get_core_freq() / HZ);
+ arc_timer_event_setup(arc_timer_freq / HZ);
return 0;
}
@@ -253,7 +267,7 @@ static int arc_timer_cpu_notify(struct notifier_block *self,
switch (action & ~CPU_TASKS_FROZEN) {
case CPU_STARTING:
- clockevents_config_and_register(evt, arc_get_core_freq(),
+ clockevents_config_and_register(evt, arc_timer_freq,
0, ULONG_MAX);
enable_percpu_irq(arc_timer_irq, 0);
break;
@@ -272,15 +286,22 @@ static struct notifier_block arc_timer_cpu_nb = {
/*
* clockevent setup for boot CPU
*/
-static void __init arc_clockevent_setup(void)
+static void __init arc_clockevent_setup(struct device_node *node)
{
struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device);
int ret;
register_cpu_notifier(&arc_timer_cpu_nb);
+ arc_timer_irq = irq_of_parse_and_map(node, 0);
+ if (arc_timer_irq <= 0)
+ panic("Can't parse IRQ");
+
+ arc_get_timer_clk(node);
+
+ evt->irq = arc_timer_irq;
evt->cpumask = cpumask_of(smp_processor_id());
- clockevents_config_and_register(evt, arc_get_core_freq(),
+ clockevents_config_and_register(evt, arc_timer_freq,
0, ARC_TIMER_MAX);
/* Needs apriori irq_set_percpu_devid() done in intc map function */
@@ -291,6 +312,7 @@ static void __init arc_clockevent_setup(void)
enable_percpu_irq(arc_timer_irq, 0);
}
+CLOCKSOURCE_OF_DECLARE(arc_clkevt, "snps,arc-timer", arc_clockevent_setup);
/*
* Called from start_kernel() - boot CPU only
@@ -299,7 +321,6 @@ static void __init arc_clockevent_setup(void)
* -Also sets up any global state needed for timer subsystem:
* - for "counting" timer, registers a clocksource, usable across CPUs
* (provided that underlying counter h/w is synchronized across cores)
- * - for "event" timer, sets up TIMER0 IRQ (as that is platform agnostic)
*/
void __init time_init(void)
{
@@ -315,7 +336,5 @@ void __init time_init(void)
* CLK upto 4.29 GHz can be safely represented in 32 bits
* because Max 32 bit number is 4,294,967,295
*/
- clocksource_register_hz(&arc_counter, arc_get_core_freq());
-
- arc_clockevent_setup();
+ clocksource_register_hz(&arc_counter, arc_timer_freq);
}
--
2.5.0
From: Alexey Brodkin <[email protected]>
UARTs usually have fixed clock so we're switching to use of
constant values instead of something derived from core clock
frequency.
Among other things this will allow us to get rid of
arc_{get|set}_core_freq() and switch to generic clock
framework later on.
Cc: Christian Ruppert <[email protected]>
Signed-off-by: Alexey Brodkin <[email protected]>
Signed-off-by: Vineet Gupta <[email protected]>
---
Changes v1 -> v2
- Base baud TB10x needs to be 166.66 not 166.67 [Christian]
v1:
- http://lists.infradead.org/pipermail/linux-snps-arc/2016-February/000453.html
Signed-off-by: Vineet Gupta <[email protected]>
---
arch/arc/kernel/devtree.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/arch/arc/kernel/devtree.c b/arch/arc/kernel/devtree.c
index 7e844fd8213f..fecbc96df828 100644
--- a/arch/arc/kernel/devtree.c
+++ b/arch/arc/kernel/devtree.c
@@ -28,14 +28,12 @@ unsigned int __init arc_early_base_baud(void)
static void __init arc_set_early_base_baud(unsigned long dt_root)
{
- unsigned int core_clk = arc_get_core_freq();
-
if (of_flat_dt_is_compatible(dt_root, "abilis,arc-tb10x"))
- arc_base_baud = core_clk/3;
+ arc_base_baud = 166666666; /* Fixed 166.6MHz clk (TB10x) */
else if (of_flat_dt_is_compatible(dt_root, "snps,arc-sdp"))
arc_base_baud = 33333333; /* Fixed 33MHz clk (AXS10x) */
else
- arc_base_baud = core_clk;
+ arc_base_baud = 50000000; /* Fixed default 50MHz */
}
#else
#define arc_set_early_base_baud(dt_root)
--
2.5.0
From: Alexey Brodkin <[email protected]>
There are no more users of this - so RIP!
Signed-off-by: Alexey Brodkin <[email protected]>
[vgupta: update changelog]
Signed-off-by: Vineet Gupta <[email protected]>
Signed-off-by: Vineet Gupta <[email protected]>
---
arch/arc/include/asm/clk.h | 22 ----------------------
arch/arc/kernel/Makefile | 2 +-
arch/arc/kernel/clk.c | 21 ---------------------
arch/arc/kernel/devtree.c | 7 -------
4 files changed, 1 insertion(+), 51 deletions(-)
delete mode 100644 arch/arc/include/asm/clk.h
delete mode 100644 arch/arc/kernel/clk.c
diff --git a/arch/arc/include/asm/clk.h b/arch/arc/include/asm/clk.h
deleted file mode 100644
index bf9d29f5bd53..000000000000
--- a/arch/arc/include/asm/clk.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright (C) 2012 Synopsys, Inc. (http://www.synopsys.com)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef _ASM_ARC_CLK_H
-#define _ASM_ARC_CLK_H
-
-/* Although we can't really hide core_freq, the accessor is still better way */
-extern unsigned long core_freq;
-
-static inline unsigned long arc_get_core_freq(void)
-{
- return core_freq;
-}
-
-extern int arc_set_core_freq(unsigned long);
-
-#endif
diff --git a/arch/arc/kernel/Makefile b/arch/arc/kernel/Makefile
index e7f3625a19b5..4f16967a0871 100644
--- a/arch/arc/kernel/Makefile
+++ b/arch/arc/kernel/Makefile
@@ -9,7 +9,7 @@
CFLAGS_ptrace.o += -DUTS_MACHINE='"$(UTS_MACHINE)"'
obj-y := arcksyms.o setup.o irq.o time.o reset.o ptrace.o process.o devtree.o
-obj-y += signal.o traps.o sys.o troubleshoot.o stacktrace.o disasm.o clk.o
+obj-y += signal.o traps.o sys.o troubleshoot.o stacktrace.o disasm.o
obj-$(CONFIG_ISA_ARCOMPACT) += entry-compact.o intc-compact.o
obj-$(CONFIG_ISA_ARCV2) += entry-arcv2.o intc-arcv2.o
diff --git a/arch/arc/kernel/clk.c b/arch/arc/kernel/clk.c
deleted file mode 100644
index 10c7b0b5a079..000000000000
--- a/arch/arc/kernel/clk.c
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * Copyright (C) 2012 Synopsys, Inc. (http://www.synopsys.com)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <asm/clk.h>
-
-unsigned long core_freq = 80000000;
-
-/*
- * As of now we default to device-tree provided clock
- * In future we can determine this in early boot
- */
-int arc_set_core_freq(unsigned long freq)
-{
- core_freq = freq;
- return 0;
-}
diff --git a/arch/arc/kernel/devtree.c b/arch/arc/kernel/devtree.c
index fecbc96df828..f1e07c2344f8 100644
--- a/arch/arc/kernel/devtree.c
+++ b/arch/arc/kernel/devtree.c
@@ -14,7 +14,6 @@
#include <linux/memblock.h>
#include <linux/of.h>
#include <linux/of_fdt.h>
-#include <asm/clk.h>
#include <asm/mach_desc.h>
#ifdef CONFIG_SERIAL_EARLYCON
@@ -63,8 +62,6 @@ const struct machine_desc * __init setup_machine_fdt(void *dt)
{
const struct machine_desc *mdesc;
unsigned long dt_root;
- const void *clk;
- int len;
if (!early_init_dt_scan(dt))
return NULL;
@@ -74,10 +71,6 @@ const struct machine_desc * __init setup_machine_fdt(void *dt)
machine_halt();
dt_root = of_get_flat_dt_root();
- clk = of_get_flat_dt_prop(dt_root, "clock-frequency", &len);
- if (clk)
- arc_set_core_freq(of_read_ulong(clk, len/4));
-
arc_set_early_base_baud(dt_root);
return mdesc;
--
2.5.0
From: Noam Camus <[email protected]>
- call clocksource_probe()
- This in turns needs of_clk_init() to be called earlier
Cc: Daniel Lezcano <[email protected]>
Signed-off-by: Noam Camus <[email protected]>
[vgupta: broken off from a bigger patch]
Signed-off-by: Vineet Gupta <[email protected]>
---
Changes v1 -> v2
- Rebased on 4.5-rc6
- Removed now not relevant header from setup.c
v1:
- http://lists.infradead.org/pipermail/linux-snps-arc/2016-February/000448.html
Signed-off-by: Vineet Gupta <[email protected]>
---
arch/arc/Kconfig | 3 ++-
arch/arc/kernel/setup.c | 2 --
arch/arc/kernel/time.c | 5 +++++
3 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index 8a188bc1786a..74689dfde0ae 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -10,8 +10,9 @@ config ARC
def_bool y
select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC
select BUILDTIME_EXTABLE_SORT
- select COMMON_CLK
+ select CLKSRC_OF
select CLONE_BACKWARDS
+ select COMMON_CLK
select GENERIC_ATOMIC64
select GENERIC_CLOCKEVENTS
select GENERIC_FIND_FIRST_BIT
diff --git a/arch/arc/kernel/setup.c b/arch/arc/kernel/setup.c
index cdc821df1809..2dad49c71c09 100644
--- a/arch/arc/kernel/setup.c
+++ b/arch/arc/kernel/setup.c
@@ -13,7 +13,6 @@
#include <linux/console.h>
#include <linux/module.h>
#include <linux/cpu.h>
-#include <linux/clk-provider.h>
#include <linux/of_fdt.h>
#include <linux/of_platform.h>
#include <linux/cache.h>
@@ -459,7 +458,6 @@ void __init setup_arch(char **cmdline_p)
static int __init customize_machine(void)
{
- of_clk_init(NULL);
/*
* Traverses flattened DeviceTree - registering platform devices
* (if any) complete with their resources
diff --git a/arch/arc/kernel/time.c b/arch/arc/kernel/time.c
index e97be743d47b..848353a27ac8 100644
--- a/arch/arc/kernel/time.c
+++ b/arch/arc/kernel/time.c
@@ -34,6 +34,8 @@
#include <linux/kernel.h>
#include <linux/time.h>
#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/cpu.h>
@@ -301,6 +303,9 @@ static void __init arc_clockevent_setup(void)
*/
void __init time_init(void)
{
+ of_clk_init(NULL);
+ clocksource_probe();
+
/*
* sets up the timekeeping free-flowing counter which also returns
* whether the counter is usable as clocksource
--
2.5.0
- Remove explicit clocksource setup and let it be done by OF framework
by defining CLOCKSOURCE_OF_DECLARE() for various timers
- This allows multiple clocksources to be potentially registered
simultaneouly: previously we could only do one - as all of them had
same arc_counter_setup() routine for registration
- Setup routines also ensure that the underlying timer actually exists.
- Remove some of the panic() calls if underlying timer is NOT detected as
fallback clocksource might still be available
1. If GRFC doesn't exist, jiffies clocksource gets registered anyways
2. if RTC doesn't exist, TIMER1 can take over (as it is always
present)
Cc: Rob Herring <[email protected]>
Cc: Noam Camus <[email protected]>
Cc: Daniel Lezcano <[email protected]>
Signed-off-by: Vineet Gupta <[email protected]>
---
Changes v1 -> v2
- Introduce arc_of_timer_init() to handle two instances of [Rob]
snps,arc-timer one for clockevent, other for clksrc
v1:
- http://lists.infradead.org/pipermail/linux-snps-arc/2016-February/000450.html
Signed-off-by: Vineet Gupta <[email protected]>
---
arch/arc/kernel/mcip.c | 4 +-
arch/arc/kernel/setup.c | 3 --
arch/arc/kernel/time.c | 124 +++++++++++++++++++++++++++---------------------
3 files changed, 72 insertions(+), 59 deletions(-)
diff --git a/arch/arc/kernel/mcip.c b/arch/arc/kernel/mcip.c
index c41c364b926c..262d9c3771e6 100644
--- a/arch/arc/kernel/mcip.c
+++ b/arch/arc/kernel/mcip.c
@@ -116,15 +116,13 @@ static void mcip_probe_n_setup(void)
IS_AVAIL1(mp.dbg, "DEBUG "),
IS_AVAIL1(mp.gfrc, "GFRC"));
+ cpuinfo_arc700[0].extn.gfrc = mp.gfrc;
idu_detected = mp.idu;
if (mp.dbg) {
__mcip_cmd_data(CMD_DEBUG_SET_SELECT, 0, 0xf);
__mcip_cmd_data(CMD_DEBUG_SET_MASK, 0xf, 0xf);
}
-
- if (IS_ENABLED(CONFIG_ARC_HAS_GFRC) && !mp.gfrc)
- panic("kernel trying to use non-existent GFRC\n");
}
struct plat_smp_ops plat_smp_ops = {
diff --git a/arch/arc/kernel/setup.c b/arch/arc/kernel/setup.c
index 2dad49c71c09..b2921a3bd924 100644
--- a/arch/arc/kernel/setup.c
+++ b/arch/arc/kernel/setup.c
@@ -323,9 +323,6 @@ static void arc_chk_core_config(void)
if (!cpu->extn.timer1)
panic("Timer1 is not present!\n");
- if (IS_ENABLED(CONFIG_ARC_HAS_RTC) && !cpu->extn.rtc)
- panic("RTC is not present\n");
-
#ifdef CONFIG_ARC_HAS_DCCM
/*
* DCCM can be arbit placed in hardware.
diff --git a/arch/arc/kernel/time.c b/arch/arc/kernel/time.c
index 693545df9827..72f023440739 100644
--- a/arch/arc/kernel/time.c
+++ b/arch/arc/kernel/time.c
@@ -77,12 +77,7 @@ static void noinline arc_get_timer_clk(struct device_node *node)
#ifdef CONFIG_ARC_HAS_GFRC
-static int arc_counter_setup(void)
-{
- return 1;
-}
-
-static cycle_t arc_counter_read(struct clocksource *cs)
+static cycle_t arc_read_gfrc(struct clocksource *cs)
{
unsigned long flags;
union {
@@ -107,15 +102,28 @@ static cycle_t arc_counter_read(struct clocksource *cs)
return stamp.full;
}
-static struct clocksource arc_counter = {
+static struct clocksource arc_counter_gfrc = {
.name = "ARConnect GFRC",
.rating = 400,
- .read = arc_counter_read,
+ .read = arc_read_gfrc,
.mask = CLOCKSOURCE_MASK(64),
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
-#else
+static void __init arc_cs_setup_gfrc(struct device_node *node)
+{
+ int exists = cpuinfo_arc700[0].extn.gfrc;
+
+ if (WARN(!exists, "Global-64-bit-Ctr clocksource not detected"))
+ return;
+
+ arc_get_timer_clk(node);
+
+ clocksource_register_hz(&arc_counter_gfrc, arc_timer_freq);
+}
+CLOCKSOURCE_OF_DECLARE(arc_gfrc, "snps,archs-timer-gfrc", arc_cs_setup_gfrc);
+
+#endif
#ifdef CONFIG_ARC_HAS_RTC
@@ -123,15 +131,7 @@ static struct clocksource arc_counter = {
#define AUX_RTC_LOW 0x104
#define AUX_RTC_HIGH 0x105
-int arc_counter_setup(void)
-{
- write_aux_reg(AUX_RTC_CTRL, 1);
-
- /* Not usable in SMP */
- return !IS_ENABLED(CONFIG_SMP);
-}
-
-static cycle_t arc_counter_read(struct clocksource *cs)
+static cycle_t arc_read_rtc(struct clocksource *cs)
{
unsigned long status;
union {
@@ -155,44 +155,66 @@ static cycle_t arc_counter_read(struct clocksource *cs)
return stamp.full;
}
-static struct clocksource arc_counter = {
+static struct clocksource arc_counter_rtc = {
.name = "ARCv2 RTC",
.rating = 350,
- .read = arc_counter_read,
+ .read = arc_read_rtc,
.mask = CLOCKSOURCE_MASK(64),
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
-#else /* !CONFIG_ARC_HAS_RTC */
-
-/*
- * set 32bit TIMER1 to keep counting monotonically and wraparound
- */
-int arc_counter_setup(void)
+static void __init arc_cs_setup_rtc(struct device_node *node)
{
- write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMER_MAX);
- write_aux_reg(ARC_REG_TIMER1_CNT, 0);
- write_aux_reg(ARC_REG_TIMER1_CTRL, TIMER_CTRL_NH);
+ int exists = cpuinfo_arc700[smp_processor_id()].extn.rtc;
+
+ if (WARN(!exists, "Local-64-bit-Ctr clocksource not detected"))
+ return;
+
+ /* Local to CPU hence not usable in SMP */
+ if (WARN(IS_ENABLED(CONFIG_SMP), "Local-64-bit-Ctr not usable in SMP"))
+ return;
+
+ arc_get_timer_clk(node);
- /* Not usable in SMP */
- return !IS_ENABLED(CONFIG_SMP);
+ write_aux_reg(AUX_RTC_CTRL, 1);
+
+ clocksource_register_hz(&arc_counter_rtc, arc_timer_freq);
}
+CLOCKSOURCE_OF_DECLARE(arc_rtc, "snps,archs-timer-rtc", arc_cs_setup_rtc);
+
+#endif
+
+/*
+ * 32bit TIMER1 to keep counting monotonically and wraparound
+ */
-static cycle_t arc_counter_read(struct clocksource *cs)
+static cycle_t arc_read_timer1(struct clocksource *cs)
{
return (cycle_t) read_aux_reg(ARC_REG_TIMER1_CNT);
}
-static struct clocksource arc_counter = {
+static struct clocksource arc_counter_timer1 = {
.name = "ARC Timer1",
.rating = 300,
- .read = arc_counter_read,
+ .read = arc_read_timer1,
.mask = CLOCKSOURCE_MASK(32),
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
-#endif
-#endif
+static void __init arc_cs_setup_timer1(struct device_node *node)
+{
+ /* Local to CPU hence not usable in SMP */
+ if (IS_ENABLED(CONFIG_SMP))
+ return;
+
+ arc_get_timer_clk(node);
+
+ write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMER_MAX);
+ write_aux_reg(ARC_REG_TIMER1_CNT, 0);
+ write_aux_reg(ARC_REG_TIMER1_CTRL, TIMER_CTRL_NH);
+
+ clocksource_register_hz(&arc_counter_timer1, arc_timer_freq);
+}
/********** Clock Event Device *********/
@@ -312,29 +334,25 @@ static void __init arc_clockevent_setup(struct device_node *node)
enable_percpu_irq(arc_timer_irq, 0);
}
-CLOCKSOURCE_OF_DECLARE(arc_clkevt, "snps,arc-timer", arc_clockevent_setup);
+
+static void __init arc_of_timer_init(struct device_node *np)
+{
+ static int init_count = 0;
+
+ if (!init_count) {
+ init_count = 1;
+ arc_clockevent_setup(np);
+ } else {
+ arc_cs_setup_timer1(np);
+ }
+}
+CLOCKSOURCE_OF_DECLARE(arc_clkevt, "snps,arc-timer", arc_of_timer_init);
/*
* Called from start_kernel() - boot CPU only
- *
- * -Sets up h/w timers as applicable on boot cpu
- * -Also sets up any global state needed for timer subsystem:
- * - for "counting" timer, registers a clocksource, usable across CPUs
- * (provided that underlying counter h/w is synchronized across cores)
*/
void __init time_init(void)
{
of_clk_init(NULL);
clocksource_probe();
-
- /*
- * sets up the timekeeping free-flowing counter which also returns
- * whether the counter is usable as clocksource
- */
- if (arc_counter_setup())
- /*
- * CLK upto 4.29 GHz can be safely represented in 32 bits
- * because Max 32 bit number is 4,294,967,295
- */
- clocksource_register_hz(&arc_counter, arc_timer_freq);
}
--
2.5.0
From: Alexey Brodkin <[email protected]>
For AXS103, certain bitfile configurations may not work with stock
"clock-frequency" specified in DT. Instead of duplicating the DT files, we
fixup the DT in-place.
This used to be done differently - as in top level "clock-frequency" was
read very early from FDT and exported using arc_{get|set}_core_freq()
also used in setting up clockevent/clocksource timers
This homebrew clk API served well for legacy timer probe (non DT)
However TIMERS are now probed from DT and use "core_clk" defined in DT,
and thus can no longer use the top level "clock-frequency".
This change reduces the number of users of ARC clk hack and paves way
for removal.
Signed-off-by: Alexey Brodkin <[email protected]>
[vgupta: broken out of from bigger patch]
Signed-off-by: Vineet Gupta <[email protected]>
Signed-off-by: Vineet Gupta <[email protected]>
---
arch/arc/kernel/setup.c | 12 +++++++-----
arch/arc/plat-axs10x/axs10x.c | 27 +++++++++++++++++++++------
2 files changed, 28 insertions(+), 11 deletions(-)
diff --git a/arch/arc/kernel/setup.c b/arch/arc/kernel/setup.c
index b2921a3bd924..6fff28be695d 100644
--- a/arch/arc/kernel/setup.c
+++ b/arch/arc/kernel/setup.c
@@ -23,7 +23,6 @@
#include <asm/page.h>
#include <asm/irq.h>
#include <asm/unwind.h>
-#include <asm/clk.h>
#include <asm/mach_desc.h>
#include <asm/smp.h>
@@ -229,10 +228,6 @@ static char *arc_cpu_mumbojumbo(int cpu_id, char *buf, int len)
if (tbl->info.id == 0)
n += scnprintf(buf + n, len - n, "UNKNOWN ARC Processor\n");
- n += scnprintf(buf + n, len - n, "CPU speed\t: %u.%02u Mhz\n",
- (unsigned int)(arc_get_core_freq() / 1000000),
- (unsigned int)(arc_get_core_freq() / 10000) % 100);
-
n += scnprintf(buf + n, len - n, "Timers\t\t: %s%s%s%s\nISA Extn\t: ",
IS_AVAIL1(cpu->extn.timer0, "Timer0 "),
IS_AVAIL1(cpu->extn.timer1, "Timer1 "),
@@ -487,6 +482,10 @@ static int show_cpuinfo(struct seq_file *m, void *v)
{
char *str;
int cpu_id = ptr_to_cpu(v);
+ struct device_node *pll = of_find_node_by_name(NULL, "core_clk");
+ u32 freq;
+
+ of_property_read_u32(pll, "clock-frequency", &freq);
if (!cpu_online(cpu_id)) {
seq_printf(m, "processor [%d]\t: Offline\n", cpu_id);
@@ -498,6 +497,9 @@ static int show_cpuinfo(struct seq_file *m, void *v)
goto done;
seq_printf(m, arc_cpu_mumbojumbo(cpu_id, str, PAGE_SIZE));
+ seq_printf(m, "CPU speed\t: %u.%02u Mhz\n",
+ (unsigned int)(freq / 1000000),
+ (unsigned int)(freq / 10000) % 100);
seq_printf(m, "Bogo MIPS\t: %lu.%02lu\n",
loops_per_jiffy / (500000 / HZ),
diff --git a/arch/arc/plat-axs10x/axs10x.c b/arch/arc/plat-axs10x/axs10x.c
index 1b0f0f458a2b..9701c93f315d 100644
--- a/arch/arc/plat-axs10x/axs10x.c
+++ b/arch/arc/plat-axs10x/axs10x.c
@@ -14,10 +14,11 @@
*
*/
+#include <linux/of_fdt.h>
#include <linux/of_platform.h>
+#include <linux/libfdt.h>
#include <asm/asm-offsets.h>
-#include <asm/clk.h>
#include <asm/io.h>
#include <asm/mach_desc.h>
#include <asm/mcip.h>
@@ -389,6 +390,13 @@ axs103_set_freq(unsigned int id, unsigned int fd, unsigned int od)
static void __init axs103_early_init(void)
{
+ int offset = fdt_path_offset(initial_boot_params, "/cpu_card/core_clk");
+ const struct fdt_property *prop = fdt_get_property(initial_boot_params,
+ offset,
+ "clock-frequency",
+ NULL);
+ u32 freq = be32_to_cpu(*(u32*)(prop->data)) / 1000000, orig = freq;
+
/*
* AXS103 configurations for SMP/QUAD configurations share device tree
* which defaults to 90 MHz. However recent failures of Quad config
@@ -401,12 +409,12 @@ static void __init axs103_early_init(void)
#ifdef CONFIG_ARC_MCIP
unsigned int num_cores = (read_aux_reg(ARC_REG_MCIP_BCR) >> 16) & 0x3F;
if (num_cores > 2)
- arc_set_core_freq(50 * 1000000);
+ freq = 50;
else if (num_cores == 2)
- arc_set_core_freq(75 * 1000000);
+ freq = 75;
#endif
- switch (arc_get_core_freq()/1000000) {
+ switch (freq) {
case 33:
axs103_set_freq(1, 1, 1);
break;
@@ -431,11 +439,18 @@ static void __init axs103_early_init(void)
* DT "clock-frequency" might not match with board value.
* Hence update it to match the board value.
*/
- arc_set_core_freq(axs103_get_freq() * 1000000);
+ freq = axs103_get_freq();
break;
}
- pr_info("Freq is %dMHz\n", axs103_get_freq());
+ pr_info("Freq is %dMHz\n", freq);
+
+ /* Patching .dtb in-place with new core clock value */
+ if (freq != orig ) {
+ freq = cpu_to_be32(freq * 1000000);
+ fdt_setprop_inplace(initial_boot_params, offset,
+ "clock-frequency", &freq, sizeof(freq));
+ }
/* Memory maps already config in pre-bootloader */
--
2.5.0
Vineet Gupta <[email protected]> wrote on 08.03.2016 13:26:10:
> From: Alexey Brodkin <[email protected]>
>
> UARTs usually have fixed clock so we're switching to use of
> constant values instead of something derived from core clock
> frequency.
>
> Among other things this will allow us to get rid of
> arc_{get|set}_core_freq() and switch to generic clock
> framework later on.
>
> Cc: Christian Ruppert <[email protected]>
> Signed-off-by: Alexey Brodkin <[email protected]>
> Signed-off-by: Vineet Gupta <[email protected]>
Acked-by: Christian Ruppert <[email protected]>
> ---
> Changes v1 -> v2
> - Base baud TB10x needs to be 166.66 not 166.67 [Christian]
>
> v1:
> - http://lists.infradead.org/pipermail/linux-snps-arc/2016-
> February/000453.html
>
> Signed-off-by: Vineet Gupta <[email protected]>
> ---
> arch/arc/kernel/devtree.c | 6 ++----
> 1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arc/kernel/devtree.c b/arch/arc/kernel/devtree.c
> index 7e844fd8213f..fecbc96df828 100644
> --- a/arch/arc/kernel/devtree.c
> +++ b/arch/arc/kernel/devtree.c
> @@ -28,14 +28,12 @@ unsigned int __init arc_early_base_baud(void)
>
> static void __init arc_set_early_base_baud(unsigned long dt_root)
> {
> - unsigned int core_clk = arc_get_core_freq();
> -
> if (of_flat_dt_is_compatible(dt_root, "abilis,arc-tb10x"))
> - arc_base_baud = core_clk/3;
> + arc_base_baud = 166666666; /* Fixed 166.6MHz clk (TB10x) */
> else if (of_flat_dt_is_compatible(dt_root, "snps,arc-sdp"))
> arc_base_baud = 33333333; /* Fixed 33MHz clk (AXS10x) */
> else
> - arc_base_baud = core_clk;
> + arc_base_baud = 50000000; /* Fixed default 50MHz */
> }
> #else
> #define arc_set_early_base_baud(dt_root)
> --
> 2.5.0
>
On Tuesday 08 March 2016 05:56 PM, Vineet Gupta wrote:
> ARC Timers have historically been probed directly.
> As precursor to start probing Timers thru DT introduce these bindings
> Note that to keep series bisectable, these bindings are not yet used in
> code.
>
> Cc: Daniel Lezcano <[email protected]>
> Cc: Rob Herring <[email protected]>
> Cc: [email protected]
> Signed-off-by: Vineet Gupta <[email protected]>
> ---
> Changes v1 -> v2
> - snps,arc-timer[0-1] folded into single snps-arc-timer [Rob]
> - Node name in DT example fixed: [Rob]
> "timer1: timer_clksrc {" -> timer@1 {
> - Introduced 64bit RTC in skeleton_hs.dtsi [Vineet]
>
> v1:
> - http://lists.infradead.org/pipermail/linux-snps-arc/2016-February/000447.html
>
> Signed-off-by: Vineet Gupta <[email protected]>
Rob, sorry for pinging you sooner than I should. This must be busy time ahead of
merge window. However if you can take a quick look at the DT bindings, we might be
able to squeeze this into 4.6
This code seems to be functionally working well and stable !
> ---
> .../devicetree/bindings/timer/snps,arc-timer.txt | 26 ++++++++++++++++++++++
> .../devicetree/bindings/timer/snps,archs-gfrc.txt | 14 ++++++++++++
> .../devicetree/bindings/timer/snps,archs-rtc.txt | 14 ++++++++++++
> arch/arc/boot/dts/abilis_tb10x.dtsi | 14 ++++++++++++
> arch/arc/boot/dts/skeleton.dtsi | 14 ++++++++++++
> arch/arc/boot/dts/skeleton_hs.dtsi | 20 +++++++++++++++++
> arch/arc/boot/dts/skeleton_hs_idu.dtsi | 14 ++++++++++++
> 7 files changed, 116 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/timer/snps,arc-timer.txt
> create mode 100644 Documentation/devicetree/bindings/timer/snps,archs-gfrc.txt
> create mode 100644 Documentation/devicetree/bindings/timer/snps,archs-rtc.txt
>
> diff --git a/Documentation/devicetree/bindings/timer/snps,arc-timer.txt b/Documentation/devicetree/bindings/timer/snps,arc-timer.txt
> new file mode 100644
> index 000000000000..9e02be24e805
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/timer/snps,arc-timer.txt
> @@ -0,0 +1,26 @@
> +Synopsys ARC Local Timer with Interrupt Capabilities
> +- Found on all ARC CPUs (ARC700/ARCHS)
> +- Can be optionally programmed to interrupt on Limit
> +- Two idential copies TIMER0 and TIMER1 exist in ARC cores and historically
> + TIMER0 used as clockevent provider (true for all ARC cores)
> + TIMER1 used for clocksource (mandatory for ARC700, optional for ARC HS)
> +
> +Required properties:
> +
> +- compatible : should be "snps,arc-timer"
> +- interrupts : single Interrupt going into parent intc
> + (16 for ARCHS cores, 3 for ARC700 cores)
> +- clocks : phandle to the source clock
> +
> +Optional properties:
> +
> +- interrupt-parent : phandle to parent intc
> +
> +Example:
> +
> + timer@0 {
> + compatible = "snps,arc-timer0";
> + interrupts = <3>;
> + interrupt-parent = <&core_intc>;
> + clocks = <&core_clk>;
> + };
> diff --git a/Documentation/devicetree/bindings/timer/snps,archs-gfrc.txt b/Documentation/devicetree/bindings/timer/snps,archs-gfrc.txt
> new file mode 100644
> index 000000000000..aaab100f54e7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/timer/snps,archs-gfrc.txt
> @@ -0,0 +1,14 @@
> +Synopsys ARC Free Running 64-bit Global Timer for ARC HS CPUs
> +- clocksource provider for SMP SoC
> +
> +Required properties:
> +
> +- compatible : should be "snps,archs-gfrc"
> +- clocks : phandle to the source clock
> +
> +Example:
> +
> + timer@1 {
> + compatible = "snps,archs-gfrc";
> + clocks = <&core_clk>;
> + };
> diff --git a/Documentation/devicetree/bindings/timer/snps,archs-rtc.txt b/Documentation/devicetree/bindings/timer/snps,archs-rtc.txt
> new file mode 100644
> index 000000000000..13f756fa1d6d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/timer/snps,archs-rtc.txt
> @@ -0,0 +1,14 @@
> +Synopsys ARC Free Running 64-bit Local Timer for ARC HS CPUs
> +- clocksource provider for UP SoC
> +
> +Required properties:
> +
> +- compatible : should be "snps,archs-rtc"
> +- clocks : phandle to the source clock
> +
> +Example:
> +
> + timer@1 {
> + compatible = "snps,arc-rtc";
> + clocks = <&core_clk>;
> + };
> diff --git a/arch/arc/boot/dts/abilis_tb10x.dtsi b/arch/arc/boot/dts/abilis_tb10x.dtsi
> index cfb5052239a1..eadbe71dfa22 100644
> --- a/arch/arc/boot/dts/abilis_tb10x.dtsi
> +++ b/arch/arc/boot/dts/abilis_tb10x.dtsi
> @@ -35,6 +35,20 @@
> };
> };
>
> + /* TIMER0 with interrupt for clockevent */
> + timer@0 {
> + compatible = "snps,arc-timer";
> + interrupts = <3>;
> + interrupt-parent = <&intc>;
> + clocks = <&cpu_clk>;
> + };
> +
> + /* TIMER1 for free running clocksource */
> + timer@1 {
> + compatible = "snps,arc-timer";
> + clocks = <&cpu_clk>;
> + };
> +
> soc100 {
> #address-cells = <1>;
> #size-cells = <1>;
> diff --git a/arch/arc/boot/dts/skeleton.dtsi b/arch/arc/boot/dts/skeleton.dtsi
> index 296d371a335c..f6109c2feba7 100644
> --- a/arch/arc/boot/dts/skeleton.dtsi
> +++ b/arch/arc/boot/dts/skeleton.dtsi
> @@ -30,6 +30,20 @@
> };
> };
>
> + /* TIMER0 with interrupt for clockevent */
> + timer@0 {
> + compatible = "snps,arc-timer";
> + interrupts = <3>;
> + interrupt-parent = <&core_intc>;
> + clocks = <&core_clk>;
> + };
> +
> + /* TIMER1 for free running clocksource */
> + timer@1 {
> + compatible = "snps,arc-timer";
> + clocks = <&core_clk>;
> + };
> +
> memory {
> device_type = "memory";
> reg = <0x80000000 0x10000000>; /* 256M */
> diff --git a/arch/arc/boot/dts/skeleton_hs.dtsi b/arch/arc/boot/dts/skeleton_hs.dtsi
> index a53876669030..49caeabca37a 100644
> --- a/arch/arc/boot/dts/skeleton_hs.dtsi
> +++ b/arch/arc/boot/dts/skeleton_hs.dtsi
> @@ -25,6 +25,26 @@
> };
> };
>
> + /* TIMER0 with interrupt for clockevent */
> + timer@0 {
> + compatible = "snps,arc-timer";
> + interrupts = <16>;
> + interrupt-parent = <&core_intc>;
> + clocks = <&core_clk>;
> + };
> +
> + /* 64-bit Local RTC: preferred clocksource for UP */
> + timer@1 {
> + compatible = "snps,archs-timer-rtc";
> + clocks = <&core_clk>;
> + };
> +
> + /* TIMER1 for free running clocksource: Fallback if rtc not found */
> + timer@2 {
> + compatible = "snps,arc-timer";
> + clocks = <&core_clk>;
> + };
> +
> memory {
> device_type = "memory";
> reg = <0x80000000 0x10000000>; /* 256M */
> diff --git a/arch/arc/boot/dts/skeleton_hs_idu.dtsi b/arch/arc/boot/dts/skeleton_hs_idu.dtsi
> index 74898d017f7a..7e301ff16200 100644
> --- a/arch/arc/boot/dts/skeleton_hs_idu.dtsi
> +++ b/arch/arc/boot/dts/skeleton_hs_idu.dtsi
> @@ -25,6 +25,20 @@
> };
> };
>
> + /* TIMER0 with interrupt for clockevent */
> + timer@0 {
> + compatible = "snps,arc-timer";
> + interrupts = <16>;
> + interrupt-parent = <&core_intc>;
> + clocks = <&core_clk>;
> + };
> +
> + /* 64-bit Global Free Running Counter */
> + timer@1 {
> + compatible = "snps,archs-timer-gfrc";
> + clocks = <&core_clk>;
> + };
> +
> memory {
> device_type = "memory";
> reg = <0x80000000 0x10000000>; /* 256M */
On Tue, Mar 08, 2016 at 05:56:05PM +0530, Vineet Gupta wrote:
> ARC Timers have historically been probed directly.
> As precursor to start probing Timers thru DT introduce these bindings
> Note that to keep series bisectable, these bindings are not yet used in
> code.
>
> Cc: Daniel Lezcano <[email protected]>
> Cc: Rob Herring <[email protected]>
> Cc: [email protected]
> Signed-off-by: Vineet Gupta <[email protected]>
> ---
> Changes v1 -> v2
> - snps,arc-timer[0-1] folded into single snps-arc-timer [Rob]
> - Node name in DT example fixed: [Rob]
> "timer1: timer_clksrc {" -> timer@1 {
> - Introduced 64bit RTC in skeleton_hs.dtsi [Vineet]
>
> v1:
> - http://lists.infradead.org/pipermail/linux-snps-arc/2016-February/000447.html
>
> Signed-off-by: Vineet Gupta <[email protected]>
> ---
> .../devicetree/bindings/timer/snps,arc-timer.txt | 26 ++++++++++++++++++++++
> .../devicetree/bindings/timer/snps,archs-gfrc.txt | 14 ++++++++++++
> .../devicetree/bindings/timer/snps,archs-rtc.txt | 14 ++++++++++++
> arch/arc/boot/dts/abilis_tb10x.dtsi | 14 ++++++++++++
> arch/arc/boot/dts/skeleton.dtsi | 14 ++++++++++++
> arch/arc/boot/dts/skeleton_hs.dtsi | 20 +++++++++++++++++
> arch/arc/boot/dts/skeleton_hs_idu.dtsi | 14 ++++++++++++
> 7 files changed, 116 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/timer/snps,arc-timer.txt
> create mode 100644 Documentation/devicetree/bindings/timer/snps,archs-gfrc.txt
> create mode 100644 Documentation/devicetree/bindings/timer/snps,archs-rtc.txt
>
> diff --git a/Documentation/devicetree/bindings/timer/snps,arc-timer.txt b/Documentation/devicetree/bindings/timer/snps,arc-timer.txt
> new file mode 100644
> index 000000000000..9e02be24e805
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/timer/snps,arc-timer.txt
> @@ -0,0 +1,26 @@
> +Synopsys ARC Local Timer with Interrupt Capabilities
> +- Found on all ARC CPUs (ARC700/ARCHS)
> +- Can be optionally programmed to interrupt on Limit
> +- Two idential copies TIMER0 and TIMER1 exist in ARC cores and historically
> + TIMER0 used as clockevent provider (true for all ARC cores)
> + TIMER1 used for clocksource (mandatory for ARC700, optional for ARC HS)
> +
> +Required properties:
> +
> +- compatible : should be "snps,arc-timer"
> +- interrupts : single Interrupt going into parent intc
> + (16 for ARCHS cores, 3 for ARC700 cores)
> +- clocks : phandle to the source clock
> +
> +Optional properties:
> +
> +- interrupt-parent : phandle to parent intc
> +
> +Example:
> +
> + timer@0 {
Use of unit addresses without reg property is going to start generating
warnings. I would just use "timer0" in this case.
> + compatible = "snps,arc-timer0";
s/timer0/timer/
> + interrupts = <3>;
> + interrupt-parent = <&core_intc>;
> + clocks = <&core_clk>;
> + };
> diff --git a/Documentation/devicetree/bindings/timer/snps,archs-gfrc.txt b/Documentation/devicetree/bindings/timer/snps,archs-gfrc.txt
> new file mode 100644
> index 000000000000..aaab100f54e7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/timer/snps,archs-gfrc.txt
> @@ -0,0 +1,14 @@
> +Synopsys ARC Free Running 64-bit Global Timer for ARC HS CPUs
> +- clocksource provider for SMP SoC
> +
> +Required properties:
> +
> +- compatible : should be "snps,archs-gfrc"
> +- clocks : phandle to the source clock
> +
> +Example:
> +
> + timer@1 {
> + compatible = "snps,archs-gfrc";
> + clocks = <&core_clk>;
> + };
> diff --git a/Documentation/devicetree/bindings/timer/snps,archs-rtc.txt b/Documentation/devicetree/bindings/timer/snps,archs-rtc.txt
> new file mode 100644
> index 000000000000..13f756fa1d6d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/timer/snps,archs-rtc.txt
> @@ -0,0 +1,14 @@
> +Synopsys ARC Free Running 64-bit Local Timer for ARC HS CPUs
> +- clocksource provider for UP SoC
> +
> +Required properties:
> +
> +- compatible : should be "snps,archs-rtc"
> +- clocks : phandle to the source clock
> +
> +Example:
> +
> + timer@1 {
rtc {
And then similar updates in the dts files.
> + compatible = "snps,arc-rtc";
> + clocks = <&core_clk>;
> + };
ARC Timers have historically been probed directly.
As precursor to start probing Timers thru DT introduce these bindings
Note that to keep series bisectable, these bindings are not yet used in
code.
Cc: Daniel Lezcano <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: [email protected]
Signed-off-by: Vineet Gupta <[email protected]>
---
v3:
- Renamed Node name to avoid new warnings when unit address used w/o regs [Rob]
v2:
- http://lists.infradead.org/pipermail/linux-snps-arc/2016-March/000653.html
- snps,arc-timer[0-1] folded into single snps-arc-timer [Rob]
- Node name in DT example fixed: [Rob]
"timer1: timer_clksrc {" -> timer@1 {
- Introduced 64bit RTC in skeleton_hs.dtsi [Vineet]
v1:
- http://lists.infradead.org/pipermail/linux-snps-arc/2016-February/000447.html
---
.../devicetree/bindings/timer/snps,arc-timer.txt | 32 ++++++++++++++++++++++
.../devicetree/bindings/timer/snps,archs-gfrc.txt | 14 ++++++++++
.../devicetree/bindings/timer/snps,archs-rtc.txt | 14 ++++++++++
arch/arc/boot/dts/abilis_tb10x.dtsi | 14 ++++++++++
arch/arc/boot/dts/skeleton.dtsi | 14 ++++++++++
arch/arc/boot/dts/skeleton_hs.dtsi | 20 ++++++++++++++
arch/arc/boot/dts/skeleton_hs_idu.dtsi | 14 ++++++++++
7 files changed, 122 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/snps,arc-timer.txt
create mode 100644 Documentation/devicetree/bindings/timer/snps,archs-gfrc.txt
create mode 100644 Documentation/devicetree/bindings/timer/snps,archs-rtc.txt
diff --git a/Documentation/devicetree/bindings/timer/snps,arc-timer.txt b/Documentation/devicetree/bindings/timer/snps,arc-timer.txt
new file mode 100644
index 000000000000..29ba64432ad7
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/snps,arc-timer.txt
@@ -0,0 +1,32 @@
+Synopsys ARC Local Timer with Interrupt Capabilities
+- Found on all ARC CPUs (ARC700/ARCHS)
+- Can be optionally programmed to interrupt on Limit
+- Two idential copies TIMER0 and TIMER1 exist in ARC cores and historically
+ TIMER0 used as clockevent provider (true for all ARC cores)
+ TIMER1 used for clocksource (mandatory for ARC700, optional for ARC HS)
+
+Required properties:
+
+- compatible : should be "snps,arc-timer"
+- interrupts : single Interrupt going into parent intc
+ (16 for ARCHS cores, 3 for ARC700 cores)
+- clocks : phandle to the source clock
+
+Optional properties:
+
+- interrupt-parent : phandle to parent intc
+
+Example:
+
+ timer0 {
+ compatible = "snps,arc-timer";
+ interrupts = <3>;
+ interrupt-parent = <&core_intc>;
+ clocks = <&core_clk>;
+ };
+
+
+ timer1 {
+ compatible = "snps,arc-timer";
+ clocks = <&core_clk>;
+ };
diff --git a/Documentation/devicetree/bindings/timer/snps,archs-gfrc.txt b/Documentation/devicetree/bindings/timer/snps,archs-gfrc.txt
new file mode 100644
index 000000000000..b6cd1b3922de
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/snps,archs-gfrc.txt
@@ -0,0 +1,14 @@
+Synopsys ARC Free Running 64-bit Global Timer for ARC HS CPUs
+- clocksource provider for SMP SoC
+
+Required properties:
+
+- compatible : should be "snps,archs-gfrc"
+- clocks : phandle to the source clock
+
+Example:
+
+ gfrc {
+ compatible = "snps,archs-gfrc";
+ clocks = <&core_clk>;
+ };
diff --git a/Documentation/devicetree/bindings/timer/snps,archs-rtc.txt b/Documentation/devicetree/bindings/timer/snps,archs-rtc.txt
new file mode 100644
index 000000000000..47bd7a702f3f
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/snps,archs-rtc.txt
@@ -0,0 +1,14 @@
+Synopsys ARC Free Running 64-bit Local Timer for ARC HS CPUs
+- clocksource provider for UP SoC
+
+Required properties:
+
+- compatible : should be "snps,archs-rtc"
+- clocks : phandle to the source clock
+
+Example:
+
+ rtc {
+ compatible = "snps,arc-rtc";
+ clocks = <&core_clk>;
+ };
diff --git a/arch/arc/boot/dts/abilis_tb10x.dtsi b/arch/arc/boot/dts/abilis_tb10x.dtsi
index cfb5052239a1..663671f22680 100644
--- a/arch/arc/boot/dts/abilis_tb10x.dtsi
+++ b/arch/arc/boot/dts/abilis_tb10x.dtsi
@@ -35,6 +35,20 @@
};
};
+ /* TIMER0 with interrupt for clockevent */
+ timer0 {
+ compatible = "snps,arc-timer";
+ interrupts = <3>;
+ interrupt-parent = <&intc>;
+ clocks = <&cpu_clk>;
+ };
+
+ /* TIMER1 for free running clocksource */
+ timer1 {
+ compatible = "snps,arc-timer";
+ clocks = <&cpu_clk>;
+ };
+
soc100 {
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/arc/boot/dts/skeleton.dtsi b/arch/arc/boot/dts/skeleton.dtsi
index 296d371a335c..3a10cc633e2b 100644
--- a/arch/arc/boot/dts/skeleton.dtsi
+++ b/arch/arc/boot/dts/skeleton.dtsi
@@ -30,6 +30,20 @@
};
};
+ /* TIMER0 with interrupt for clockevent */
+ timer0 {
+ compatible = "snps,arc-timer";
+ interrupts = <3>;
+ interrupt-parent = <&core_intc>;
+ clocks = <&core_clk>;
+ };
+
+ /* TIMER1 for free running clocksource */
+ timer1 {
+ compatible = "snps,arc-timer";
+ clocks = <&core_clk>;
+ };
+
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>; /* 256M */
diff --git a/arch/arc/boot/dts/skeleton_hs.dtsi b/arch/arc/boot/dts/skeleton_hs.dtsi
index a53876669030..71fd308a9298 100644
--- a/arch/arc/boot/dts/skeleton_hs.dtsi
+++ b/arch/arc/boot/dts/skeleton_hs.dtsi
@@ -25,6 +25,26 @@
};
};
+ /* TIMER0 with interrupt for clockevent */
+ timer0 {
+ compatible = "snps,arc-timer";
+ interrupts = <16>;
+ interrupt-parent = <&core_intc>;
+ clocks = <&core_clk>;
+ };
+
+ /* 64-bit Local RTC: preferred clocksource for UP */
+ rtc {
+ compatible = "snps,archs-timer-rtc";
+ clocks = <&core_clk>;
+ };
+
+ /* TIMER1 for free running clocksource: Fallback if rtc not found */
+ timer1 {
+ compatible = "snps,arc-timer";
+ clocks = <&core_clk>;
+ };
+
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>; /* 256M */
diff --git a/arch/arc/boot/dts/skeleton_hs_idu.dtsi b/arch/arc/boot/dts/skeleton_hs_idu.dtsi
index 74898d017f7a..d1cb25a66989 100644
--- a/arch/arc/boot/dts/skeleton_hs_idu.dtsi
+++ b/arch/arc/boot/dts/skeleton_hs_idu.dtsi
@@ -25,6 +25,20 @@
};
};
+ /* TIMER0 with interrupt for clockevent */
+ timer0 {
+ compatible = "snps,arc-timer";
+ interrupts = <16>;
+ interrupt-parent = <&core_intc>;
+ clocks = <&core_clk>;
+ };
+
+ /* 64-bit Global Free Running Counter */
+ gfrc {
+ compatible = "snps,archs-timer-gfrc";
+ clocks = <&core_clk>;
+ };
+
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>; /* 256M */
--
2.5.0
On Fri, Mar 18, 2016 at 10:56:29AM +0530, Vineet Gupta wrote:
> ARC Timers have historically been probed directly.
> As precursor to start probing Timers thru DT introduce these bindings
> Note that to keep series bisectable, these bindings are not yet used in
> code.
>
> Cc: Daniel Lezcano <[email protected]>
> Cc: Rob Herring <[email protected]>
> Cc: [email protected]
> Signed-off-by: Vineet Gupta <[email protected]>
> ---
> v3:
> - Renamed Node name to avoid new warnings when unit address used w/o regs [Rob]
> v2:
> - http://lists.infradead.org/pipermail/linux-snps-arc/2016-March/000653.html
> - snps,arc-timer[0-1] folded into single snps-arc-timer [Rob]
> - Node name in DT example fixed: [Rob]
> "timer1: timer_clksrc {" -> timer@1 {
> - Introduced 64bit RTC in skeleton_hs.dtsi [Vineet]
> v1:
> - http://lists.infradead.org/pipermail/linux-snps-arc/2016-February/000447.html
> ---
> .../devicetree/bindings/timer/snps,arc-timer.txt | 32 ++++++++++++++++++++++
> .../devicetree/bindings/timer/snps,archs-gfrc.txt | 14 ++++++++++
> .../devicetree/bindings/timer/snps,archs-rtc.txt | 14 ++++++++++
> arch/arc/boot/dts/abilis_tb10x.dtsi | 14 ++++++++++
> arch/arc/boot/dts/skeleton.dtsi | 14 ++++++++++
> arch/arc/boot/dts/skeleton_hs.dtsi | 20 ++++++++++++++
> arch/arc/boot/dts/skeleton_hs_idu.dtsi | 14 ++++++++++
> 7 files changed, 122 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/timer/snps,arc-timer.txt
> create mode 100644 Documentation/devicetree/bindings/timer/snps,archs-gfrc.txt
> create mode 100644 Documentation/devicetree/bindings/timer/snps,archs-rtc.txt
Acked-by: Rob Herring <[email protected]>
On Sunday 20 March 2016 06:12 AM, Rob Herring wrote:
> On Fri, Mar 18, 2016 at 10:56:29AM +0530, Vineet Gupta wrote:
>> ARC Timers have historically been probed directly.
>> As precursor to start probing Timers thru DT introduce these bindings
>> Note that to keep series bisectable, these bindings are not yet used in
>> code.
>>
>> Cc: Daniel Lezcano <[email protected]>
>> Cc: Rob Herring <[email protected]>
>> Cc: [email protected]
>> Signed-off-by: Vineet Gupta <[email protected]>
>> ---
>> v3:
>> - Renamed Node name to avoid new warnings when unit address used w/o regs [Rob]
>> v2:
>> - http://lists.infradead.org/pipermail/linux-snps-arc/2016-March/000653.html
>> - snps,arc-timer[0-1] folded into single snps-arc-timer [Rob]
>> - Node name in DT example fixed: [Rob]
>> "timer1: timer_clksrc {" -> timer@1 {
>> - Introduced 64bit RTC in skeleton_hs.dtsi [Vineet]
>> v1:
>> - http://lists.infradead.org/pipermail/linux-snps-arc/2016-February/000447.html
>> ---
>> .../devicetree/bindings/timer/snps,arc-timer.txt | 32 ++++++++++++++++++++++
>> .../devicetree/bindings/timer/snps,archs-gfrc.txt | 14 ++++++++++
>> .../devicetree/bindings/timer/snps,archs-rtc.txt | 14 ++++++++++
>> arch/arc/boot/dts/abilis_tb10x.dtsi | 14 ++++++++++
>> arch/arc/boot/dts/skeleton.dtsi | 14 ++++++++++
>> arch/arc/boot/dts/skeleton_hs.dtsi | 20 ++++++++++++++
>> arch/arc/boot/dts/skeleton_hs_idu.dtsi | 14 ++++++++++
>> 7 files changed, 122 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/timer/snps,arc-timer.txt
>> create mode 100644 Documentation/devicetree/bindings/timer/snps,archs-gfrc.txt
>> create mode 100644 Documentation/devicetree/bindings/timer/snps,archs-rtc.txt
> Acked-by: Rob Herring <[email protected]>
Thx a bunch Rob !
-Vineet